CN105024699B - Double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion - Google Patents
Double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion Download PDFInfo
- Publication number
- CN105024699B CN105024699B CN201410167280.5A CN201410167280A CN105024699B CN 105024699 B CN105024699 B CN 105024699B CN 201410167280 A CN201410167280 A CN 201410167280A CN 105024699 B CN105024699 B CN 105024699B
- Authority
- CN
- China
- Prior art keywords
- digital
- switching capacity
- integrator
- time
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Analogue/Digital Conversion (AREA)
Abstract
Double slope integrating analog to digital converter the present invention is based on switching capacity feedback digital-to-analogue conversion include the integrator for feeding back D/A converter module by switching capacity and capacitance is formed, amplifier, comparator, digital control and counting module, switching capacity feeds back D/A converter module, input signal is added in feeds back D/A converter module by switching capacity, on the integrator that capacitance is formed, it is digital control to be started counting up with counting module, after the predetermined time, control switching capacity feedback D/A converter module by a reversed polarity reference voltage loading on capacitance, the stored charge of integrator is directly proportional in the average value of this period with input at this time, the integration of reference voltage is the backslash slope that slope is VREF/RC, it is digital control at this time to be counted with counting module from 0, when integrator output reaches 0, it counts and stops, reset analog circuit.The present invention fails after solving the problems, such as integrator saturation, reduces error of the electric current in nA or pA ranks, also reduces the area of chip.
Description
Technical field
The invention belongs to electronic circuit fields, relate more specifically to a kind of double slopes based on switching capacity feedback digital-to-analogue conversion
Integrating analog to digital converter.
Background technology
Integral analogue-to-digital converter has a wide range of applications in low speed, field of high-precision measurement, particularly in digital instrument
Fields of measurement integral analogue-to-digital converter has two kinds of conversion regimes of simple integral and double integrator, and the work of simple integral analog-digital converter is former
Reason is that the electric signal that will be converted first becomes interval of time, is then counted again to time interval, so as to indirectly simulation
Amount is converted into a kind of conversion method of digital quantity, its major defect is that conversion accuracy is not high, is mainly occurred by ramp voltage
The influence of device, comparator precision and clock pulses stability, in order to improve integral analogue-to-digital converter under similarity condition
Conversion accuracy, can be used double integrator type analog-to-digital converter, and dual integ ration ADC passes through accumulating twice to analog input signal
Point, partial offset is due to error caused by ramp generator, the improve conversion accuracy " spy of double integrator type analog-to-digital converter
Point is shown：Precision is higher, can reach 22；Strong antijamming capability due to the effect of integrating capacitor, can substantially restrain height
Frequency noise.But its conversion speed is slower, conversion accuracy is reduced with the increase of conversion rate, so this converter master
Apply the conversion art in low speed, such as fields of measurement.
The emphasis of dual integ ration ADC is exactly its internal integrator, and the performance of integrator will see amplifier certainly,
Further, the BUFFER that buffer action is played in system also has an impact the performance of system.
The structure of specific double integrator type analog-to-digital converter is as shown in Figure 1, input signal is added on integrator, unison counter
It starts counting up.In the scheduled time（T）Afterwards, the reference voltage of a reversed polarity is added on integrator.The accumulation of integrator at this time
Charge and input are in this period（T）Average value it is directly proportional.The integration of reference voltage is the backslash slope that slope is VREF/RC.
This hour counter counts again from 0.When integrator output reaches 0, count and stop, resetting analog circuit.Because the increase of charge
It is directly proportional with VIN × T, and the charge of same amount loss is directly proportional with VREF × tx, the result is that relative to full-scale counting
Value is directly proportional with tx/T=VIN/VREF.If the output of counter is binary number, here it is the binary numbers of input voltage
Expression.
Traditional double slope integrating analog to digital converter existing defects when measuring high-precision current sensor and coming：1. electric current
It is difficult to carry out signal processing again after being converted into voltage in nA or pA ranks；2. R（Resistance）And C（Capacitance）The integrator of formation
Saturation state is easily entered when curent change is bigger, analog-digital converter loses function；After 3. resistance or capacitance are too big
It can not be integrated on the chip of very little, especially on cell phone type chip.
Invention content
1st, the purpose of the present invention.
The present invention is in order to solve failure and chip area mistake after error of the electric current in nA or pA ranks, integrator saturation
The problem of big, and propose a kind of double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion.
2nd, the technical solution adopted in the present invention.
Based on double slope integrating analog to digital converter of switching capacity feedback digital-to-analogue conversion, including being turned by switching capacity feedback digital-to-analogue
It changes the mold integrator, amplifier, comparator, digital control and counting module, switching capacity that block and capacitance are formed and feeds back digital-to-analogue turn
Block is changed the mold, input signal is added on the integrator being made of switching capacity feedback D/A converter module, capacitance, digital control with counting
Digital-to-analogue BOB(beginning of block) counts, and after the predetermined time, control switching capacity feeds back D/A converter module by a reversed polarity reference voltage
Loading on capacitance, at this time the stored charge of integrator and input this period average value it is directly proportional, the product of reference voltage
Divide the backslash slope for being slope for VREF/RC, it is digital control at this time to be counted with counting module from 0, when integrator output reaches 0,
It counts and stops, resetting analog circuit.
Further, the preset time is to be regulated and controled by digital control with counting module, so as to control the time of integration.
Further, the increase of the charge of integrator and input voltage × time are directly proportional, and the charge of same amount lose and
Contrast potential × contrast potential time is directly proportional, the result is that relative to full-scale count value and contrast potential input time/
Input voltage time=input voltage/contrast potential is directly proportional.
Further, the digital control output with counting module is binary number.
Further, it is stored when on capacitance when carrying out integration and anti-integration, offset voltage is offset.
Further, the comparator detects zero crossing to judge whether anti-integral process is tied when anti-integration
Beam.
Further, bandwidth is determined by the speed of the comparator.
3rd, beneficial effects of the present invention.
（1）The present invention makes the capacitance C of integrator very little also unsaturated by regulating and controlling the time of integration, solves integrator and satisfies
The problem of with rear failure.
（2）Present invention switching capacity feeds back the size that D/A converter module reduces traditional quadrature device resistance R, reduces electricity
The error in nA or pA ranks is flowed, also reduces the area of chip.
Description of the drawings
Fig. 1 circuit diagrams in the prior art.
Fig. 2 is the circuit diagram of the present invention.
Specific embodiment
In order to enable the auditor of the Patent Office especially public that the technical spirit of the present invention is more clearly understood and have
Beneficial effect, applicant will elaborate by way of examples below, but be not to this hair to the description of embodiment
The limitation of bright scheme, the made only formal but not substantive equivalent transformation of any design according to the present invention all should
It is considered as technical scheme of the present invention scope.
Embodiment 1
Based on double slope integrating analog to digital converter of switching capacity feedback digital-to-analogue conversion, including being turned by switching capacity feedback digital-to-analogue
It changes the mold integrator, amplifier, comparator, digital control and counting module, switching capacity that block and capacitance are formed and feeds back digital-to-analogue turn
Block is changed the mold, input signal is added on the integrator being made of switching capacity feedback D/A converter module, capacitance, digital control with counting
Digital-to-analogue BOB(beginning of block) counts, and after the predetermined time, control switching capacity feeds back D/A converter module by a reversed polarity reference voltage
Loading on capacitance, at this time the stored charge of integrator and input this period average value it is directly proportional, the product of reference voltage
Divide the backslash slope for being slope for VREF/RC, it is digital control at this time to be counted with counting module from 0, when integrator output reaches 0,
It counts and stops, resetting analog circuit.
Embodiment 2
Based on double slope integrating analog to digital converter of switching capacity feedback digital-to-analogue conversion, including being turned by switching capacity feedback digital-to-analogue
It changes the mold integrator, amplifier, comparator, digital control and counting module, switching capacity that block and capacitance are formed and feeds back digital-to-analogue turn
Block is changed the mold, input signal is added on the integrator being made of switching capacity feedback D/A converter module, capacitance, digital control with counting
Digital-to-analogue BOB(beginning of block) counts, and after the predetermined time, control switching capacity feeds back D/A converter module by a reversed polarity reference voltage
Loading on capacitance, at this time the stored charge of integrator and input this period average value it is directly proportional, the product of reference voltage
Divide the backslash slope for being slope for VREF/RC, it is digital control at this time to be counted with counting module from 0, when integrator output reaches 0,
It counts and stops, resetting analog circuit.
The preset time is to be regulated and controled by digital control with counting module, so as to control the time of integration.The electricity of integrator
The increase of lotus and input voltage × time are directly proportional, and the charge of same amount is lost and contrast potential × contrast potential time into just
Than the result is that relative to full-scale count value and contrast potential input time/input voltage time=input voltage/comparison electricity
It is pressed into direct ratio.The digital control output with counting module is binary number.It is stored on capacitance when carrying out integration and anti-integration
When, offset voltage is offset.The comparator detects zero crossing to judge whether anti-integral process terminates when anti-integration.
Bandwidth is determined by the speed of the comparator.
Claims (6)
1. a kind of double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion, it is characterised in that：Including by switching
Integrator, amplifier, comparator, the digital control and counting module that capacitive feedback D/A converter module and capacitance are formed, input
Signal is added on the integrator being made of switching capacity feedback D/A converter module, capacitance, digital control to start with counting module
It counts, after the predetermined time, control switching capacity feedback D/A converter module is by a reversed polarity reference voltage loading in capacitance
On, the stored charge of integrator is directly proportional in the time average of this period with input at this time, and the integration of reference voltage is oblique
Voltage on the basis of rate/（Resistance * capacitances）Backslash slope, it is digital control at this time to be started counting up with counting module from 0, when integrator is defeated
It when going out to reach 0, counts and stops, resetting analog circuit.
2. double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion according to claim 1, special
Sign is：The signal integration time according to input current signal size, is regulated and controled by digital control with counting module.
3. double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion according to claim 1 or 2,
It is characterized in that：The increase of the charge of integrator and input voltage × time are directly proportional, and the charge of same amount is lost and comparison
Voltage × contrast potential time is directly proportional, the result is that relative to full-scale count value and contrast potential input time/defeated
It is directly proportional to enter voltage time=input voltage/contrast potential.
4. double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion according to claim 1, special
Sign is：The digital control output with counting module is binary number.
5. double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion according to claim 1, special
Sign is：The comparator judges whether anti-integral process terminates when anti-integration by detecting zero crossing.
6. double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion according to claim 1, special
Sign is：Bandwidth is determined by the speed of the comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410167280.5A CN105024699B (en) | 2014-04-24 | 2014-04-24 | Double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410167280.5A CN105024699B (en) | 2014-04-24 | 2014-04-24 | Double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105024699A CN105024699A (en) | 2015-11-04 |
| CN105024699B true CN105024699B (en) | 2018-06-29 |
Family
ID=54414453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410167280.5A Active CN105024699B (en) | 2014-04-24 | 2014-04-24 | Double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105024699B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105811987B (en) * | 2016-03-09 | 2022-12-09 | 广州龙之杰科技有限公司 | Single-integration analog-to-digital converter and conversion method thereof |
| CN106899297B (en) * | 2017-01-17 | 2020-05-19 | 华中科技大学 | Memristor-based AD conversion circuit |
| KR102632360B1 (en) * | 2019-07-03 | 2024-02-02 | 삼성전기주식회사 | Dual slope analog to digital converter with parallel counting structure |
| CN113346896B (en) * | 2021-04-27 | 2022-09-02 | 北京航空航天大学 | Charge integrating and counting type circuit and analog storage and calculation integrated structure |
| CN113839677B (en) * | 2021-08-31 | 2024-02-02 | 中国计量大学 | Integral analog-to-digital converter and analog-to-digital conversion method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6411247B2 (en) * | 2000-06-09 | 2002-06-25 | Oki Electric Industry Co., Ltd. | Analog/digital converter |
| US7471231B2 (en) * | 2007-04-24 | 2008-12-30 | Forza Silicon Corporation | Column parallel readout with a differential sloped A/D converter |
| CN101860367A (en) * | 2010-06-25 | 2010-10-13 | 房慧龙 | High-precision fast-integration type AD (Analog-Digital) converter based on single chip microcomputer |
| CN102394651A (en) * | 2011-09-01 | 2012-03-28 | 徐州师范大学 | Programmable double integral type 32-bit ADC (analog-to-digital converter) |
-
2014
- 2014-04-24 CN CN201410167280.5A patent/CN105024699B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6411247B2 (en) * | 2000-06-09 | 2002-06-25 | Oki Electric Industry Co., Ltd. | Analog/digital converter |
| US7471231B2 (en) * | 2007-04-24 | 2008-12-30 | Forza Silicon Corporation | Column parallel readout with a differential sloped A/D converter |
| CN101860367A (en) * | 2010-06-25 | 2010-10-13 | 房慧龙 | High-precision fast-integration type AD (Analog-Digital) converter based on single chip microcomputer |
| CN102394651A (en) * | 2011-09-01 | 2012-03-28 | 徐州师范大学 | Programmable double integral type 32-bit ADC (analog-to-digital converter) |
Non-Patent Citations (1)
| Title |
|---|
| 双斜率积分ADC中开关电容积分器的设计;张鹏南 等;《黑龙江科技学院学报》;20110930;第21卷(第5期);第404-407页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105024699A (en) | 2015-11-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105024699B (en) | Double slope integrating analog to digital converter based on switching capacity feedback digital-to-analogue conversion | |
| TWI651930B (en) | Capacitive proximity detection using delta-sigma conversion | |
| US9529030B2 (en) | Capacitance sensing circuits and methods | |
| Jung et al. | 27.6 A 0.7 pF-to-10nF fully digital capacitance-to-digital converter using iterative delay-chain discharge | |
| US7667468B1 (en) | Capacitive sensor with ratiometric voltage references | |
| CN103207560B (en) | The time of integration and/or capacitance measurement system, method and apparatus | |
| CN102193033B (en) | Self-capacitance change measuring circuit with quick response | |
| US20140146002A1 (en) | Touch Detection System of Terminal Device and Terminal Device | |
| CN204462255U (en) | Apparatus for measuring capacitance capacity | |
| CN103034117B (en) | High-precision time meter | |
| CN103957010A (en) | High-precision analog-to-digital converter and analog-to-digital conversion method | |
| CN105629061A (en) | Precise frequency measurement device based on high-stability wide reference pulse | |
| CN102832915A (en) | Programmable power-on reset system | |
| US9100043B2 (en) | Method and circuit for an analog digital capacitance converter | |
| US20140354460A1 (en) | Pulse generator and analog-digital converter including the same | |
| CN106707009A (en) | Wide-range high-precision current statistics circuit | |
| CN101865951A (en) | Anti-interference frequency measuring method | |
| CN103308773A (en) | Mutual capacitance variation measuring circuit with high precision and low power consumption | |
| CN103440073A (en) | Capacitor sensing circuit for excluding effect of parasitic capacitor | |
| CN104460303B (en) | A kind of high resolution time interval measurement apparatus with temperature compensation function | |
| CN104300985A (en) | Integral-type AD converting circuit and method based on pulse counting | |
| CN203942513U (en) | Adjustable high precision fractional frequency division circuit based on FPGA | |
| CN203535119U (en) | Capacitance detection circuit | |
| CN108037358B (en) | Single-chip microcomputer frequency testing system and method | |
| CN203658463U (en) | Digital frequency meter based on DSP |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20181016 Address after: 201800 room 409, 811 Ping Cheng Road, Jiading District, Shanghai. Patentee after: SHANGHAI SIMAX TECHNOLOGY CO., LTD. Address before: 215500 Room 308, Southeast University Science and Technology Park, Changshou City hi tech Industrial Development Zone, Suzhou, Jiangsu Patentee before: SUZHOU MAIYUE INFORMATION TECHNOLOGY CO., LTD. |
|
| TR01 | Transfer of patent right |