CN102394598A - Single event upset resistant synchronously resettable D flip-flop - Google Patents
Single event upset resistant synchronously resettable D flip-flop Download PDFInfo
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- CN102394598A CN102394598A CN2011103237918A CN201110323791A CN102394598A CN 102394598 A CN102394598 A CN 102394598A CN 2011103237918 A CN2011103237918 A CN 2011103237918A CN 201110323791 A CN201110323791 A CN 201110323791A CN 102394598 A CN102394598 A CN 102394598A
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Abstract
The invention discloses a single event upset resistant synchronously resettable D flip-flop, aiming at improving the single event upset resistance of a resettable D flip-flop. The D flip-flop is composed of a clock circuit, a master latch, a slave latch, a first inverter circuit and a second inverter circuit, wherein the master latch is composed of 12 PMOS (P-channel Metal Oxide Semiconductor) FETs (Field Effect Transistors) and 12 NMOS (N-channel Metal Oxide Semiconductor) FETs, the slave latch is composed of 10 PMOS FETs and 10 NMOS FETs, duplication redundant reinforcement is performed on the master latch and the slave latch, and the C2MOS (Clocked Complementary Metal Oxide Semiconductor) circuit structures of the master latch and the slave latch are improved, i.e. a pull-up circuit and a pull-down circuit in the mutually redundant C2MOS circuits are separated from the master latch, and a pull-up PMOS FET and a pull-down NMOS FET in the mutually redundant C2MOS circuits are separated from the slave latch. The single event upset resistant resettable D flip-flop disclosed by the invention has strong single event upset resistance, is suitable for a standard cell library of a single event upset resistance reinforced integrated circuit, and is applied to the fields of aviation, aerospace and the like.
Description
Technical field
The present invention relates to a kind of principal and subordinate's d type flip flop that has the synchronous reset structure, particularly a kind of anti-single particle overturn (signal event upset) but the synchronous reset d type flip flop.
Background technology
In the cosmic space, there are a large amount of high energy particles (proton, electronics, heavy ion) and charged particle.After integrated circuit receives the bombardment of these high energy particles and charged particle, can produce electronic impulse in the integrated circuit, the original level of IC interior node is overturn, this effect is called single-particle inversion (SEU).LET (linear energy transfer) value of single-particle bombardment integrated circuit is high more, and the electronic impulse of generation is strong more.The integrated circuit that uses in the Aeronautics and Astronautics field all can receive the threat of single-particle inversion, makes the integrated circuit job insecurity, even produces fatal mistake, and therefore exploitation advanced person's integrated circuit anti-single particle overturn reinforcement technique is particularly important.
The anti-single particle overturn reinforcement technique of integrated circuit can be divided into system-level reinforcing, circuit stages is reinforced and device level is reinforced.The IC reliability of system-level reinforcing is high, but chip area is big, power consumption is big, the speed of service is slow.The integrated circuit speed of service that device level is reinforced is fast, and chip area is little, low in energy consumption, but the device level reinforcing realizes that difficulty is big, and cost is high.The IC reliability that circuit stages is reinforced is high; Chip area, power consumption and the speed of service are superior to the integrated circuit of system-level reinforcing; And realizing the integrated circuit that difficulty and cost are reinforced less than device level, is crucial integrated circuit anti-single particle overturn reinforcement means.
D type flip flop is to use one of maximum unit in the sequential logical circuit, and its anti-single particle overturn ability has directly determined the anti-single particle overturn ability of integrated circuit.D type flip flop is carried out circuit stages reinforce the anti-single particle overturn ability that can under less chip area, power consumption and cost, improve integrated circuit effectively.
Traditional d type flip flop is principal and subordinate's d type flip flop, generally constitutes by the main latch with from the level series of latches, and it is the effective ways of realizing that the d type flip flop anti-single particle is reinforced that the anti-single particle overturn of latch is reinforced." the Upset Hardened Memory Design for Submicron CMOS Technology " that people such as T.Clain deliver on IEEE Transaction on Nuclear Science (IEEE atomic energy science journal) (memory cell design is reinforced in the upset under sub-micron CMOS technology) (roll up by the 6th phases 43 of December in 1996; The 2874th～2878 page) a kind of redundant latch of reinforcing proposed; This latch has increased an inverter and a feedback loop on the basis of classical latch structure, with original inverter and feedback loop redundant circuit each other.The input of N pipe separates with the input of P pipe in the inverter, connects two feedback loops respectively, C in the feedback loop
2The input that the N of MOS circuit pipe and P manage is respectively from the output of two inverters.The signal input and the signal of this latch are preserved by C
2The control of MOS clock circuit.The latch advantage that this redundancy is reinforced is: the upset level that produces when bombarding a node can return to original state through the correct level of corresponding node in its redundant circuit.The deficiency of the latch that this redundancy is reinforced is: two redundant each other C of input
2Draw PMOS pipe and a pull-down NMOS pipe on shared one of the MOS circuit, make C in the feedback loop
2There is an indirect path between the output node of MOS circuit and the redundant circuit corresponding node, when the single-particle bombardment makes this C
2The level upset of MOS circuit output node; Then this upset level can propagate into the corresponding node of redundant circuit along indirect path; If the LET value of single-particle bombardment is higher, then the level upset all can take place in two redundant each other circuit, and the output of latch is also overturn.The d type flip flop of the redundant reinforcing of forming by the redundant series of latches of reinforcing of two these kinds of tradition; When the LET value of single-particle bombardment higher; Then the level upset also all can take place in two redundant each other circuit, and the output of the redundant d type flip flop of reinforcing of tradition is also overturn." the The DF-DICE Storage Element for Immunity to Soft Errors " that people such as R.Naseer deliver on the 48th IEEE International Midwest Symposium on Circuits and Systems (the 48th IEEE circuit and system's Midwest international conference) (to DF-DICE memory cell of soft error immunity) also proposed the similarly latch of redundant reinforcing of a kind of and above-mentioned latch structure.Two C of this latch input
2The MOS circuit is fully independently, there is not indirect path in corresponding node in two redundant each other circuit, has overcome the weak point of the latch that redundancy that people such as T.Clain propose reinforces.But the latch that the redundancy that people such as R.Naseer propose is reinforced has used passgate structures in feedback loop, and when a node received the single-particle bombardment that upset takes place, its redundant circuit fed back to this node with correct level through transmission gate.Because the noise margin of passgate structures is lower, the signal feedback ability of feedback loop a little less than, when the LET value of single-particle bombardment was higher, feedback loop can not make this node recover correct level, has had a strong impact on this latch anti-single particle overturn ability.The d type flip flop of the redundant reinforcing of forming by the redundant series of latches of reinforcing of two these kinds of tradition; When the LET value of single-particle bombardment is higher; Also can be because of the passgate structures in the feedback loop; Can not make this node recover correct level, having influenced should the redundant d type flip flop anti-single particle overturn ability of reinforcing of tradition.
The patent No. is the d type flip flop that the Chinese patent of CN101499788A discloses a kind of anti-single particle overturn and single-particle transient pulse.This invention is the d type flip flop of a kind of similar in the time sampling structure, comprises two variable connectors, two delay circuits, two shutter circuit and three inverters, has realized that the anti-single particle overturn of d type flip flop is reinforced.Owing to adopt delay circuit and shutter circuit to shield the electronic impulse that bombardment produces; When the LET value of single-particle bombardment is higher; The electronic impulse width can be greater than the time of delay of delay circuit; The output level of shutter circuit is overturn, greatly reduce the anti-single particle overturn ability of this d type flip flop.
Some integrated circuit needs the state of d type flip flop in the control integrated circuit, forces the d type flip flop input low level.On the original architecture basics of d type flip flop, increase synchronous reset circuit and synchronous reset signal input; Thereby realize the synchronous reset structure of d type flip flop; And control the synchronous reset function of d type flip flop through synchronous reset signal; But but this synchronous reset d type flip flop anti-single particle overturn ability is not high at present, is unfavorable in the IC chip in fields such as Aeronautics and Astronautics, using.
Summary of the invention
The technical problem that the present invention will solve is; But to the present not high problem of primary particle inversion resistant synchronous reset d type flip flop anti-single particle overturn ability; But a kind of primary particle inversion resistant synchronous reset d type flip flop is proposed, it can be under the bombardment of the single-particle of higher LET value operate as normal and do not produce single-particle inversion.
But the primary particle inversion resistant synchronous reset d type flip flop that the present invention proposes is by clock circuit, main latch, form from latch, first inverter circuit and second inverter circuit.
But the primary particle inversion resistant synchronous reset d type flip flop of the present invention has three inputs and two outputs.Three inputs are respectively that CK is that clock signal input part, D are that data-signal input and RN are the synchronous reset signal input; Two outputs are respectively Q and QN, and Q and QN export a pair of opposite data-signal.
Clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, is made up of first order inverter and second level inverter; First order inverter is made up of PMOS pipe and NMOS pipe, and the grid Pg1 of PMOS pipe connects CK, and the Pd1 that drains connects the drain electrode Nd1 that a NMOS manages, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is made up of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, and the Pd2 that drains connects the drain electrode Nd2 that the 2nd NMOS manages, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.
Main latch and be the redundant latch of reinforcing from latch.Main latch and series connection before and after the latch, and all be connected with clock circuit.Also be connected with second inverter circuit with first inverter circuit respectively from latch.
Main latch has four inputs and an output, and four inputs are D, C, CN, RN, and an output is MO.Main latch is made up of 12 PMOS pipes and 12 NMOS pipes, and the substrate of all PMOS pipes connects power vd D in the main latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg3 of the 3rd PMOS pipe connects D, and drain electrode Pd3 connects the source electrode Ps4 of the 4th PMOS pipe, and source electrode Ps3 connects power vd D; The grid Pg4 of the 4th PMOS pipe connects C, and drain electrode Pd4 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps4 connects Pd3; The grid Pg5 of the 5th PMOS pipe connects RN, and drain electrode Pd5 connects Pd3, and source electrode Ps5 connects power vd D; The grid Pg6 of the 6th PMOS pipe connects D, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects C, and drain electrode Pd7 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects RN, and drain electrode Pd8 connects Pd6, and source electrode Ps8 connects power vd D; The grid Pg9 of the 9th PMOS pipe connects Pd4, and drain electrode Pd9 connects the drain electrode Nd9 of the 9th NMOS pipe and as the output MO of main latch, source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects Pd7, and drain electrode Pd10 connects the drain electrode Nd10 of the tenth NMOS pipe, and source electrode Ps10 connects power vd D; The grid Pg11 of the 11 PMOS pipe connects Pd10, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects CN, and drain electrode Pd12 connects the drain electrode Nd11 of the 11 NMOS pipe, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects Pd9, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe, and source electrode Ps13 connects power vd D; The grid Pg14 of the 14 PMOS pipe connects CN, and drain electrode Pd14 connects the drain electrode Nd13 of the 13 NMOS pipe, and source electrode Ps14 connects Pd13; The grid Ng3 of the 3rd NMOS pipe connects CN, and drain electrode Nd3 connects Pd4, and source electrode Ns3 connects the drain electrode Nd4 of the 4th NMOS pipe; The grid Ng4 of the 4th NMOS pipe connects RN, and drain electrode Nd4 connects Ns3, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects D, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects power supply VSS; The grid Ng6 of the 6th NMOS pipe connects CN, and drain electrode Nd6 connects Pd7, and source electrode Ns6 connects the drain electrode Nd7 of the 7th NMOS pipe; The grid Ng7 of the 7th NMOS pipe connects RN, and drain electrode Nd7 connects Ns6, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects D, and drain electrode Nd8 connects Ns7, and source electrode Ns8 connects power supply VSS; The grid Ng9 of the 9th NMOS pipe connects Pd7, and drain electrode Nd9 connects Pd9, source electrode Ns9 ground connection VSS; The grid Ng10 of the tenth NMOS pipe connects Pd4, and drain electrode Nd10 connects Pd10, source electrode Ns10 ground connection VSS; The grid Ng11 of the 11 NMOS pipe connects C, and drain electrode Nd11 connects Pd12, and source electrode Ns11 connects the drain electrode Nd12 of the 12 NMOS pipe; The grid Ng12 of the 12 NMOS pipe connects Pd9, and drain electrode Nd12 connects Ns11, source electrode Ns12 ground connection VSS; The grid Ng13 of the 13 NMOS pipe connects C, and drain electrode Nd13 connects Pd14, and source electrode Ns13 connects the drain electrode Nd14 of the 14 NMOS pipe; The grid Ng14 of the 14 NMOS pipe connects Pd10, and drain electrode Nd14 connects Ns13, source electrode Ns14 ground connection VSS.
From latch three inputs and two outputs are arranged, three inputs are MO, C, CN, and two outputs are SO, SON.Be made up of ten PMOS pipes and ten NMOS pipes from latch, the substrate of all PMOS pipes connects power vd D from latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg15 of the 15 PMOS pipe connects MO, and drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects CN, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe, and source electrode connects Pd15; The grid Pg17 of the 17 PMOS pipe connects MO, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects CN, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the drain electrode Nd19 of the 19 NMOS pipe and as an output SO from latch, source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects Pd16, and drain electrode Pd20 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects Pd20, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects C, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe, and source electrode Ps22 connects Pd21; The grid Pg23 of the 23 PMOS pipe connects Pd19, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects C, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe and as another output SON from latch, source electrode Ps24 connects Pd23; The grid Ng15 of the 15 NMOS pipe connects C, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects MO, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects C, and drain electrode Nd17 connects Pd18, and source electrode Ns17 connects the drain electrode Nd18 of the 18 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects MO, and drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects Pd16, and drain electrode Nd19 connects Pd19, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects Pd18, and drain electrode Nd20 connects Pd20, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects CN, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd19, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23 NMOS pipe connects CN, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects Pd20, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS.
First inverter circuit has an input and an output, and input is SO, and output is QN.First inverter circuit is made up of the 25 PMOS pipe and the 25 NMOS pipe.The substrate of the 25 PMOS pipe all is connected power vd D with source electrode Ps25, the substrate and the equal ground connection VSS of source electrode Ns25 of the 25 NMOS pipe.The grid Pg25 of the 25 PMOS pipe connects SO, and drain electrode Pd25 connects the drain electrode Nd25 of the 25 NMOS pipe, and as the output QN of first inverter; The grid Ng25 of the 25 NMOS pipe connects SO, and drain electrode Nd25 connects Pd25.
Second inverter circuit has an input and an output, and input is SON, and output is Q.Second inverter circuit is made up of the 26 PMOS pipe and the 26 NMOS pipe.The substrate of the 26 PMOS pipe all is connected power vd D with source electrode Ps26, the substrate and the equal ground connection VSS of source electrode Ns26 of the 26 NMOS pipe.The grid Pg26 of the 26 PMOS pipe connects SON, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe, and as the output Q of second inverter; The grid Ng26 of the 26 NMOS pipe connects SON, and drain electrode Nd26 connects Pd26.
But the primary particle inversion resistant synchronous reset d type flip flop of the present invention course of work is following:
Clock circuit receives CK, produce respectively after it is cushioned with the CN of CK anti-phase and with the C of CK homophase, and CN with C imports main latch into and from latch.When CK was low level, CN was that high level, C are low level, and main latch is opened, if this moment, RN was a high level, d type flip flop does not carry out synchronous reset, but received D and it is carried out buffered, simultaneously the MO of output and D homophase; If this moment, RN was a low level, d type flip flop carries out synchronous reset, does not receive D but reception data-signal " 0 ", and the MO of output is a low level simultaneously.At CK is between low period, is in preservation state from latch, does not receive the MO of main latch output, but preserves the MO that a CK trailing edge samples; When CK is a high level, CN is that low level, C are that main latch is in preservation state between high period, preserves the D that previous CK rising edge samples, and the MO of output and D homophase.At CK is the output MO that opens and receive main latch between high period from latch, to MO carry out buffered and output and MO homophase SO and with the SON of MO anti-phase.First inverter circuit all will receive the output SO from latch at any time, to the QN of SO buffering and output and SO anti-phase.Second inverter circuit all will receive the output SON from latch at any time, to the Q of SON buffering and output and SON anti-phase.
Adopt the present invention can reach following technique effect:
But but but but the anti-single particle overturn ability of the primary particle inversion resistant synchronous reset d type flip flop of the present invention is superior to the synchronous reset d type flip flop and the redundant synchronous reset d type flip flop of reinforcing of tradition of the unguyed synchronous reset d type flip flop of tradition, time sampling reinforcing.But, all carried out the duplication redundancy reinforcing, and to main latch C to main latch with from latch because the present invention transforms the unguyed synchronous reset d type flip flop of tradition structure
2The MOS circuit structure improves, and promptly separates redundant each other C
2Pull-up circuit in the MOS circuit and pull-down circuit are to from latch C
2The MOS circuit structure improves, and promptly separates redundant each other C
2Last PMOS in the MOS circuit manages and pull-down NMOS pipe, but has further improved the anti-single particle overturn ability of the primary particle inversion resistant synchronous reset d type flip flop of the present invention.But the primary particle inversion resistant synchronous reset d type flip flop of the present invention is suitable for the standard cell lib that anti-single particle overturn is reinforced integrated circuit, is applied to fields such as Aeronautics and Astronautics.
Description of drawings
But Fig. 1 is the primary particle inversion resistant synchronous reset d type flip flop of a present invention logical construction sketch map.
But Fig. 2 is clock circuit structural representation in the primary particle inversion resistant synchronous reset d type flip flop of the present invention.
But Fig. 3 is main latch structural representation in the primary particle inversion resistant synchronous reset d type flip flop of the present invention.
But Fig. 4 is from the latch structure sketch map in the primary particle inversion resistant synchronous reset d type flip flop of the present invention.
But Fig. 5 is the first inverter circuit structure sketch map in the primary particle inversion resistant synchronous reset d type flip flop of the present invention.
But Fig. 6 is the second inverter circuit structure sketch map in the primary particle inversion resistant synchronous reset d type flip flop of the present invention.
Embodiment
But Fig. 1 is the primary particle inversion resistant synchronous reset d type flip flop of a present invention logical construction sketch map.The present invention is by clock circuit (as shown in Figure 2), main latch (as shown in Figure 3), form from latch (as shown in Figure 4), first inverter circuit (as shown in Figure 5) and second inverter circuit (as shown in Figure 6).The present invention has three each and every one input and two outputs.Three inputs are respectively that CK is that clock signal input part, D are that data-signal input and RN are the synchronous reset signal input; Two outputs are respectively Q and QN, and Q and QN export a pair of opposite data-signal.Clock circuit receives CK, and CK is carried out exporting C and CN respectively after the buffered.Main latch receives D and C and CN, and main latch latchs processing back output MO to D under the control of C and CN.Receive MO and C and CN from latch, after under the control of C and CN MO being latched processing, export SO, SON respectively from latch.First inverter circuit receives SO, and it is carried out exporting QN after the buffered.Second inverter circuit receives SON, and it is carried out exporting Q after the buffered.When RN is low level, but the primary particle inversion resistant synchronous reset d type flip flop of the present invention carries out synchronous reset; When RN is high level, but the primary particle inversion resistant synchronous reset d type flip flop of the present invention operate as normal.
As shown in Figure 2, clock circuit has an input and two outputs, and input is CK, and output is C, CN.Clock circuit is a two-stage inverter, and first order inverter is made up of PMOS pipe and NMOS pipe, and the grid Pg1 of PMOS pipe connects CK, and the Pd1 that drains connects the drain electrode Nd1 that a NMOS manages, and as an output CN of clock circuit.The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is made up of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, and the Pd2 that drains connects the drain electrode Nd2 that the 2nd NMOS manages, and as another output C of clock circuit.The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2.The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also.(with preceding consistent)
As shown in Figure 3, main latch has four inputs and an output, and four inputs are D, C, CN, RN, and an output is MO.Main latch is made up of 12 PMOS pipes and 12 NMOS pipes, and the substrate of all PMOS pipes connects power vd D in the main latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg3 of the 3rd PMOS pipe connects D, and drain electrode Pd3 connects the source electrode Ps4 of the 4th PMOS pipe, and source electrode Ps3 connects power vd D; The grid Pg4 of the 4th PMOS pipe connects C, and drain electrode Pd4 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps4 connects Pd3; The grid Pg5 of the 5th PMOS pipe connects RN, and drain electrode Pd5 connects Pd3, and source electrode Ps5 connects power vd D; The grid Pg6 of the 6th PMOS pipe connects D, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects C, and drain electrode Pd7 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects RN, and drain electrode Pd8 connects Pd6, and source electrode Ps8 connects power vd D; The grid Pg9 of the 9th PMOS pipe connects Pd4, and drain electrode Pd9 connects the drain electrode Nd9 of the 9th NMOS pipe and as the output MO of main latch, source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects Pd7, and drain electrode Pd10 connects the drain electrode Nd10 of the tenth NMOS pipe, and source electrode Ps10 connects power vd D; The grid Pg11 of the 11 PMOS pipe connects Pd10, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects CN, and drain electrode Pd12 connects the drain electrode Nd11 of the 11 NMOS pipe, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects Pd9, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe, and source electrode Ps13 connects power vd D; The grid Pg14 of the 14 PMOS pipe connects CN, and drain electrode Pd14 connects the drain electrode Nd13 of the 13 NMOS pipe, and source electrode Ps14 connects Pd13; The grid Ng3 of the 3rd NMOS pipe connects CN, and drain electrode Nd3 connects Pd4, and source electrode Ns3 connects the drain electrode Nd4 of the 4th NMOS pipe; The grid Ng4 of the 4th NMOS pipe connects RN, and drain electrode Nd4 connects Ns3, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects D, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects power supply VSS; The grid Ng6 of the 6th NMOS pipe connects CN, and drain electrode Nd6 connects Pd7, and source electrode Ns6 connects the drain electrode Nd7 of the 7th NMOS pipe; The grid Ng7 of the 7th NMOS pipe connects RN, and drain electrode Nd7 connects Ns6, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects D, and drain electrode Nd8 connects Ns7, and source electrode Ns8 connects power supply VSS; The grid Ng9 of the 9th NMOS pipe connects Pd7, and drain electrode Nd9 connects Pd9, source electrode Ns9 ground connection VSS; The grid Ng10 of the tenth NMOS pipe connects Pd4, and drain electrode Nd10 connects Pd10, source electrode Ns10 ground connection VSS; The grid Ng11 of the 11 NMOS pipe connects C, and drain electrode Nd11 connects Pd12, and source electrode Ns11 connects the drain electrode Nd12 of the 12 NMOS pipe; The grid Ng12 of the 12 NMOS pipe connects Pd9, and drain electrode Nd12 connects Ns11, source electrode Ns12 ground connection VSS; The grid Ng13 of the 13 NMOS pipe connects C, and drain electrode Nd13 connects Pd14, and source electrode Ns13 connects the drain electrode Nd14 of the 14 NMOS pipe; The grid Ng14 of the 14 NMOS pipe connects Pd10, and drain electrode Nd14 connects Ns13, source electrode Ns14 ground connection VSS.
As shown in Figure 4, from latch three inputs and two outputs are arranged, three inputs are MO, C, CN, two outputs are SO, SON.Be made up of ten PMOS pipes and ten NMOS pipes from latch, the substrate of all PMOS pipes connects power vd D from latch, the substrate ground connection VSS of all NMOS pipes.The grid Pg15 of the 15 PMOS pipe connects MO, and drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects CN, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe, and source electrode connects Pd15; The grid Pg17 of the 17 PMOS pipe connects MO, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects CN, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the drain electrode Nd19 of the 19 NMOS pipe and as an output SO from latch, source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects Pd16, and drain electrode Pd20 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects Pd20, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects C, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe, and source electrode Ps22 connects Pd21; The grid Pg23 of the 23 PMOS pipe connects Pd19, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects C, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe and as another output SON from latch, source electrode Ps24 connects Pd23; The grid Ng15 of the 15 NMOS pipe connects C, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects MO, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects C, and drain electrode Nd17 connects Pd18, and source electrode Ns17 connects the drain electrode Nd18 of the 18 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects MO, and drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects Pd16, and drain electrode Nd19 connects Pd19, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects Pd18, and drain electrode Nd20 connects Pd20, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects CN, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd19, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23 NMOS pipe connects CN, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects Pd20, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS.
As shown in Figure 5, first inverter circuit has an input and an output, and input is SO, and output is QN.First inverter circuit is made up of the 25 PMOS pipe and the 25 NMOS pipe.The substrate of the 25 PMOS pipe all is connected power vd D with source electrode Ps25, the substrate and the equal ground connection VSS of source electrode Ns25 of the 25 NMOS pipe.The grid Pg25 of the 25 PMOS pipe connects SO, and drain electrode Pd25 connects the drain electrode Nd25 of the 25 NMOS pipe, and as the output QN of first inverter; The grid Ng25 of the 25 NMOS pipe connects SO, and drain electrode Nd25 connects Pd25.
As shown in Figure 6, second inverter circuit has an input and an output, and input is SON, and output is Q.Second inverter circuit is made up of the 26 PMOS pipe and the 26 NMOS pipe.The substrate of the 26 PMOS pipe all is connected power vd D with source electrode Ps26, the substrate and the equal ground connection VSS of source electrode Ns26 of the 26 NMOS pipe.The grid Pg26 of the 26 PMOS pipe connects SON, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe, and as the output Q of second inverter; The grid Ng26 of the 26 NMOS pipe connects SON, and drain electrode Nd26 connects Pd26.
The H-13 of Beijing Institute of Atomic Energy tandem accelerator can produce the LET value and be respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2Four kinds of ground heavy ion irradiation test environments of/mg.But but but but will be in the LET value that the redundant synchronous reset d type flip flop of reinforcing of traditional unguyed synchronous reset d type flip flop, tradition of normal operating conditions, synchronous reset d type flip flop that time sampling is reinforced and the primary particle inversion resistant synchronous reset d type flip flop of the present invention place the H-13 of Beijing Institute of Atomic Energy tandem accelerator to produce and be respectively 2.88MeVcm
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2In the ground heavy ion irradiation test environment of/mg, observe each d type flip flop whether single-particle inversion takes place, obtain the minimum LET Value Data that each d type flip flop generation single-particle inversion needs.But but but but the synchronous reset d type flip flop of the redundant synchronous reset d type flip flop of reinforcing of traditional unguyed synchronous reset d type flip flop, tradition that the ground heavy particle irradiation test that table 1 carries out for the use H-13 of Beijing Institute of Atomic Energy tandem accelerator obtains, time sampling reinforcing and the minimum LET Value Data that the primary particle inversion resistant synchronous reset d type flip flop of the present invention generation single-particle inversion needs.But the unguyed synchronous reset d type flip flop of tradition is 2.88MeVcm in the LET value
2/ mg, 8.62MeVcm
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2Single-particle inversion all takes place in the ground heavy ion irradiation test environment of/mg when working, but the redundant synchronous reset d type flip flop of reinforcing of tradition is 12.6MeVcm in the LET value
2/ mg and 17.0MeVcm
2Single-particle inversion takes place when working in the ground heavy ion irradiation test environment of/mg, but the synchronous reset d type flip flop that time sampling is reinforced is 8.62MeVcm in the LET value
2/ mg, 12.6MeVcm
2/ mg and 17.0MeVcm
2Single-particle inversion takes place when working in the ground heavy ion irradiation test environment of/mg, but the primary particle inversion resistant synchronous reset d type flip flop of the present invention is 17.0MeVcm in the LET value only
2Single-particle inversion takes place in the ground heavy ion irradiation test environment of/mg when working.From then on table can be found out; But the minimum LET value that generation single-particle inversion of the present invention the needs synchronous reset d type flip flop more unguyed than tradition improves 343%; But improve 35% than the redundant synchronous reset d type flip flop of reinforcing of tradition; But the synchronous reset d type flip flop than time sampling is reinforced improves 97%; So but but but anti-single particle overturn ability of the present invention is superior to the synchronous reset d type flip flop and the redundant synchronous reset d type flip flop of reinforcing of tradition of the unguyed synchronous reset d type flip flop of tradition, time sampling reinforcing, be suitable for the standard cell lib that anti-single particle overturn is reinforced integrated circuit, be applied to fields such as Aeronautics and Astronautics.
Table 1
Claims (1)
1. but primary particle inversion resistant synchronous reset d type flip flop; But primary particle inversion resistant synchronous reset d type flip flop is by clock circuit, main latch, form from latch, first inverter circuit and second inverter circuit; Three inputs and two outputs are arranged; Three inputs are respectively that CK is that clock signal input part, D are that data-signal input and RN are the synchronous reset signal input, and two outputs are respectively Q and QN, and Q and QN export a pair of opposite data-signal; Clock circuit has an input and two outputs, and input is CK, and output is C, CN, and clock circuit is a two-stage inverter, is made up of first order inverter and second level inverter; First order inverter is made up of PMOS pipe and NMOS pipe, and the grid Pg1 of PMOS pipe connects CK, and the Pd1 that drains connects the drain electrode Nd1 that a NMOS manages, and as an output CN of clock circuit; The grid Ng1 of the one NMOS pipe connects CK, and drain electrode Nd1 connects Pd1; Second level inverter is made up of the 2nd PMOS pipe and the 2nd NMOS pipe, and the grid Pg2 of the 2nd PMOS pipe connects CN, and the Pd2 that drains connects the drain electrode Nd2 that the 2nd NMOS manages, and as another output C of clock circuit; The grid Ng2 of the 2nd NMOS pipe connects CN, and drain electrode Nd2 connects Pd2; The one PMOS pipe is connected power vd D with the substrate of the 2nd PMOS pipe, and source electrode Ps1, Ps2 connect power vd D; The substrate ground connection VSS of the one NMOS pipe and the 2nd NMOS pipe, source electrode Ns1, Ns2 be ground connection VSS also; First inverter circuit has an input and an output, and input is SO, and output is QN; First inverter circuit is made up of the 25 PMOS pipe and the 25 NMOS pipe; The substrate of the 25 PMOS pipe all is connected power vd D with source electrode Ps25, the substrate and the equal ground connection VSS of source electrode Ns25 of the 25 NMOS pipe; The grid Pg25 of the 25 PMOS pipe connects SO, and drain electrode Pd25 connects the drain electrode Nd25 of the 25 NMOS pipe, and as the output QN of first inverter; The grid Ng25 of the 25 NMOS pipe connects SO, and drain electrode Nd25 connects Pd25; Second inverter circuit has an input and an output, and input is SON, and output is Q; Second inverter circuit is made up of the 26 PMOS pipe and the 26 NMOS pipe; The substrate of the 26 PMOS pipe all is connected power vd D with source electrode Ps26, the substrate and the equal ground connection VSS of source electrode Ns26 of the 26 NMOS pipe; The grid Pg26 of the 26 PMOS pipe connects SON, and drain electrode Pd26 connects the drain electrode Nd26 of the 26 NMOS pipe, and as the output Q of second inverter; The grid Ng26 of the 26 NMOS pipe connects SON, and drain electrode Nd26 connects Pd26; Main latch and be the redundant latch of reinforcing from latch, main latch and series connection before and after the latch, and all be connected with clock circuit, also be connected with second inverter circuit with first inverter circuit respectively from latch; It is characterized in that main latch has four inputs and an output, four inputs are D, C, CN, RN, and an output is MO; Main latch is made up of 12 PMOS pipes and 12 NMOS pipes, and the substrate of all PMOS pipes connects power vd D in the main latch, the substrate ground connection VSS of all NMOS pipes; The grid Pg3 of the 3rd PMOS pipe connects D, and drain electrode Pd3 connects the source electrode Ps4 of the 4th PMOS pipe, and source electrode Ps3 connects power vd D; The grid Pg4 of the 4th PMOS pipe connects C, and drain electrode Pd4 connects the drain electrode Nd3 of the 3rd NMOS pipe, and source electrode Ps4 connects Pd3; The grid Pg5 of the 5th PMOS pipe connects RN, and drain electrode Pd5 connects Pd3, and source electrode Ps5 connects power vd D; The grid Pg6 of the 6th PMOS pipe connects D, and drain electrode Pd6 connects the source electrode Ps7 of the 7th PMOS pipe, and source electrode Ps6 connects power vd D; The grid Pg7 of the 7th PMOS pipe connects C, and drain electrode Pd7 connects the drain electrode Nd6 of the 6th NMOS pipe, and source electrode Ps7 connects Pd6; The grid Pg8 of the 8th PMOS pipe connects RN, and drain electrode Pd8 connects Pd6, and source electrode Ps8 connects power vd D; The grid Pg9 of the 9th PMOS pipe connects Pd4, and drain electrode Pd9 connects the drain electrode Nd9 of the 9th NMOS pipe and as the output MO of main latch, source electrode Ps9 connects power vd D; The grid Pg10 of the tenth PMOS pipe connects Pd7, and drain electrode Pd10 connects the drain electrode Nd10 of the tenth NMOS pipe, and source electrode Ps10 connects power vd D; The grid Pg11 of the 11 PMOS pipe connects Pd10, and drain electrode Pd11 connects the source electrode Ps12 of the 12 PMOS pipe, and source electrode Ps11 connects power vd D; The grid Pg12 of the 12 PMOS pipe connects CN, and drain electrode Pd12 connects the drain electrode Nd11 of the 11 NMOS pipe, and source electrode Ps12 connects Pd11; The grid Pg13 of the 13 PMOS pipe connects Pd9, and drain electrode Pd13 connects the source electrode Ps14 of the 14 PMOS pipe, and source electrode Ps13 connects power vd D; The grid Pg14 of the 14 PMOS pipe connects CN, and drain electrode Pd14 connects the drain electrode Nd13 of the 13 NMOS pipe, and source electrode Ps14 connects Pd13; The grid Ng3 of the 3rd NMOS pipe connects CN, and drain electrode Nd3 connects Pd4, and source electrode Ns3 connects the drain electrode Nd4 of the 4th NMOS pipe; The grid Ng4 of the 4th NMOS pipe connects RN, and drain electrode Nd4 connects Ns3, and source electrode Ns4 connects the drain electrode Nd5 of the 5th NMOS pipe; The grid Ng5 of the 5th NMOS pipe connects D, and drain electrode Nd5 connects Ns4, and source electrode Ns5 connects power supply VSS; The grid Ng6 of the 6th NMOS pipe connects CN, and drain electrode Nd6 connects Pd7, and source electrode Ns6 connects the drain electrode Nd7 of the 7th NMOS pipe; The grid Ng7 of the 7th NMOS pipe connects RN, and drain electrode Nd7 connects Ns6, and source electrode Ns7 connects the drain electrode Nd8 of the 8th NMOS pipe; The grid Ng8 of the 8th NMOS pipe connects D, and drain electrode Nd8 connects Ns7, and source electrode Ns8 connects power supply VSS; The grid Ng9 of the 9th NMOS pipe connects Pd7, and drain electrode Nd9 connects Pd9, source electrode Ns9 ground connection VSS; The grid Ng10 of the tenth NMOS pipe connects Pd4, and drain electrode Nd10 connects Pd10, source electrode Ns10 ground connection VSS; The grid Ng11 of the 11 NMOS pipe connects C, and drain electrode Nd11 connects Pd12, and source electrode Ns11 connects the drain electrode Nd12 of the 12 NMOS pipe; The grid Ng12 of the 12 NMOS pipe connects Pd9, and drain electrode Nd12 connects Ns11, source electrode Ns12 ground connection VSS; The grid Ng13 of the 13 NMOS pipe connects C, and drain electrode Nd13 connects Pd14, and source electrode Ns13 connects the drain electrode Nd14 of the 14 NMOS pipe; The grid Ng14 of the 14 NMOS pipe connects Pd10, and drain electrode Nd14 connects Ns13, source electrode Ns14 ground connection VSS; From latch three inputs and two outputs are arranged, three inputs are MO, C, CN, and two outputs are SO, SON; Be made up of ten PMOS pipes and ten NMOS pipes from latch, the substrate of all PMOS pipes connects power vd D from latch, the substrate ground connection VSS of all NMOS pipes; The grid Pg15 of the 15 PMOS pipe connects MO, and drain electrode Pd15 connects the source electrode Ps16 of the 16 PMOS pipe, and source electrode Ps15 connects power vd D; The grid Pg16 of the 16 PMOS pipe connects CN, and drain electrode Pd16 connects the drain electrode Nd15 of the 15 NMOS pipe, and source electrode connects Pd15; The grid Pg17 of the 17 PMOS pipe connects MO, and drain electrode Pd17 connects the source electrode Ps18 of the 18 PMOS pipe, and source electrode Ps17 connects power vd D; The grid Pg18 of the 18 PMOS pipe connects CN, and drain electrode Pd18 connects the drain electrode Nd17 of the 17 NMOS pipe, and source electrode Ps18 connects Pd17; The grid Pg19 of the 19 PMOS pipe connects Pd18, and drain electrode Pd19 connects the drain electrode Nd19 of the 19 NMOS pipe and as an output SO from latch, source electrode Ps19 connects power vd D; The grid Pg20 of the 20 PMOS pipe connects Pd16, and drain electrode Pd20 connects the drain electrode Nd20 of the 20 NMOS pipe, and source electrode Ps20 connects power vd D; The grid Pg21 of the 21 PMOS pipe connects Pd20, and drain electrode Pd21 connects the source electrode Ps22 of the 22 PMOS pipe, and source electrode Ps21 connects power vd D; The grid Pg22 of the 22 PMOS pipe connects C, and drain electrode Pd22 connects the drain electrode Nd21 of the 21 NMOS pipe, and source electrode Ps22 connects Pd21; The grid Pg23 of the 23 PMOS pipe connects Pd19, and drain electrode Pd23 connects the source electrode Ps24 of the 24 PMOS pipe, and source electrode Ps23 connects power vd D; The grid Pg24 of the 24 PMOS pipe connects C, and drain electrode Pd24 connects the drain electrode Nd23 of the 23 NMOS pipe and as another output SON from latch, source electrode Ps24 connects Pd23; The grid Ng15 of the 15 NMOS pipe connects C, and drain electrode Nd15 connects Pd16, and source electrode Ns15 connects the drain electrode Nd16 of the 16 NMOS pipe; The grid Ng16 of the 16 NMOS pipe connects MO, and drain electrode Nd16 connects Ns15, source electrode Ns16 ground connection VSS; The grid Ng17 of the 17 NMOS pipe connects C, and drain electrode Nd17 connects Pd18, and source electrode Ns17 connects the drain electrode Nd18 of the 18 NMOS pipe; The grid Ng18 of the 18 NMOS pipe connects MO, and drain electrode Nd18 connects Ns17, source electrode Ns18 ground connection VSS; The grid Ng19 of the 19 NMOS pipe connects Pd16, and drain electrode Nd19 connects Pd19, source electrode Ns19 ground connection VSS; The grid Ng20 of the 20 NMOS pipe connects Pd18, and drain electrode Nd20 connects Pd20, source electrode Ns20 ground connection VSS; The grid Ng21 of the 21 NMOS pipe connects CN, and drain electrode Nd21 connects Pd22, and source electrode Ns21 connects the drain electrode Nd22 of the 22 NMOS pipe; The grid Ng22 of the 22 NMOS pipe connects Pd19, and drain electrode Nd22 connects Ns21, source electrode Ns22 ground connection VSS; The grid Ng23 of the 23 NMOS pipe connects CN, and drain electrode Nd23 connects Pd24, and source electrode Ns23 connects the drain electrode Nd24 of the 24 NMOS pipe; The grid Ng24 of the 24 NMOS pipe connects Pd20, and drain electrode Nd24 connects Ns23, source electrode Ns24 ground connection VSS.
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| CN110190833A (en) * | 2019-07-03 | 2019-08-30 | 西安微电子技术研究所 | A kind of primary particle inversion resistant self-test self- recoverage synchronous reset d type flip flop |
| CN110190833B (en) * | 2019-07-03 | 2023-02-07 | 西安微电子技术研究所 | Self-detection and self-recovery synchronous reset D trigger resisting single event upset |
| CN110855270A (en) * | 2019-09-04 | 2020-02-28 | 合肥工业大学 | Cross-layer dual-mode redundancy sensitive amplifier type trigger with low overhead |
| CN110855270B (en) * | 2019-09-04 | 2022-09-23 | 合肥工业大学 | Cross-layer dual-mode redundancy sensitive amplifier type trigger with low overhead |
| CN111211769A (en) * | 2020-01-08 | 2020-05-29 | 中国人民武装警察部队海警学院 | Single event upset resistant latch and data trigger |
| CN111211769B (en) * | 2020-01-08 | 2023-04-25 | 中国人民武装警察部队海警学院 | Latch capable of resisting single event upset and data trigger |
| CN116185745A (en) * | 2023-04-26 | 2023-05-30 | 中国民航大学 | Quick soft error detection method for Beidou signal processing complex operation chip |
| CN116185745B (en) * | 2023-04-26 | 2023-06-27 | 中国民航大学 | Quick soft error detection method for Beidou signal processing complex operation chip |
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