CN102390001B - Widened type soft-switch inverter welding machine - Google Patents
Widened type soft-switch inverter welding machine Download PDFInfo
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- CN102390001B CN102390001B CN201110380438.3A CN201110380438A CN102390001B CN 102390001 B CN102390001 B CN 102390001B CN 201110380438 A CN201110380438 A CN 201110380438A CN 102390001 B CN102390001 B CN 102390001B
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Abstract
The invention relates to a soft-switch inverter welding machine and in particular relates to a widened type soft-switch inverter welding machine. The widened type soft-switch inverter welding machine can be used for solving the problem that the existing soft-switch inverter welding machine can not realize PWM (pulse-width modulation) control of a soft switch in no load and light load. The widened type soft-switch inverter welding machine is characterized in that a working circuit comprises a soft-switch main circuit and a soft-switch driving circuit, wherein the soft-switch main circuit comprises an IGBT (insulated gate bipolar translator) inverter circuit formed by a first IGBT tube, a second IGBT tube, a third IGBT tube and a fourth IGBT tube which are connected; an absorbing capacitor is connected in parallel among power supplies of the IGBT inverter circuit; a first resonance capacitor is connected in parallel between a collector and an emitter of the first IGBT tube; a second resonance capacitor is connected in parallel between a collector and an emitter of the second IGBT tube; and grids of the first IGBT tube, the second IGBT tube, the third IGBT tube and the fourth IGBT tube are connected with the output end of the soft-switch driving circuit. The widened type soft-switch inverter welding machine can be used for effectively solving the problem that the existing soft-switch inverter welding machine can not realize PWM (pulse-width modulation) control of the soft switch in no load and light load, and is applicable to various welding machines.
Description
Technical field
The present invention relates to soft-switching inversion welding machine, specifically the wide type soft-switching inversion welding machine of a kind of tune.
Background technology
Existing soft-switching inversion welding machine adopts the PWM control technology of fixed width phase shift type conventionally, the limitation of this technology is that leading arm pulsewidth is always in maximum pulse width, turn-off time is short, when unloaded and underloading, be difficult to realize no-voltage and turn on and off, while causing unloaded and underloading, welding machine loss and IGBT stress are also larger than hard switching circuit on the contrary.Based on this, be necessary to invent a kind of brand-new soft-switching inversion welding machine, to solve existing soft-switching inversion welding machine, cannot realize the problem of soft-switch PWM control when unloaded and the underloading.
Summary of the invention
The present invention cannot realize the problem of soft-switch PWM control when unloaded and the underloading in order to solve existing soft-switching inversion welding machine, the wide type soft-switching inversion of a kind of tune welding machine is provided.
The present invention adopts following technical scheme to realize: adjust wide type soft-switching inversion welding machine, its operating circuit comprises soft switch main circuit and soft switch driving circuit; Described soft switch main circuit comprises the IGBT inverter circuit consisting of first-, tetra-IGBT pipe connections; Between the power supply of IGBT inverter circuit, be parallel with Absorption Capacitance; Between the colelctor electrode of the one IGBT pipe and emitter stage, be parallel with the first resonant capacitance; Between the colelctor electrode of the 2nd IGBT pipe and emitter stage, be parallel with the second resonant capacitance; Between the mid point of two brachium pontis of IGBT inverter circuit, be connected with by primary coil, capacitance, the resonant inductance of main transformer and be connected in series the series arm forming; The initiatively secondary change of current inductance that is serially connected with of transformer; Initiatively between the secondary coil two ends of transformer and the positive output end of soft switch main circuit, be connected with by the first diode and the second diode and connect the parallel branch forming, initiatively between the centre tap of secondary coil of transformer and the negative output terminal of soft switch main circuit, being connected with by reactance and current divider and being connected in series the series arm forming; The grid of first-, tetra-IGBT pipes connects the output of soft switch driving circuit.
During work, the input of IGBT inverter circuit is connected with electrical network, and Absorption Capacitance is for absorbing the transient voltage of electrical network input.The positive and negative output of soft switch main circuit is connected with the high-frequency impulse arc striking circuit of welding machine.By turning on and off of soft switch driving circuit control IGBT inverter circuit, in conjunction with the resonance effect of the first resonant capacitance, the second resonant capacitance, resonant inductance, can realize the soft switch control of welding machine.In control procedure, capacitance can prevent from damaging because active transformer is offset the IGBT pipe causing.The effect of change of current inductance be when zero load or underloading for former limit resonant inductance provides electric current, guarantee also can realize soft switch when zero load or underloading.Based on said process, compared with existing soft-switching inversion welding machine, the soft-switch PWM control circuit structure of the wide type soft-switching inversion of tune of the present invention welding machine based on brand-new, realized when unloaded and underloading and carried out soft-switch PWM control, thoroughly solved thus existing soft-switching inversion welding machine and cannot realize the problem of soft-switch PWM control when zero load and underloading.
The present invention efficiently solves existing soft-switching inversion welding machine and cannot realize when unloaded and underloading the problem of soft-switch PWM control, is applicable to all kinds of welding machines.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of soft switch main circuit of the present invention.
Fig. 2 is the schematic diagram of soft switch driving circuit of the present invention.
The specific embodiment
Adjust wide type soft-switching inversion welding machine, its operating circuit comprises soft switch main circuit and soft switch driving circuit;
Described soft switch main circuit comprises that by first-, tetra-IGBT, managing K1-K4 connects the IGBT inverter circuit forming; Between the power supply of IGBT inverter circuit, be parallel with Absorption Capacitance C101; Between the colelctor electrode of the one IGBT pipe K1 and emitter stage, be parallel with the first resonant capacitance C102; Between the colelctor electrode of the 2nd IGBT pipe K2 and emitter stage, be parallel with the second resonant capacitance C103; Between the mid point of two brachium pontis of IGBT inverter circuit, be connected with by primary coil, capacitance C104, the resonant inductance L1 of main transformer T3 and be connected in series the series arm forming; The initiatively secondary change of current inductance L 2 that is serially connected with of transformer T3; Initiatively between the secondary coil two ends of transformer T3 and the positive output end of soft switch main circuit, be connected with by the first diode M1 and the second diode M2 and connect the parallel branch forming, initiatively between the centre tap of secondary coil of transformer T3 and the negative output terminal of soft switch main circuit, being connected with by reactance L3 and current divider S1 and being connected in series the series arm forming; The grid of first-, tetra-IGBT pipe K1-K4 connects the output of soft switch driving circuit;
Described soft switch driving circuit comprises that power supply circuits, primary current sample circuit, PWM produce circuit, slope compensation circuit, under-voltage protecting circuit, setting and follow circuit, lock-out pulse amplifying circuit, lagging leg signal generating circuit, drive circuit and signal indicating circuit;
Described power supply circuits comprise the first rectifier bridge B1; The input of the first rectifier bridge B1 is connected with the 5th plug J5; Between two outputs of the first rectifier bridge B1, be connected with by the first voltage-stablizer U8 and the second voltage-stablizer U2 and connect the parallel branch forming; The output that the input of the first voltage-stablizer U8 is connected with the 31 capacitor C 31, the first voltage-stablizer U8 is connected with by the 21 capacitor C the 21 and the 26 capacitor C 26 and connects the parallel branch forming; The input of the second voltage-stablizer U2 is connected with the 23 capacitor C 23; During work, alternating current is sent into the first rectifier bridge B1 rectification through the 5th plug J5, after rectification, after the 31 capacitor C the 31, the 23 capacitor C 23 filtering, send into the first voltage-stablizer U8, the second voltage-stablizer U2 voltage stabilizing, the power supply after voltage stabilizing is given whole soft switch driving circuit power supply;
Described primary current sample circuit comprises the second rectifier bridge being comprised of the first commutation diode D1, the second commutation diode D2, the 3rd commutation diode D3, the 5th commutation diode D5, the input of the second rectifier bridge is connected with the second plug J2, between two outputs of the second rectifier bridge, be connected with the 19 resistance R 19, the 19 resistance R 19 two ends are connected with respectively the first partial pressure filter circuit being comprised of the 30 resistance R the 30, the 20 capacitor C the 20, the 18 capacitor C 18 and the second partial pressure filter circuit being comprised of the 27 resistance R the 27, the 14 resistance R the 14, the 12 capacitor C 12, between the output of the output of the first partial pressure filter circuit and the first voltage-stablizer U8, be connected with the 31 resistance R 31, between the output of the output of the first partial pressure filter circuit and the second voltage-stablizer U2, be connected with by the 6th resistance R the 6 and the 28 resistance R 28 and be connected in series the series arm forming, the 6th resistance R 6 two ends are connected with by the 8th resistance R 8 and the second capacitor C 2 and are connected in series the series arm forming, during work, main transformer primary current signal by foreign current mutual inductor sample is sent into by the first commutation diode D1 through the second plug J2, the second commutation diode D2, the 3rd commutation diode D3, the second rectifier bridge of the 5th commutation diode D5 composition, current signal after rectification becomes voltage signal from the 19 resistance R 19, this voltage signal is via the 30 resistance R 30, the 20 capacitor C 20, the first partial pressure filter circuit filtering that the 18 capacitor C 18 forms, and send into respectively two paths of signals after adding a positive bias by the 31 resistance R 31: a road is via the 27 resistance R 27, the 14 resistance R 14, 16 pin of sending into current mode pwm chip UC3846U3 after the second partial pressure filter circuit dividing potential drop filtering that the 12 capacitor C 12 forms form current foldback circuit, another road the 28 resistance R 28, the 6th resistance R 6 dividing potential drops, and by the 6th resistance R 6, add 4 pin of sending into current mode pwm chip UC3846U3 after a back bias voltage and form the input current signal of current mode PWM,
Described PWM produces circuit and comprises current mode pwm chip UC3846U3; 16 pin of current mode pwm chip UC3846U3 connect the output of the second partial pressure filter circuit; 15 pin of current mode pwm chip UC3846U3 connect the output of the first voltage-stablizer U8; Between 13 pin of current mode pwm chip UC3846U3 and the output of the first voltage-stablizer U8, be connected with the power supply filter circuit being formed by the 22 resistance R the 22, the 15 capacitor C the 15, the 17 capacitor C 17; 9 pin of current mode pwm chip UC3846U3 are connected with by the 25 resistance R the 25, the 26 resistance R 26 and connect the timer resistance circuit forming; 8 pin of current mode pwm chip UC3846U3 are connected with by the 6th capacitor C 6, the 7th capacitor C 7 and connect the timer condenser network forming; 2 pin of current mode pwm chip UC3846U3 are connected with the current limit bleeder circuit being comprised of the tenth resistance R the 10, the 12 resistance R 12, the 9th capacitor C the 9, the 11 capacitor C 11; During work, current mode pwm chip UC3846U3 is determined the driving pulse width of 11 pin and 14 pin jointly by input current signal, the setting voltage signal of 5 pin and the maximum current limit signal of 1 pin of 4 pin; The directly export structure power supply to current mode pwm chip UC3846U3 through 15 pin of voltage-stabilized power supply, after the power supply filter circuit filtering that voltage-stabilized power supply forms via the 22 resistance R the 22, the 15 capacitor C the 15, the 17 capacitor C 17, the control section power supply through 13 pin to UC3846; The 25 resistance R the 25, the 26 resistance R 26 that is connected to the 6th capacitor C 6, the 7th capacitor C 7 of 8 pin and is connected to 9 pin forms timer capacitance-resistance, determines frequency and the dead band of output PWM; The maximum current limit signal consisting of the tenth resistance R the 10, the 12 resistance R 12, the 9th capacitor C the 9, the 11 capacitor C 11 is delivered to 1 pin, determines the maximum primary current allowing;
Described slope compensation circuit comprises the first amplifier U1B; The positive input terminal of the first amplifier U1B connects 8 pin of current mode pwm chip UC3846U3; The negative input end of the first amplifier U1B connects the output of the first amplifier U1B, between the output of the first amplifier U1B and 4 pin of current mode pwm chip UC3846U3, is connected with the 5th resistance R 5; During work, the sawtooth signal of 8 pin of current mode pwm chip UC3846U3 is followed after output through the first amplifier U1B, through be added to 4 pin of UC3846U3 of the 5th resistance R 5, so just on current signal basis, compensated a ramp signal, be conducive to the stable of whole PWM regulating circuit;
Described under-voltage protecting circuit comprises the first comparator U4B, between the output of the positive input terminal of the first comparator U4B and the first voltage-stablizer U8, be connected with the 3rd partial pressure filter circuit being formed by the 33 resistance R the 33, the 34 resistance R the 34, the 24 capacitor C 24, the negative input end of the first comparator U4B connects 2 pin of current mode pwm chip UC3846U3, the output of the first comparator U4B connects 1 pin of current mode pwm chip UC3846U3, during work, voltage-stabilized power supply is via the 33 resistance R 33, the 34 resistance R 34, after the 3rd partial pressure filter circuit dividing potential drop filtering that the 24 capacitor C 24 forms, send into the positive input terminal of the first comparator U4B, the negative input end of the first comparator U4B directly connects 2 pin of current mode pwm chip UC3846U3, the output of the first comparator U4B directly connects 1 pin of current mode pwm chip UC3846U3, when voltage-stabilized power supply low voltage, the first comparator U4B output directly drags down 1 pin of current mode pwm chip UC3846U3, forbid PWM output, reach the object of under-voltage protection,
Described setting is followed circuit and is comprised the second amplifier U1A; The 4th partial pressure filter circuit that the positive input terminal of the second amplifier U1A is connected with the 3rd plug J3 and is comprised of the first resistance R 1 and the 3rd capacitor C 3; The negative input end of the second amplifier U1A connects the output of the second amplifier U1A; Between 5 pin of the output of the second amplifier U1A and current mode pwm chip UC3846U3, be connected with the 5th partial pressure filter circuit being formed by the second resistance R 2 and the 8th capacitor C 8; The 3rd plug J3 connects 1 pin of current mode pwm chip UC3846U3; During work, the setting voltage that external piloting control plate provides is inputted through the 3rd plug J3, after the 4th partial pressure filter circuit filtering forming via the first resistance R 1 and the 3rd capacitor C 3, send into the positive input terminal by the second amplifier U1A, after the 5th partial pressure filter circuit filtering that output signal after amplifier is followed forms via the second resistance R 2 and the 8th capacitor C 8,5 pin of delivering to current mode pwm chip UC3846U3 carry out regulating impulse width; 1 pin of the 3rd plug J3 is directly connected to 1 pin of current mode pwm chip UC3846U3, and external piloting control plate just can directly be controlled the startup of PWM and be stopped by this signal like this, detects whether overcurrent of drive circuit simultaneously;
Described lock-out pulse amplifying circuit comprises the second comparator U4A; The positive input terminal of the second comparator U4A connects 10 pin of current mode pwm chip UC3846U3; Between the output of the positive input terminal of the second comparator U4A and the first voltage-stablizer U8, be connected with the 6th partial pressure filter circuit being formed by the 16 resistance R the 16 and the 25 capacitor C 25; Between the output of the negative input end of the second comparator U4A and the second voltage-stablizer U2, be connected with the 7th partial pressure filter circuit being formed by the 17 resistance R the 17, the 18 resistance R the 18, the 13 capacitor C 13; Between the output of the output of the second comparator U4A and the second voltage-stablizer U2, be connected with the 23 resistance R 23; During work, the synchronizing signal of 10 pin of current mode pwm chip UC3846U3 is because amplitude is little, need to be after amplifying could be used by circuit below.The voltage that the 7th partial pressure filter circuit being comprised of the 17 resistance R the 17, the 18 resistance R the 18, the 13 capacitor C 13 obtains voltage-stabilized power supply dividing potential drop is delivered to the negative input end of the second comparator U4A, the synchronizing signal of current mode pwm chip UC3846U3 is sent into the positive input terminal of the second comparator U4A, the output of the second comparator U4A connects the 23 resistance R 23, and this signal is delivered to lagging leg signal generating circuit and participated in logical operation;
Described lagging leg signal generating circuit comprises rest-set flip-flop CD4013U5, two 4 inputs or door CD4072U6 and the 4th metal-oxide-semiconductor Q4; 5 pin of 4 pin of rest-set flip-flop CD4013U5 and 11 pin, two 4 inputs or door CD4072U6 are connected the output of the second comparator U4A with 10 pin; 8 pin of rest-set flip-flop CD4013U5 connect 11 pin of current mode pwm chip UC3846U3; 10 pin of rest-set flip-flop CD4013U5 connect 14 pin of current mode pwm chip UC3846U3; 9 pin of rest-set flip-flop CD4013U5 are connected 9 pin of two 4 inputs or door CD4072U6 with 12 pin; 13 pin of rest-set flip-flop CD4013U5 connect 2 pin of two 4 inputs or door CD4072U6; 1 pin of rest-set flip-flop CD4013U5 connects 3 pin and 12 pin of two 4 inputs or door CD4072U6; The grid of the 4th metal-oxide-semiconductor Q4 connects the output of the first comparator U4B and 1 pin of pwm chip UC3846U3; The drain electrode of the 4th metal-oxide-semiconductor Q4 connects 4 pin and 11 pin of 6 pin of rest-set flip-flop CD4013U5, two 4 inputs or door CD4072U6; Between the output of the drain electrode of the 4th metal-oxide-semiconductor Q4 and the first voltage-stablizer U8, be connected with the 15 resistance R 15; During work, the A(11 pin that current mode pwm chip UC3846U3 produces), B(14 pin) pwm signal sends into respectively the SET(8 pin of rest-set flip-flop CD4013U5) and RSET(10 pin), the lock-out pulse after the second comparator U4A amplifies is delivered to respectively 5 pin and 10 pin of 11 pin of rest-set flip-flop CD4013U5, two 4 inputs or a CD4072U6.The 1 pin signal of current mode pwm chip UC3846U3 is delivered to respectively 4 pin and 11 pin of 6 pin of rest-set flip-flop CD4013U5, two 4 inputs or door CD4072U6 after the 4th metal-oxide-semiconductor Q4 and the 15 resistance R 15.When overcurrent, under-voltage and while forbidding PWM situation occurs, the 1 pin step-down of current mode pwm chip UC3846U3, the D pin of the 4th metal-oxide-semiconductor Q4 uprises, and lagging leg output is prohibited.13 pin of rest-set flip-flop CD4013U5 are connected to 2 pin of two 4 inputs or door CD4072U6,12 pin of rest-set flip-flop CD4013U5 are connected to 9 pin of two 4 inputs or door CD4072U6,1 pin of rest-set flip-flop CD4013U5 is connected to 12 pin and 3 pin of two 4 inputs or door CD4072U6, has just produced the pulse width signal of determining of lagging leg by this cover logic circuit;
Described drive circuit comprises the one 555 timer U9, the 2 555 timer U7, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3, the 5th metal-oxide-semiconductor Q5, the 6th metal-oxide-semiconductor Q6, the 7th metal-oxide-semiconductor Q7, the 8th metal-oxide-semiconductor Q8, the 9th metal-oxide-semiconductor Q9, the first driving transformer T1, the second driving transformer T2, the first plug J1, the 4th plug J4; 4 pin of the one 555 timer U9 connect 13 pin of two 4 inputs or door CD4072U6; 4 pin of the 2 555 timer U7 connect 1 pin of two 4 inputs or door CD4072U6; Between the grid of the 3rd metal-oxide-semiconductor Q3 and 14 pin of rest-set flip-flop CD4013U5, be connected with the 11 resistance R 11; Between the grid of the second metal-oxide-semiconductor Q2 and 14 pin of rest-set flip-flop CD4013U5, be connected with the 4th resistance R 4; The drain electrode of the 3rd metal-oxide-semiconductor Q3 connects the drain electrode of the second metal-oxide-semiconductor Q2; Between the output of the source electrode of the second metal-oxide-semiconductor Q2 and the first voltage-stablizer U8, be connected with the 21 resistance R 21; Between the grid of the 5th metal-oxide-semiconductor Q5 and 11 pin of rest-set flip-flop CD4013U5, be connected with the 13 resistance R 13; Between the 6th metal-oxide-semiconductor Q6 and 11 pin of rest-set flip-flop CD4013U5, be connected with the 3rd resistance R 3; The drain electrode of the 5th metal-oxide-semiconductor Q5 connects the drain electrode of the 6th metal-oxide-semiconductor Q6; Between the output of the source electrode of the 5th metal-oxide-semiconductor Q5 and the first voltage-stablizer U8, be connected with the 21 resistance R 21; The elementary two ends of the first driving transformer T1 connect respectively the drain electrode of the second metal-oxide-semiconductor Q2 and the drain electrode of the 5th metal-oxide-semiconductor Q5; Between secondary and the first plug J1 of the first driving transformer T1, be connected with the first output Shaping circuit being formed by the 4th commutation diode D4, the 9th resistance R 9, the 7th resistance R 7, the 5th capacitor C 5 and the second output Shaping circuit being formed by the 6th commutation diode D6, the 20 resistance R the 20, the 29 resistance R the 29, the 22 capacitor C 22; Between 3 pin of the grid of the 7th metal-oxide-semiconductor Q7 and the one 555 timer U9, be connected with the 46 resistance R 46; Between 3 pin of the grid of the 8th metal-oxide-semiconductor Q8 and the one 555 timer U9, be connected with the 48 resistance R 48; The drain electrode of the 7th metal-oxide-semiconductor Q7 connects the drain electrode of the 8th metal-oxide-semiconductor Q8; Between the output of the source electrode of the 7th metal-oxide-semiconductor Q7 and the first voltage-stablizer U8, be connected with the 41 resistance R 41; Between 3 pin of the grid of the 6th metal-oxide-semiconductor Q6 and the 2 555 timer U7, be connected with the 43 resistance R 43; Between 3 pin of the grid of the 9th metal-oxide-semiconductor Q9 and the 2 555 timer U7, be connected with the 44 resistance R 44; The drain electrode of the 6th metal-oxide-semiconductor Q6 connects the drain electrode of the 9th metal-oxide-semiconductor Q9; Between the output of the source electrode of the 6th metal-oxide-semiconductor Q6 and the first voltage-stablizer U8, be connected with the 41 resistance R 41; The elementary two ends of the second driving transformer T2 connect respectively the drain electrode of the 7th metal-oxide-semiconductor Q7 and the drain electrode of the 6th metal-oxide-semiconductor Q6; Between secondary and the 4th plug J4 of the second driving transformer T2, be connected with the 3rd output Shaping circuit being formed by the 7th commutation diode D7, the 39 resistance R the 39, the 36 resistance R the 36, the 27 capacitor C 27 and the 4th output Shaping circuit being formed by the 8th commutation diode D8, the 45 resistance R the 45, the 47 resistance R the 47, the 33 capacitor C 33; The first plug J1 connects the grid of an IGBT pipe K1, the 2nd IGBT pipe K2; The 4th plug J4 connects the grid of the 3rd IGBT pipe K3, the 4th IGBT pipe K4; During work, A, the B two-way PWM of current mode pwm chip UC3846U3 output drives signal to drive the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3, the 5th metal-oxide-semiconductor Q5 via the 32 resistance R the 32, the 35 resistance R the 35, the 37 resistance R the 37, the 11 resistance R 11, the 4th resistance R the 4, the 37 resistance R the 37, the 13 resistance R 13, the 3rd resistance R 3.These 4 metal-oxide-semiconductors drive the first driving transformer T1, and the secondary output two paths of signals of the first driving transformer T1 by after the first output Shaping circuit and the second output Shaping circuit shaping, drives two IGBT up and down of leading arm IGBT module respectively through the first plug J1.The lagging leg two-way pwm signal of two 4 inputs or door CD4072U6 output after the one 555 timer U9, the 2 555 timer U7 amplify, drives the 6th metal-oxide-semiconductor Q6, the 7th metal-oxide-semiconductor Q7, the 8th metal-oxide-semiconductor Q8, the 9th metal-oxide-semiconductor Q9 via the 46 resistance R the 46, the 48 resistance R the 48, the 43 resistance R the 43, the 44 resistance R 44 respectively.These 4 metal-oxide-semiconductors drive the second driving transformer T2, and the secondary output two paths of signals of the second driving transformer T2, respectively by after the 3rd output Shaping circuit and the 4th output Shaping circuit shaping, drives two IGBT up and down of lagging leg IGBT module through the 4th plug J4;
Described signal indicating circuit comprises the first light emitting diode H1 of 15 pin that are connected in current mode pwm chip UC3846U3 and is connected in the second light emitting diode H2 of 14 pin of current mode pwm chip UC3846U3; During work, the first light emitting diode H1 and the second light emitting diode H2 indicate respectively power supply and PWM to drive.
Claims (2)
1. adjust a wide type soft-switching inversion welding machine, it is characterized in that: its operating circuit comprises soft switch main circuit and soft switch driving circuit; Described soft switch main circuit comprises the IGBT inverter circuit that is connected formation by first-, tetra-IGBT pipes (K1-K4); Between the power supply of IGBT inverter circuit, be parallel with Absorption Capacitance (C101); Between the colelctor electrode of the one IGBT pipe (K1) and emitter stage, be parallel with the first resonant capacitance (C102); Between the colelctor electrode of the 2nd IGBT pipe (K2) and emitter stage, be parallel with the second resonant capacitance (C103); Between the mid point of two brachium pontis of IGBT inverter circuit, be connected with by primary coil, capacitance (C104), the resonant inductance (L1) of main transformer (T3) and be connected in series the series arm forming; The initiatively secondary change of current inductance (L2) that is serially connected with of transformer (T3); Initiatively between the secondary coil two ends of transformer (T3) and the positive output end of soft switch main circuit, be connected with by the first diode (M1) and the second diode (M2) and connect the parallel branch forming, initiatively between the centre tap of secondary coil of transformer (T3) and the negative output terminal of soft switch main circuit, being connected with by reactance (L3) and current divider (S1) and being connected in series the series arm forming; The grid of first-, tetra-IGBT pipes (K1-K4) connects the output of soft switch driving circuit.
2. the wide type soft-switching inversion of tune according to claim 1 welding machine, is characterized in that: described soft switch driving circuit comprises that power supply circuits, primary current sample circuit, PWM produce circuit, slope compensation circuit, under-voltage protecting circuit, setting and follow circuit, lock-out pulse amplifying circuit, lagging leg signal generating circuit, drive circuit and signal indicating circuit;
Described power supply circuits comprise the first rectifier bridge (B1); The input of the first rectifier bridge (B1) is connected with the 5th plug (J5); Between two outputs of the first rectifier bridge (B1), be connected with by the first voltage-stablizer (U8) and the second voltage-stablizer (U2) and connect the parallel branch forming; The input of the first voltage-stablizer (U8) is connected with the 31 electric capacity (C31), and the output of the first voltage-stablizer (U8) is connected with by the 21 electric capacity (C21) and the 26 electric capacity (C26) and connects the parallel branch forming; The input of the second voltage-stablizer (U2) is connected with the 23 electric capacity (C23);
Described primary current sample circuit comprises the second rectifier bridge being comprised of the first commutation diode (D1), the second commutation diode (D2), the 3rd commutation diode (D3), the 5th commutation diode (D5); The input of the second rectifier bridge is connected with the second plug (J2); Between two outputs of the second rectifier bridge, be connected with the 19 resistance (R19); The 19 resistance (R19) two ends are connected with respectively the first partial pressure filter circuit being comprised of the 30 resistance (R30), the 20 electric capacity (C20), the 18 electric capacity (C18) and the second partial pressure filter circuit being comprised of the 27 resistance (R27), the 14 resistance (R14), the 12 electric capacity (C12); Between the output of the output of the first partial pressure filter circuit and the first voltage-stablizer (U8), be connected with the 31 resistance (R31); Between the output of the output of the first partial pressure filter circuit and the second voltage-stablizer (U2), be connected with by the 6th resistance (R6) and the 28 resistance (R28) and be connected in series the series arm forming; The 6th resistance (R6) two ends are connected with by the 8th resistance (R8) and the second electric capacity (C2) and are connected in series the series arm forming;
Described PWM produces circuit and comprises current mode pwm chip UC3846(U3); Current mode pwm chip UC3846(U3) 16 pin connect the output of the second partial pressure filter circuit; Current mode pwm chip UC3846(U3) 15 pin connect the output of the first voltage-stablizer (U8); Current mode pwm chip UC3846(U3) 13 pin and the output of the first voltage-stablizer (U8) between be connected with the power supply filter circuit being formed by the 22 resistance (R22), the 15 electric capacity (C15), the 17 electric capacity (C17); Current mode pwm chip UC3846(U3) 9 pin be connected with by the 25 resistance (R25), the 26 resistance (R26) and connect the timer resistance circuit forming; Current mode pwm chip UC3846(U3) 8 pin be connected with by the 6th electric capacity (C6), the 7th electric capacity (C7) and connect the timer condenser network forming; Current mode pwm chip UC3846(U3) 2 pin be connected with the current limit bleeder circuit being formed by the tenth resistance (R10), the 12 resistance (R12), the 9th electric capacity (C9), the 11 electric capacity (C11);
Described slope compensation circuit comprises the first amplifier (U1B); The positive input terminal of the first amplifier (U1B) connects current mode pwm chip UC3846(U3) 8 pin; The negative input end of the first amplifier (U1B) connects the output of the first amplifier (U1B), the output of the first amplifier (U1B) and current mode pwm chip UC3846(U3) 4 pin between be connected with the 5th resistance (R5);
Described under-voltage protecting circuit comprises the first comparator (U4B); Between the output of the positive input terminal of the first comparator (U4B) and the first voltage-stablizer (U8), be connected with the 3rd partial pressure filter circuit being formed by the 33 resistance (R33), the 34 resistance (R34), the 24 electric capacity (C24); The negative input end of the first comparator (U4B) connects current mode pwm chip UC3846(U3) 2 pin; The output of the first comparator (U4B) connects current mode pwm chip UC3846(U3) 1 pin;
Described setting is followed circuit and is comprised the second amplifier (U1A); The 4th partial pressure filter circuit that the positive input terminal of the second amplifier (U1A) is connected with the 3rd plug (J3) and is comprised of the first resistance (R1) and the 3rd electric capacity (C3); The negative input end of the second amplifier (U1A) connects the output of the second amplifier (U1A); The output of the second amplifier (U1A) and current mode pwm chip UC3846(U3) 5 pin between be connected with the 5th partial pressure filter circuit being formed by the second resistance (R2) and the 8th electric capacity (C8); The 3rd plug (J3) connects current mode pwm chip UC3846(U3) 1 pin;
Described lock-out pulse amplifying circuit comprises the second comparator (U4A); The positive input terminal of the second comparator (U4A) connects current mode pwm chip UC3846(U3) 10 pin; Between the output of the positive input terminal of the second comparator (U4A) and the first voltage-stablizer (U8), be connected with the 6th partial pressure filter circuit being formed by the 16 resistance (R16) and the 25 electric capacity (C25); Between the output of the negative input end of the second comparator (U4A) and the second voltage-stablizer (U2), be connected with the 7th partial pressure filter circuit being formed by the 17 resistance (R17), the 18 resistance (R18), the 13 electric capacity (C13); Between the output of the output of the second comparator (U4A) and the second voltage-stablizer (U2), be connected with the 23 resistance (R23);
Described lagging leg signal generating circuit comprises rest-set flip-flop CD4013(U5), two 4 inputs or door CD4072(U6) and the 4th metal-oxide-semiconductor (Q4); Rest-set flip-flop CD4013(U5) 4 pin and 11 pin, two 4 inputs or door CD4072(U6) 5 pin be connected the output of the second comparator (U4A) with 10 pin; Rest-set flip-flop CD4013(U5) 8 pin connect current mode pwm chip UC3846(U3) 11 pin; Rest-set flip-flop CD4013(U5) 10 pin connect current mode pwm chip UC3846(U3) 14 pin; Rest-set flip-flop CD4013(U5) 9 pin be connected two 4 inputs or door CD4072(U6 with 12 pin) 9 pin; Rest-set flip-flop CD4013(U5) 13 pin connect two 4 inputs or door CD4072(U6) 2 pin; Rest-set flip-flop CD4013(U5) 1 pin connect two 4 inputs or door CD4072(U6) 3 pin and 12 pin; The grid of the 4th metal-oxide-semiconductor (Q4) connects output and the pwm chip UC3846(U3 of the first comparator (U4B)) 1 pin; The drain electrode of the 4th metal-oxide-semiconductor (Q4) connects rest-set flip-flop CD4013(U5) 6 pin, two 4 inputs or door CD4072(U6) 4 pin and 11 pin; Between the output of the drain electrode of the 4th metal-oxide-semiconductor (Q4) and the first voltage-stablizer (U8), be connected with the 15 resistance (R15);
Described drive circuit comprises the one 555 timer (U9), the 2 555 timer (U7), the first metal-oxide-semiconductor (Q1), the second metal-oxide-semiconductor (Q2), the 3rd metal-oxide-semiconductor (Q3), the 5th metal-oxide-semiconductor (Q5), the 6th metal-oxide-semiconductor (Q6), the 7th metal-oxide-semiconductor (Q7), the 8th metal-oxide-semiconductor (Q8), the 9th metal-oxide-semiconductor (Q9), the first driving transformer (T1), the second driving transformer (T2), the first plug (J1), the 4th plug (J4); 4 pin of the one 555 timer (U9) connect two 4 inputs or door CD4072(U6) 13 pin; 4 pin of the 2 555 timer (U7) connect two 4 inputs or door CD4072(U6) 1 pin; The grid of the 3rd metal-oxide-semiconductor (Q3) and rest-set flip-flop CD4013(U5) 14 pin between be connected with the 11 resistance (R11); The grid of the second metal-oxide-semiconductor (Q2) and rest-set flip-flop CD4013(U5) 14 pin between be connected with the 4th resistance (R4); The drain electrode of the 3rd metal-oxide-semiconductor (Q3) connects the drain electrode of the second metal-oxide-semiconductor (Q2); Between the output of the source electrode of the second metal-oxide-semiconductor (Q2) and the first voltage-stablizer (U8), be connected with the 21 resistance (R21); The grid of the 5th metal-oxide-semiconductor (Q5) and rest-set flip-flop CD4013(U5) 11 pin between be connected with the 13 resistance (R13); The 6th metal-oxide-semiconductor (Q6) and rest-set flip-flop CD4013(U5) 11 pin between be connected with the 3rd resistance (R3); The drain electrode of the 5th metal-oxide-semiconductor (Q5) connects the drain electrode of the 6th metal-oxide-semiconductor (Q6); Between the output of the source electrode of the 5th metal-oxide-semiconductor (Q5) and the first voltage-stablizer (U8), be connected with the 21 resistance (R21); The elementary two ends of the first driving transformer (T1) connect respectively the drain electrode of the second metal-oxide-semiconductor (Q2) and the drain electrode of the 5th metal-oxide-semiconductor (Q5); Between secondary and first plug (J1) of the first driving transformer (T1), be connected with the first output Shaping circuit being formed by the 4th commutation diode (D4), the 9th resistance (R9), the 7th resistance (R7), the 5th electric capacity (C5) and the second output Shaping circuit being formed by the 6th commutation diode (D6), the 20 resistance (R20), the 29 resistance (R29), the 22 electric capacity (C22); Between the 7th grid of metal-oxide-semiconductor (Q7) and 3 pin of the one 555 timer (U9), be connected with the 46 resistance (R46); Between the 8th grid of metal-oxide-semiconductor (Q8) and 3 pin of the one 555 timer (U9), be connected with the 48 resistance (R48); The drain electrode of the 7th metal-oxide-semiconductor (Q7) connects the drain electrode of the 8th metal-oxide-semiconductor (Q8); Between the output of the source electrode of the 7th metal-oxide-semiconductor (Q7) and the first voltage-stablizer (U8), be connected with the 41 resistance (R41); Between the 6th grid of metal-oxide-semiconductor (Q6) and 3 pin of the 2 555 timer (U7), be connected with the 43 resistance (R43); Between the 9th grid of metal-oxide-semiconductor (Q9) and 3 pin of the 2 555 timer (U7), be connected with the 44 resistance (R44); The drain electrode of the 6th metal-oxide-semiconductor (Q6) connects the drain electrode of the 9th metal-oxide-semiconductor (Q9); Between the output of the source electrode of the 6th metal-oxide-semiconductor (Q6) and the first voltage-stablizer (U8), be connected with the 41 resistance (R41); The elementary two ends of the second driving transformer (T2) connect respectively the drain electrode of the 7th metal-oxide-semiconductor (Q7) and the drain electrode of the 6th metal-oxide-semiconductor (Q6); Between secondary and the 4th plug (J4) of the second driving transformer (T2), be connected with the 3rd output Shaping circuit being formed by the 7th commutation diode (D7), the 39 resistance (R39), the 36 resistance (R36), the 27 electric capacity (C27) and the 4th output Shaping circuit being formed by the 8th commutation diode (D8), the 45 resistance (R45), the 47 resistance (R47), the 33 electric capacity (C33); The first plug (J1) connects the grid of an IGBT pipe (K1), the 2nd IGBT pipe (K2); The 4th plug (J4) connects the grid of the 3rd IGBT pipe (K3), the 4th IGBT pipe (K4);
Described signal indicating circuit comprise be connected in current mode pwm chip UC3846(U3) 15 pin the first light emitting diode (H1) and be connected in current mode pwm chip UC3846(U3) second light emitting diode (H2) of 14 pin.
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| CN201110380438.3A CN102390001B (en) | 2011-11-25 | 2011-11-25 | Widened type soft-switch inverter welding machine |
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| CN102390001B true CN102390001B (en) | 2014-04-16 |
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| CN201039013Y (en) * | 2007-05-17 | 2008-03-19 | 徐爱平 | Reverse conversion soft switch device |
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| CN201552368U (en) * | 2009-10-31 | 2010-08-18 | 华南理工大学 | Inverter welding power source for aluminum alloy double-wire double pulse digitized soft switch |
| CN102205476A (en) * | 2011-05-26 | 2011-10-05 | 太原市星云焊接设备有限公司 | High-frequency soft switching contravariant digital multifunctional welding machine |
| CN202344105U (en) * | 2011-11-25 | 2012-07-25 | 太原市星云焊接设备有限公司 | Width modulation type soft-switch inverter welding machine |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN201039010Y (en) * | 2007-03-30 | 2008-03-19 | 江苏科技大学 | Full-bridge phase shift zero-voltage soft switch reverse conversion arc welding power |
| CN201039013Y (en) * | 2007-05-17 | 2008-03-19 | 徐爱平 | Reverse conversion soft switch device |
| CN101599705A (en) * | 2008-06-02 | 2009-12-09 | 株式会社大亨 | Supply unit and arc component processing power source |
| CN201552368U (en) * | 2009-10-31 | 2010-08-18 | 华南理工大学 | Inverter welding power source for aluminum alloy double-wire double pulse digitized soft switch |
| CN102205476A (en) * | 2011-05-26 | 2011-10-05 | 太原市星云焊接设备有限公司 | High-frequency soft switching contravariant digital multifunctional welding machine |
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Effective date of registration: 20180116 Address after: No. 18, Fushun (Xin Bin), Liaoning (Xin Bin) welding Industrial Park Patentee after: LIAONING NEBULA WELDING EQUIPMENT MANUFACTURING CO., LTD. Address before: 030006 Shanxi city of Taiyuan province high tech Zone North Lane pioneering venture building A block 5 layer Patentee before: Taiyuan Nebula Welding Equipment Co., Ltd. |
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