CN102376674B - Packaging structure with embedded semi-conductor element - Google Patents
Packaging structure with embedded semi-conductor element Download PDFInfo
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- CN102376674B CN102376674B CN2010102500367A CN201010250036A CN102376674B CN 102376674 B CN102376674 B CN 102376674B CN 2010102500367 A CN2010102500367 A CN 2010102500367A CN 201010250036 A CN201010250036 A CN 201010250036A CN 102376674 B CN102376674 B CN 102376674B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
The invention relates to a packaging structure with an embedded semi-conductor element which comprises a substrate, at least one first metal frame, at least one semi-conductor chip, first dielectric layers, a first line layer and first layer-adding structures; the substrate is provided with a first surface and a second surface which are over against each other and at least one opening which penetrates through the first surface and the second surface; the first metal frame is arranged on the periphery of the opening and is arranged on the first surface; the semi-conductor chip is correspondingly arranged in the opening; the first dielectric layers are arranged on the first surface, the second surface and the semi-conductor chip; the first line layer is arranged on the first dielectric layer of the first surface; and the first layer-adding structures are arranged on the first dielectric layer of the first surface and the first line layer. According to the packaging structure with the embedded semi-conductor element, the metal frame is arranged on the periphery of the opening of the pre-embedded semi-conductor chip of the substrate and arranged on at least one surface; and the hole shape of laser burning is precisely controlled through the metal frame, so that the semi-conductor chip can be precisely embedded in the substrate.
Description
Technical field
The present invention relates to a kind of encapsulating structure, particularly a kind of have an encapsulating structure that is embedded with semiconductor element that accurate semiconductor chip is embedded into the position.
Background technology
Evolution along with semiconductor packaging, except traditional routing type (Wire bonding) and cover the semiconductor packaging of crystalline substance (Flipchip), semiconductor device (Semiconductor device) has been developed different packaged types at present, for example directly be embedded in a base plate for packaging (package substrate) and electrical integrated one semiconductor chip that for example has an integrated circuit, this kind packaging part can reduce the volume of overall semiconductor device and promote electrical functionality, then becomes a kind of trend of encapsulation.
See also Figure 1A to Fig. 1 C ', be the known encapsulating structure that is embedded with semiconductor element and the cutaway view of method for making thereof, wherein, Figure 1B ' is another form of Figure 1B, and Fig. 1 C ' continuity is from Figure 1B '.
As shown in Figure 1A, provide one to have relative first surface 10a and the substrate 10 of second surface 10b, and this substrate 10 has the pre-opening 100 of predetermined embedded with semi-conductor chip, and also forms several run through the conductive through hole 12 of first surface 10a and second surface 10b in this substrate 10.
As shown in Figure 1B, form with pre-opening 100 positions at this substrate 10 opening 100 ' run through this first surface 10a and second surface 10b by laser burn (laser ablation).
yet, the known encapsulating structure that is embedded with semiconductor element is that direct equipment with laser burn carries out contraposition to form this opening 100 ', and form this opening 100 ' because laser burns continuously, be rough surface through after burning reaction, cause the hole shape of laser burn to be difficult to accurately control profile, so can't accurately form this opening 100 ' shape, cause with original pre-opening 100 shapes and produce deviation, thereby position and original design different that semiconductor chip is embedded, namely for the incomplete hollow out of the opening 100 ' that is embedded this semiconductor chip, so namely easily cause this semiconductor chip accurately to be arranged in this opening 100 '.
As shown in Figure 1B ', and be to solve above-mentioned disappearance, and the pre-opening 100 that will be scheduled to is increased to another pre-opening 101, the more pre-opening after the increase of this substrate 10 101 form the opening 101 ' that runs through this first surface 10a and second surface 10b with laser burn.
As shown in Fig. 1 C ', continuity is from Figure 1B ', semiconductor chip 13 correspondences are located in this opening 101 ', and this semiconductor chip 13 also has acting surface 13a and non-acting surface 13b, this acting surface 13a exposes to this opening 100 ', and have several electronic padses 131 on this acting surface 13a, and on the gap between this opening 100 ' and semiconductor chip 13, this semiconductor chip 13, upper first dielectric layer 14 that forms of this first surface 10a and second surface 10b; Then, form the first line layer 141 on the first dielectric layer 14 on this first surface 10a, and form to be electrically connected the first conductive blind hole 142 of this first line layer 141, conductive through hole 12 and electronic pads 131 in this first dielectric layer 14, also form the second line layer 171 on the first dielectric layer 14 on this second surface 10b, and form the second conductive blind hole 172 that is electrically connected this second line layer 171 and conductive through hole 12 in this first dielectric layer 14; At last, form the first layer reinforced structure 15 on the first dielectric layer 14 of this first surface 10a and the first line layer 141, and form the second layer reinforced structure 18 on the first dielectric layer 14 of this second surface 10b and the second line layer 171.
but, the known encapsulating structure that is embedded with semiconductor element, the pre-opening 100 that to be scheduled to as shown in Figure 1B ' and Fig. 1 C ' is increased to another pre-opening 101, be installed with in this opening 101 ' for this semiconductor chip 13, yet, larger pre-opening 101 will cause the gap between this semiconductor chip 13 and this opening 101 ' larger, and then cause this first dielectric layer 14 to be difficult for filling up in this gap, cause this first dielectric layer 14 surface generation depressions, severe patient will make between the follow-up circuit that increases in layer process and to produce the phenomenon that short circuit or circuit peel off and occur, and then cause the reliability of overall package structure and yield significantly to descend the degradation problem.
In addition, maybe can insert viscose material (not expression in graphic) in order to the method for fixing this semiconductor chip 13, but the gap between this semiconductor chip 13 and this opening 101 ' is larger, must insert more viscose material, and the viscose material is quite expensive, thereby increase the process of inserting viscose, cause the waste of the increase of preparation process step and manufacturing cost.
Therefore, how to avoid the opening shape in the encapsulating structure that is embedded with semiconductor element in known technology not accurately to need enlarged opening, cause the problems such as reliability reduction of overall package structure, the real problem of desiring most ardently at present solution that become.
Summary of the invention
In view of the disadvantages of above-mentioned known technology, main purpose of the present invention is to provide a kind of encapsulating structure that is embedded with semiconductor element with accurate opening shape and tool high-reliability.
For reaching above-mentioned and other purpose, the invention provides a kind of encapsulating structure that is embedded with semiconductor element, it comprises:
Substrate has relative first surface and second surface, and has at least one opening that runs through this first surface and second surface;
At least one the first metal frame is located at the periphery of this at least one opening and is positioned on this first surface;
At least one semiconductor chip, correspondence are arranged in this at least one opening, and this semiconductor chip has corresponding acting surface and non-acting surface, and this acting surface has several electronic padses;
The first dielectric layer is located on the acting surface of the first surface of this substrate and semiconductor chip and on the non-acting surface of the second surface of this substrate and semiconductor chip;
The first line layer is located on the first dielectric layer on the acting surface of the first surface of this substrate and this semiconductor chip; And
The first layer reinforced structure is located on the first dielectric layer and the first line layer on this first surface.
In described encapsulating structure, also comprise at least one the second metal frame, correspondence is located at the periphery of this at least one opening and is positioned on the second surface of this substrate.
The described encapsulating structure that is embedded with semiconductor element, this first dielectric layer fill in gap between this opening and semiconductor chip, so that this semiconductor chip is fixed in this opening.
Described encapsulating structure also comprises at least one conductive through hole that runs through this first surface and second surface; Also be provided with the first conductive blind hole that several are electrically connected this first line layer, conductive through hole and electronic pads in this first dielectric layer.
In described encapsulating structure, this first layer reinforced structure comprises at least one the second dielectric layer, be located at the second line layer on this second dielectric layer, and several be located in this second dielectric layer and be electrically connected the second conductive blind hole of this first line layer and the second line layer, outermost the second line layer of this first layer reinforced structure also can have several first electric contact mats; Also be provided with the first insulating protective layer on this first layer reinforced structure outermost layer, and be provided with the first perforate that several correspondences expose each this first electric contact mat in this first insulating protective layer.
The described encapsulating structure that is embedded with semiconductor element, also comprise the tertiary circuit layer, be located on the second surface and the first dielectric layer on this non-acting surface of this substrate, and be provided with the 3rd conductive blind hole that several are electrically connected this tertiary circuit layer and conductive through hole in this first dielectric layer; Also comprise the second layer reinforced structure, be located on the first dielectric layer and tertiary circuit layer on this second surface, this second layer reinforced structure comprises at least one the 3rd dielectric layer, be located at the 4th line layer on the 3rd dielectric layer, and several be located in the 3rd dielectric layer and be electrically connected the 4th line layer and the 4th conductive blind hole of tertiary circuit layer, outermost the 4th line layer of this second layer reinforced structure also can have several second electric contact mats; Also be provided with the second insulating protective layer on this second layer reinforced structure outermost layer, and be provided with the second perforate that several correspondences expose each this second electric contact mat in this second insulating protective layer.
In described encapsulating structure, the quantity of this opening is several, and this first metal frame and semiconductor chip be corresponding several, and those first metal frames are connected to each other, and the semiconductor chip of accommodating correspondence in each this opening.
as from the foregoing, the encapsulating structure that is embedded with semiconductor element of the present invention is at predetermined institute's periphery of embedded with semi-conductor chip opening of wanting and is positioned at correspondence formation metal frame at least one surface of this substrate, can't penetrate and burn the characteristic of metal due to laser, make laser burn continuously when forming this opening, guarantee position and the hole shape of this opening with this metal frame, and then guarantee that this semiconductor chip can accurately be arranged at the pre-position, thereby need not strengthen pre-opening and can accurately this semiconductor chip be embedded in this opening, and the gap between this semiconductor chip and opening is less, can avoid inserting dielectric layer or viscose material when fixing this semiconductor chip in this gap, this dielectric layer surface generation depression, and can form even curface, to promote reliability, and can simplify preparation process and reduce manufacturing cost.
Description of drawings
Figure 1A to Fig. 1 C ' is the known encapsulating structure that is embedded with semiconductor element and the cutaway view of method for making thereof;
Fig. 2 A to Fig. 2 E is the encapsulating structure of semiconductor element and the cutaway view of method for making thereof of being embedded with of the present invention;
[critical piece symbol description]
10,20 substrates
10a, 20a first surface
10b, 20b second surface
100,101,200 pre-openings
100 ', 101 ', 200 ' opening
12,22 conductive through holes
13,23 semiconductor chips
13a, 23a acting surface
The non-acting surface of 13b, 23b
131,231 electronic padses
14,24 first dielectric layers
141,241 first line layers
142,242 first conductive blind holes
15,25 first layer reinforced structures
172,252 second conductive blind holes
171,253 second line layers
18,28 second layer reinforced structures
21a the first metal frame
21b the second metal frame
251 second dielectric layers
254 first electric contact mats
26 first insulating protective layers
260 first perforates
271 tertiary circuit layers
272 the 3rd conductive blind holes
281 the 3rd dielectric layers
282 the 4th conductive blind holes
283 the 4th line layers
284 second electric contact mats
29 second insulating protective layers
290 second perforates
Embodiment
Below by particular specific embodiment, embodiments of the present invention are described, those of ordinary skills can understand other advantages of the present invention and effect easily by the content that this specification provides.
See also Fig. 2 A to Fig. 2 E, be the encapsulating structure of semiconductor element and the cutaway view of method for making thereof of being embedded with of the present invention, wherein, Fig. 2 B ' and Fig. 2 B " be the vertical view of Fig. 2 B.
As shown in Fig. 2 A, a substrate 20 is provided, it has relative first surface 20a and second surface 20b.
As shown in Fig. 2 B, the periphery of at least one pre-opening 200 of this substrate 20 predetermined embedded with semi-conductor chip of wanting and be positioned at this first surface 20a and second surface 20b at least one the first metal frame 21a of corresponding formation and the second metal frame 21b respectively, and several run through the conductive through hole 22 of this first surface 20a and second surface 20b also can be included in this substrate 20 formation; The better copper that can be of material of this first metal frame 21a of described formation and the second metal frame 21b; In other embodiment, also can only form this first metal frame 21a on this first surface 20a, and not form this second metal frame 21b at this second surface 20b.
As Fig. 2 B ' and Fig. 2 B " as shown in, be the various different forms of implementation of the vertical view of Fig. 2 B; Wherein, this Fig. 2 B ' is for being illustrated in for example a pre-opening 200 and being located at its periphery and being positioned at the first metal frame 21a on this first surface 20a; And this Fig. 2 B " for representing for example two pre-openings 200 and being located at its periphery and being positioned at two the first metal frame 21a on this first surface 20a; and these two the first metal frame 21a are connected to each other; in order in subsequent preparation process, with two semiconductor chips respectively correspondence be located at these two pre-opening 200 places (not representing semiconductor chip in graphic).
As shown in Fig. 2 C, with at this pre-opening 200 places, namely in this first metal frame 21a and the second metal frame 21b, form the opening 200 ' that runs through this first surface 20a and second surface 20b by laser burn (laser ablation).
As shown in Fig. 2 D, be installed with at least one semiconductor chip 23 in this opening 200 ', and this semiconductor chip 23 has corresponding acting surface 23a and non-acting surface 23b, and this acting surface 23a exposes to this opening 200 ' and is positioned at this first surface 20a, and this acting surface 23a has several electronic padses 231; Then, forming the first dielectric layer 24 on the acting surface 23a of the first surface 20a of this substrate 20 and semiconductor chip 23 and on the non-acting surface 23b of the second surface 20b of this substrate 20 and semiconductor chip 23, and this first dielectric layer 24 fills in gap between this opening 200 ' and semiconductor chip 23, so that this semiconductor chip 23 is fixed in this opening 200 '; In other example, also can comprise viscose material (not expression in graphic) is filled in the gap between this opening 200 ' and semiconductor chip 23, so that this semiconductor chip 23 is fixed in this opening 200 '.
as shown in Fig. 2 E, form the first line layer 241 on the first dielectric layer 24 on this first surface 20a and this acting surface 23a, and form the first conductive blind hole 242 that several are electrically connected this first line layer 241, conductive through hole 22 and electronic pads 231 in this first dielectric layer 24, then, form the first layer reinforced structure 25 on the first dielectric layer 24 on this first surface 20a and the first line layer 241, and this first layer reinforced structure 25 comprises at least one the second dielectric layer 251, be formed on the second line layer 253 on this second dielectric layer 251, and several are formed in this second dielectric layer 251 and are electrically connected this first line layer 241 and the second conductive blind hole 252 of the second line layer 253, and outermost the second line layer 253 of this first layer reinforced structure 25 also has several the first electric contact mats 254, also form the first insulating protective layer 26 on these the first layer reinforced structure 25 outermost layers, and be formed with the first perforate 260 that several correspondences expose each this first electric contact mat 254 in this first insulating protective layer 26.
as shown in Fig. 2 E, the present invention also forms tertiary circuit layer 271 on the first dielectric layer 24 on the second surface 20b of this substrate 20 and this non-acting surface 23b, and forms the 3rd conductive blind hole 272 that several are electrically connected this tertiary circuit layer 271 and conductive through hole 22 in this first dielectric layer 24, then, form the second layer reinforced structure 28 on the first dielectric layer 24 of this second surface 20b and tertiary circuit layer 271, this second layer reinforced structure 28 also comprises at least one the 3rd dielectric layer 281, be formed at the 4th line layer 283 on the 3rd dielectric layer 281, reach the 4th conductive blind hole 282 that several are formed in the 3rd dielectric layer 281 and are electrically connected the 4th line layer 283 and tertiary circuit layer 271, and outermost the 4th line layer 283 of this second layer reinforced structure 28 also has several the second electric contact mats 284, also form the second insulating protective layer 29 on these the second layer reinforced structure 28 outermost layers, and be formed with the second perforate 290 that several correspondences expose each this second electric contact mat 284 in this second insulating protective layer 29.
The invention provides a kind of encapsulating structure that is embedded with semiconductor element, comprising: substrate 20 has relative first surface 20a and second surface 20b, and has at least one opening 200 ' that runs through this first surface 20a and second surface 20b; At least one the first metal frame 21a, correspondence is located at the periphery of this opening 200 ' and is positioned on this first surface 20a; And at least one semiconductor chip 23, be installed with in this opening 200 '.
In the described encapsulating structure that is embedded with semiconductor element, also can comprise at least one the second metal frame 21b, correspondence is located at the periphery of this at least one opening 200 ' and is positioned on this second surface 20b, and can comprise that also several run through the conductive through hole 22 of this first surface 20a and second surface 20b, this semiconductor chip 23 also can have corresponding acting surface 23a and non-acting surface 23b, this acting surface 23a exposes to this opening 200 ' and is positioned at this first surface 20a, has several electronic padses 231 on this acting surface 23a.
the described encapsulating structure that is embedded with semiconductor element, also can comprise the first dielectric layer 24, be located on the acting surface 23a of the first surface 20a of this substrate 20 and semiconductor chip 23, and on the non-acting surface 23b of the second surface 20b of this substrate 20 and semiconductor chip 23, and this first dielectric layer 24 and fill in this opening 200 ' and semiconductor chip 23 between the gap in, and also can comprise the first line layer 241, be located on the first dielectric layer 24 on this first surface 20a and this acting surface 23a, and be provided with several be electrically connected this first line layer 241 in this first dielectric layer 24, the first conductive blind hole 242 of conductive through hole 22 and electronic pads 231.
described encapsulating structure, also can comprise the first layer reinforced structure 25, be located on the first dielectric layer 24 and the first line layer 241 on this first surface 20a, this first layer reinforced structure 25 comprises at least one the second dielectric layer 251, be located at the second line layer 253 on this second dielectric layer 251, and several are located in this second dielectric layer 251 and are electrically connected this first line layer 241 and the second conductive blind hole 252 of the second line layer 253, outermost the second line layer 253 of this first layer reinforced structure 25 also can have several first electric contact mats 254, also be provided with the first insulating protective layer 26 on these the first layer reinforced structure 25 outermost layers, and be provided with the first perforate 260 that several correspondences expose each this first electric contact mat 254 in this first insulating protective layer 26.
in the described encapsulating structure that is embedded with semiconductor element, also can comprise tertiary circuit layer 271, be located on the first dielectric layer 24 on this second surface 20b and this non-acting surface 23b, and be provided with the 3rd conductive blind hole 272 that several are electrically connected this tertiary circuit layer 271 and conductive through hole 22 in this first dielectric layer 24, and also can comprise the second layer reinforced structure 28, be located on the first dielectric layer 24 and tertiary circuit layer 271 on this second surface 20b, this second layer reinforced structure 28 comprises at least one the 3rd dielectric layer 281, be located at the 4th line layer 283 on the 3rd dielectric layer 281, reach the 4th conductive blind hole 282 that several are located in the 3rd dielectric layer 281 and are electrically connected the 4th line layer 283 and tertiary circuit layer 271, outermost the 4th line layer 283 of this second layer reinforced structure 28 also can have several second electric contact mats 284, also be provided with the second insulating protective layer 29 on these the second layer reinforced structure 28 outermost layers, and be provided with the second perforate 290 that several correspondences expose each this second electric contact mat 284 in this second insulating protective layer 29.
In described encapsulating structure, this opening 200 ', the first metal frame 21a and semiconductor chip 23 can be several, and those first metal frames 21a can be connected to each other, and correspondence is installed with semiconductor chip 23 in this opening 200 ' respectively.
in sum, the encapsulating structure that is embedded with semiconductor element of the present invention was wanted the opening periphery of embedded with semi-conductor chip and is positioned at least one surface of this substrate to form metal frame in substrate predetermined, can't penetrate and burn the characteristic of metal due to laser, make laser burn continuously when forming this opening, guarantee position and the hole shape of this opening with this metal frame, and then guarantee that this semiconductor chip can accurately be arranged at the pre-position, thereby need not strengthen pre-opening and can accurately this semiconductor chip be embedded in this opening, and the gap between this semiconductor chip and opening is less, can avoid inserting dielectric layer or viscose material when fixing this semiconductor chip in this gap, this dielectric layer surface generation depression, and can form even curface, to promote reliability, and can simplify preparation process and reduce manufacturing cost.
Above-described embodiment is in order to illustrative principle of the present invention and effect thereof, but not is used for restriction the present invention.Those of ordinary skills all can under spirit of the present invention and category, modify to above-described embodiment.
Claims (11)
1. an encapsulating structure that is embedded with semiconductor element, is characterized in that, comprising:
Substrate has relative first surface and second surface, and has at least one opening that runs through this first surface and second surface;
At least one the first metal frame is located at the periphery of this at least one opening and is positioned on this first surface;
At least one semiconductor chip, correspondence are arranged in this at least one opening, and this semiconductor chip has corresponding acting surface and non-acting surface, and this acting surface has several electronic padses;
The first dielectric layer is located on the acting surface of the first surface of this substrate and semiconductor chip and on the non-acting surface of the second surface of this substrate and semiconductor chip;
The first line layer is located on the first dielectric layer on the acting surface of the first surface of this substrate and this semiconductor chip, and this first metal frame is not electrically connected this first line layer; And
The first layer reinforced structure is located on the first dielectric layer and the first line layer on this first surface.
2. the encapsulating structure that is embedded with semiconductor element as claimed in claim 1, is characterized in that this encapsulating structure also comprises at least one the second metal frame, and correspondence is located at the periphery of this at least one opening and is positioned on the second surface of this substrate.
3. the encapsulating structure that is embedded with semiconductor element as claimed in claim 1, is characterized in that, this first dielectric layer fills in gap between this opening and semiconductor chip, so that this semiconductor chip is fixed in this opening.
4. the encapsulating structure that is embedded with semiconductor element as claimed in claim 1, is characterized in that, this encapsulating structure also comprises at least one conductive through hole that runs through this first surface and second surface.
5. the encapsulating structure that is embedded with semiconductor element as claimed in claim 4, is characterized in that, is provided with the first conductive blind hole that several are electrically connected this first line layer, conductive through hole and electronic pads in this first dielectric layer.
6. the encapsulating structure that is embedded with semiconductor element as claimed in claim 1, it is characterized in that, this first layer reinforced structure comprises at least one the second dielectric layer, be located at the second line layer on this second dielectric layer, and several be located in this second dielectric layer and be electrically connected the second conductive blind hole of this first line layer and the second line layer.
7. the encapsulating structure that is embedded with semiconductor element as claimed in claim 6; it is characterized in that; outermost the second line layer of this first layer reinforced structure also has several the first electric contact mats; also be provided with the first insulating protective layer on this first layer reinforced structure outermost layer, and be provided with the first perforate that several correspondences expose each this first electric contact mat in this first insulating protective layer.
8. the encapsulating structure that is embedded with semiconductor element as claimed in claim 4, it is characterized in that, this encapsulating structure also comprises the tertiary circuit layer, be located on the second surface and the first dielectric layer on this non-acting surface of this substrate, and be provided with the 3rd conductive blind hole that several are electrically connected this tertiary circuit layer and conductive through hole in this first dielectric layer.
9. the encapsulating structure that is embedded with semiconductor element as claimed in claim 8, it is characterized in that, this encapsulating structure also comprises the second layer reinforced structure, be located on the first dielectric layer and tertiary circuit layer on this second surface, this second layer reinforced structure comprises at least one the 3rd dielectric layer, be located at the 4th line layer on the 3rd dielectric layer, and several be located in the 3rd dielectric layer and be electrically connected the 4th line layer and the 4th conductive blind hole of tertiary circuit layer.
10. the encapsulating structure that is embedded with semiconductor element as claimed in claim 9; it is characterized in that; outermost the 4th line layer of this second layer reinforced structure also has several the second electric contact mats; also be provided with the second insulating protective layer on this second layer reinforced structure outermost layer, and be provided with the second perforate that several correspondences expose each this second electric contact mat in this second insulating protective layer.
11. the encapsulating structure that is embedded with semiconductor element as claimed in claim 1, it is characterized in that, the quantity of this opening is several, and this first metal frame and semiconductor chip are corresponding several, those first metal frames are connected to each other, and the semiconductor chip of accommodating correspondence in this opening respectively.
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| CN2010102500367A CN102376674B (en) | 2010-08-04 | 2010-08-04 | Packaging structure with embedded semi-conductor element |
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| CN2010102500367A CN102376674B (en) | 2010-08-04 | 2010-08-04 | Packaging structure with embedded semi-conductor element |
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| CN102376674A CN102376674A (en) | 2012-03-14 |
| CN102376674B true CN102376674B (en) | 2013-06-26 |
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| CN106935516B (en) * | 2015-12-30 | 2019-05-03 | 欣兴电子股份有限公司 | The production method of the encapsulating structure of built-in type electronic building brick |
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|---|---|
| CN102376674A (en) | 2012-03-14 |
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