CN102355244B - Frequency divider resetting circuit and system - Google Patents
Frequency divider resetting circuit and system Download PDFInfo
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- CN102355244B CN102355244B CN 201110213434 CN201110213434A CN102355244B CN 102355244 B CN102355244 B CN 102355244B CN 201110213434 CN201110213434 CN 201110213434 CN 201110213434 A CN201110213434 A CN 201110213434A CN 102355244 B CN102355244 B CN 102355244B
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- 230000005669 field effect Effects 0.000 claims abstract description 239
- 230000000630 rising effect Effects 0.000 claims abstract description 25
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Abstract
The invention discloses a frequency divider resetting circuit, which comprises a clock signal input end, a first signal output end, a second signal output end, a rising edge triggering circuit, a falling edge triggering circuit, a control circuit connected with the rising edge triggering circuit and the falling edge triggering circuit and a resetting signal input end connected with the control circuit. The control circuit comprises a first inverter connected with the resetting signal input end, a second inverter connected with the first inverter, a thirteenth field effect transistor connected with the resetting signal input end, a fourteenth field effect transistor connected with the resetting signal input end, a fifteenth field effect transistor connected with the second inverter and a capacitor connected between the first inverter and the second inverter. The thirteenth field effect transistor is connected with the falling edge triggering circuit. The fourteenth and fifteenth field effect transistors are connected with the rising edge triggering circuit. The invention also provides a frequency divider resetting system. The circuit and the system have simple structures.
Description
Technical field
The present invention relates to a kind of frequency divider, espespecially a kind of simple in structure and have frequency divider reset circuit and a system of reset function.
Background technology
Frequency divider is that the frequency of oscillation that produces is the nonlinear device of the whole approximate number of its incoming frequency.In order to guarantee the normal operation of sequence circuit, often require frequency divider when just starting working, a pair of differential signal of its output output has fixing original levels.
And in the prior art, frequency divider is when just starting working, the impact that its output is easy to be subject to circuit noise, device mismatch etc. has randomness, and so that the original levels of the differential signal of output output may be high level or low level, fixing difference not, thus the normal operation of sequence circuit affected.
Summary of the invention
In view of above content, be necessary to provide a kind of simple in structure and have frequency divider reset circuit and a system of reset function.
A kind of frequency divider reset circuit, comprise a clock signal input part, one first signal output and a secondary signal output, the a pair of differential signal of the common output of described first signal output and described secondary signal output, described frequency divider reset circuit also comprises rising edge circuits for triggering that link to each other with described clock signal input terminal, the one trailing edge circuits for triggering that link to each other with described clock signal input terminal, one control circuit that links to each other with described rising edge circuits for triggering and described trailing edge circuits for triggering respectively and a reset signal input that links to each other with described control circuit, described control circuit comprises first inverter that links to each other with described reset signal input, one the second inverter that links to each other with described the first inverter, one the 13 field effect transistor that links to each other with described reset signal input, one the 14 field effect transistor that links to each other with described reset signal input, one the 15 field effect transistor and that links to each other with described the second inverter is connected in the electric capacity between described the first inverter and described the second inverter, described the 13 field effect transistor links to each other with described trailing edge circuits for triggering, and described the 14 field effect transistor and described the 15 field effect transistor link to each other with described rising edge circuits for triggering.
A kind of frequency divider resetting system, be used for a frequency divider, described frequency divider resetting system comprises that one is used for the clock signal input terminal of input one clock signal, one first signal output and a secondary signal output, the a pair of differential signal of the common output of described first signal output and described secondary signal output, described frequency divider reset circuit also comprises one at the rising edge sampling of described clock signal and the rising edge circuits for triggering of output signal, one at the trailing edge sampling of described clock signal and the trailing edge circuits for triggering of output signal, one control circuit that links to each other with described rising edge circuits for triggering and described trailing edge circuits for triggering respectively and one link to each other with described control circuit be used for input one reset signal the reset signal input, described control circuit is controlled the differential signal that described first signal output and described secondary signal output exported and is had fixing original levels when described frequency divider has just been started working.
Relative prior art, frequency divider reset circuit of the present invention and system are so that the differential signal that frequency divider its first signal output and secondary signal output when starting working are exported has fixing original levels, and system configuration and circuit structure are simple.
Description of drawings
Fig. 1 is the system block diagram of frequency divider resetting system preferred embodiments of the present invention.
Fig. 2 is the circuit diagram of frequency divider reset circuit preferred embodiments of the present invention.
Embodiment
See also Fig. 1 and Fig. 2, frequency divider reset circuit of the present invention and system's preferred embodiments comprise control circuit, a reset signal input that links to each other with this control circuit, a first signal output and the secondary signal output that a clock signal input part, rising edge circuits for triggering that link to each other with this clock signal input terminal, trailing edge circuits for triggering, that link to each other with this clock signal input terminal link to each other with these rising edge circuits for triggering and this trailing edge circuits for triggering respectively.
See also Fig. 2, Fig. 2 is the physical circuit figure of frequency divider reset circuit preferred embodiments of the present invention.This clock signal input terminal is used for input one clock signal clk.These rising edge circuits for triggering are used for rising edge sampling and the output signal at clock signal clk.These trailing edge circuits for triggering are used for trailing edge sampling and the output signal at clock signal clk.This reset signal input is used for input one reset signal RESET.This control circuit is used for the original levels of this first signal output of control and this secondary signal output output signal when frequency divider is just started working, and makes the signal of this first signal output and this secondary signal output output have fixing original levels.This first signal output and this secondary signal output are used for exporting a pair of differential signal VOUT+, VOUT-.
These rising edge circuits for triggering comprise one first field effect transistor M1, one second field effect transistor M2, one the 3rd field effect transistor M3, one the 4th field effect transistor M4, one the 5th field effect transistor M5, one the 6th field effect transistor M6 and one the 7th field effect transistor M7.These trailing edge circuits for triggering comprise one the 8th field effect transistor M8, one the 9th field effect transistor M9,1 the tenth field effect transistor M10,1 the 11 field effect transistor M11 and 1 the 12 field effect transistor M12.This control circuit comprises one first inverter INV1, one second inverter INV2,1 the 13 field effect transistor M13,1 the 14 field effect transistor M14,1 the 15 field effect transistor M15 and a capacitor C.
The physical circuit annexation of frequency divider reset circuit preferred embodiments of the present invention is as follows: the grid of this first field effect transistor M1 jointly is connected this clock signal input terminal with the grid of the 8th field effect transistor M8 and links to each other, be used for receiving the clock signal clk of this clock signal input terminal input, the drain electrode of this first field effect transistor M1 links to each other with the source class of this second field effect transistor M2 and the source class of the 3rd field effect transistor M3.The grid of this second field effect transistor M2 links to each other with the grid of the 9th field effect transistor M9, the drain electrode of the tenth field effect transistor M10 and the drain electrode of the 12 field effect transistor M12, the drain electrode of this second field effect transistor M2 links to each other with the grid of the grid of the 11 field effect transistor M11, the 4th field effect transistor M4, the grid of the 6th field effect transistor M6, the drain electrode of the 5th field effect transistor M5, drain electrode and this secondary signal output of the 7th field effect transistor M7, and output difference sub-signal VOUT-.The grid of the 3rd field effect transistor M3 links to each other with the drain electrode of the 9th field effect transistor M9, the grid of the tenth field effect transistor M10 and the drain electrode of the 11 field effect transistor M11, the drain electrode of the 3rd field effect transistor M3 links to each other with the grid of the 5th field effect transistor M5, the grid of the 7th field effect transistor M7, the drain electrode of the 4th field effect transistor M4, the drain electrode of the 6th field effect transistor M6, grid and this first signal output of the 12 field effect transistor M12, and output difference sub-signal VOUT+.The source class of the 4th field effect transistor M4 links to each other with the drain electrode of the 14 field effect transistor M14, and the source class of the 5th field effect transistor M5 links to each other with the drain electrode of the 15 field effect transistor M15.The source class of the 8th field effect transistor M8 links to each other with the drain electrode of the 13 field effect transistor M13, and its drain electrode links to each other with the source class of the 9th field effect transistor M9 and the source class of the tenth field effect transistor M10.This reset signal input links to each other with the input of this first inverter INV1, the grid of the 13 field effect transistor M13 and the grid of the 14 field effect transistor M14, is used for input one reset signal RESET.The output of this first inverter INV1 links to each other with the input of this second inverter INV2 and an end of this capacitor C, and the other end of this capacitor C connects an earth terminal GND, and the output of this second inverter INV2 links to each other with the grid of the 15 field effect transistor M15.The common power end VDD that connects of the source class of the source class of the 13 field effect transistor M13, the source class of the 14 field effect transistor M14 and the 15 field effect transistor M15, the source class of this first field effect transistor M1, the source class of the 6th field effect transistor M6, the source class of the 7th field effect transistor M7, the source class of the 11 field effect transistor M11 and the source class of the 12 field effect transistor M12 connect this earth terminal GND jointly.
The principle Analysis of frequency divider reset circuit preferred embodiments of the present invention is as follows: when the clock signal clk of this clock signal input terminal input by the high level saltus step during to low level, the trailing edge circuits for triggering are sampled to the grid of the 11 field effect transistor M11 and the grid of the 12 field effect transistor M12, and amplify rear output by the positive feedback amplifying circuit that is comprised of the 9th field effect transistor M9 and the tenth field effect transistor M10.When the clock signal clk of this clock signal input terminal input by low transition during to high level, the rising edge circuits for triggering are sampled to the grid of this second field effect transistor M2 and the grid of the 3rd field effect transistor M3, and amplify differential signal VOUT+, the VOUT-of rear output full swing by the positive feedback amplifying circuit that is comprised of the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6 and the 7th field effect transistor M7.Because by the 4th field effect transistor M4, the 5th field effect transistor M5, the gain of the positive feedback amplifying circuit that the 6th field effect transistor M6 and the 7th field effect transistor M7 form is very large, after so this circuit powers on, differential signal VOUT+, VOUT-will inevitably be one high and one low, suppose that differential signal VOUT+ is high level, differential signal VOUT-is low level, when the clock signal clk trailing edge arrives, the 11 field effect transistor M11 and the 12 field effect transistor M12 are with differential signal VOUT+, VOUT-samples, so that voltage end Va is low level, voltage end Vb is high level; When the clock signal clk rising edge arrives, this the second field effect transistor M2 and the 3rd field effect transistor M3 sample to the voltage of voltage end Va, Vb, thereby so that differential signal VOUT+ is low level, differential signal VOUT-is high level, be that differential signal VOUT+, VOUT-change one time level in the one-period of clock signal clk, the cycle of differential signal VOUT+, VOUT-is a times of clock signal clk cycle, the frequency of differential signal VOUT+, VOUT-is half of clock signal clk frequency, thereby has realized the frequency division to clock signal clk.
When frequency divider operation, this reset signal RESET becomes low level by high level, this moment, the 13 field effect transistor M13 and the 14 field effect transistor M14 opened, because this first inverter INV1, the effect of this second inverter INV2 and this capacitor C, the inhibit signal RESET_DELAY that is exported by the output of this second inverter INV2 lags behind reset signal RESET, therefore when the 13 field effect transistor M13 and the 14 field effect transistor M14 unlatching, because inhibit signal RESET_DELAY still keeps high level, the 15 field effect transistor M15 still is in closed condition, can infer that this moment, differential signal VOUT-was low level, again because the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6 and the 7th field effect transistor M7 have formed positive feedback path, so differential signal VOUT+ can very fast quilt draws and is high level.Be that differential signal VOUT+, VOUT-have fixing original levels when frequency divider is started working, and be not subjected to the impact of external environment.
Frequency divider reset circuit of the present invention and system are so that the differential signal of frequency divider its first output and the second output output when starting working has fixing original levels, and system configuration and circuit structure are simple.
Claims (2)
1. frequency divider reset circuit, comprise a clock signal input part, one first signal output and a secondary signal output, the a pair of differential signal of the common output of described first signal output and described secondary signal output, it is characterized in that: described frequency divider reset circuit also comprises rising edge circuits for triggering that link to each other with described clock signal input terminal, the one trailing edge circuits for triggering that link to each other with described clock signal input terminal, one control circuit that links to each other with described rising edge circuits for triggering and described trailing edge circuits for triggering respectively and a reset signal input that links to each other with described control circuit, described control circuit comprises first inverter that links to each other with described reset signal input, one the second inverter that links to each other with described the first inverter, one the 13 field effect transistor that links to each other with described reset signal input, one the 14 field effect transistor that links to each other with described reset signal input, one the 15 field effect transistor and that links to each other with described the second inverter is connected in the electric capacity between described the first inverter and described the second inverter, described the 13 field effect transistor links to each other with described trailing edge circuits for triggering, and described the 14 field effect transistor and described the 15 field effect transistor link to each other with described rising edge circuits for triggering; Described reset signal input links to each other with the grid of the input of described the first inverter, described the 13 field effect transistor and the grid of described the 14 field effect transistor, the output of described the first inverter links to each other with the input of described the second inverter and an end of described electric capacity, the other end of described electric capacity connects an earth terminal, the output of described the second inverter links to each other with the grid of described the 15 field effect transistor, the common power end that connects of the source electrode of the source electrode of described the 13 field effect transistor, the source electrode of described the 14 field effect transistor and described the 15 field effect transistor; Described rising edge circuits for triggering comprise first field effect transistor that links to each other with described clock signal input terminal, one the second field effect transistor that links to each other with described the first field effect transistor, one the 3rd field effect transistor that links to each other with described the first field effect transistor, one the 4th field effect transistor that links to each other with described first signal output respectively, one the 5th field effect transistor, one the 6th field effect transistor and one the 7th field effect transistor, and described secondary signal output respectively with described the 4th field effect transistor, described the 5th field effect transistor, described the 6th field effect transistor and described the 7th field effect transistor connect, and described trailing edge circuits for triggering comprise the 8th field effect transistor that links to each other with described clock signal input terminal, one the 9th field effect transistor that links to each other with described the 8th field effect transistor, one the tenth field effect transistor that links to each other with described the 8th field effect transistor, one the 11 field effect transistor that links to each other with described secondary signal output and the 12 field effect transistor that links to each other with described first signal output; The grid of described the first field effect transistor jointly is connected described clock signal input terminal with the grid of described the 8th field effect transistor and links to each other, the drain electrode of described the first field effect transistor links to each other with the source electrode of described the second field effect transistor and the source electrode of described the 3rd field effect transistor, the grid of the grid of described the second field effect transistor and described the 9th field effect transistor, the drain electrode of described the tenth field effect transistor and the drain electrode of described the 12 field effect transistor link to each other, the drain electrode of described the second field effect transistor and the grid of described the 11 field effect transistor, the grid of described the 4th field effect transistor, the grid of described the 6th field effect transistor, the drain electrode of described the 5th field effect transistor, the drain electrode of described the 7th field effect transistor and described secondary signal output link to each other; The grid of described the 3rd field effect transistor links to each other with the grid of the drain electrode of described the 9th field effect transistor, described the tenth field effect transistor and the drain electrode of described the 11 field effect transistor, and the drain electrode of described the 3rd field effect transistor links to each other with grid and the described first signal output of the drain electrode of the grid of the grid of described the 5th field effect transistor, described the 7th field effect transistor, described the 4th field effect transistor, the drain electrode of described the 6th field effect transistor, described the 12 field effect transistor; The source electrode of described the 4th field effect transistor links to each other with the drain electrode of described the 14 field effect transistor, the source electrode of described the 5th field effect transistor links to each other with the drain electrode of described the 15 field effect transistor, the source electrode of described the 8th field effect transistor links to each other with the drain electrode of described the 13 field effect transistor, and the drain electrode of described the 8th field effect transistor links to each other with the source electrode of described the 9th field effect transistor and the source electrode of described the tenth field effect transistor; The common earth terminal that connects of the source electrode of the source electrode of the source electrode of the source electrode of described the first field effect transistor, described the 6th field effect transistor, described the 7th field effect transistor, the source electrode of described the 11 field effect transistor and described the 12 field effect transistor.
2. frequency divider resetting system, be used for a frequency divider, described frequency divider resetting system comprises that one is used for the clock signal input terminal of input one clock signal, one first signal output and a secondary signal output, the a pair of differential signal of the common output of described first signal output and described secondary signal output, it is characterized in that: described frequency divider resetting system also comprises one at the rising edge sampling of described clock signal and the rising edge circuits for triggering of output signal, one at the trailing edge sampling of described clock signal and the trailing edge circuits for triggering of output signal, one control circuit that links to each other with described rising edge circuits for triggering and described trailing edge circuits for triggering respectively and one link to each other with described control circuit be used for input one reset signal the reset signal input, described control circuit is controlled the differential signal that described first signal output and described secondary signal output exported and is had fixing original levels when described frequency divider has just been started working, described control circuit comprises first inverter that links to each other with described reset signal input, one the second inverter that links to each other with described the first inverter, one the 13 field effect transistor that links to each other with described reset signal input, one the 14 field effect transistor that links to each other with described reset signal input, one the 15 field effect transistor and that links to each other with described the second inverter is connected in the electric capacity between described the first inverter and described the second inverter, described the 13 field effect transistor links to each other with described trailing edge circuits for triggering, and described the 14 field effect transistor and described the 15 field effect transistor link to each other with described rising edge circuits for triggering; Described reset signal input links to each other with the grid of the input of described the first inverter, described the 13 field effect transistor and the grid of described the 14 field effect transistor, the output of described the first inverter links to each other with the input of described the second inverter and an end of described electric capacity, the other end of described electric capacity connects an earth terminal, the output of described the second inverter links to each other with the grid of described the 15 field effect transistor, the common power end that connects of the source electrode of the source electrode of described the 13 field effect transistor, the source electrode of described the 14 field effect transistor and described the 15 field effect transistor; Described rising edge circuits for triggering comprise first field effect transistor that links to each other with described clock signal input terminal, one the second field effect transistor that links to each other with described the first field effect transistor, one the 3rd field effect transistor that links to each other with described the first field effect transistor, one the 4th field effect transistor that links to each other with described first signal output respectively, one the 5th field effect transistor, one the 6th field effect transistor and one the 7th field effect transistor, and described secondary signal output respectively with described the 4th field effect transistor, described the 5th field effect transistor, described the 6th field effect transistor and described the 7th field effect transistor connect, and described trailing edge circuits for triggering comprise the 8th field effect transistor that links to each other with described clock signal input terminal, one the 9th field effect transistor that links to each other with described the 8th field effect transistor, one the tenth field effect transistor that links to each other with described the 8th field effect transistor, one the 11 field effect transistor that links to each other with described secondary signal output and the 12 field effect transistor that links to each other with described first signal output; The grid of described the first field effect transistor jointly is connected described clock signal input terminal with the grid of described the 8th field effect transistor and links to each other, the drain electrode of described the first field effect transistor links to each other with the source electrode of described the second field effect transistor and the source electrode of described the 3rd field effect transistor, the grid of the grid of described the second field effect transistor and described the 9th field effect transistor, the drain electrode of described the tenth field effect transistor and the drain electrode of described the 12 field effect transistor link to each other, the drain electrode of described the second field effect transistor and the grid of described the 11 field effect transistor, the grid of described the 4th field effect transistor, the grid of described the 6th field effect transistor, the drain electrode of described the 5th field effect transistor, the drain electrode of described the 7th field effect transistor and described secondary signal output link to each other; The grid of described the 3rd field effect transistor links to each other with the grid of the drain electrode of described the 9th field effect transistor, described the tenth field effect transistor and the drain electrode of described the 11 field effect transistor, and the drain electrode of described the 3rd field effect transistor links to each other with grid and the described first signal output of the drain electrode of the grid of the grid of described the 5th field effect transistor, described the 7th field effect transistor, described the 4th field effect transistor, the drain electrode of described the 6th field effect transistor, described the 12 field effect transistor; The source electrode of described the 4th field effect transistor links to each other with the drain electrode of described the 14 field effect transistor, the source electrode of described the 5th field effect transistor links to each other with the drain electrode of described the 15 field effect transistor, the source electrode of described the 8th field effect transistor links to each other with the drain electrode of described the 13 field effect transistor, and the drain electrode of described the 8th field effect transistor links to each other with the source electrode of described the 9th field effect transistor and the source electrode of described the tenth field effect transistor; The common earth terminal that connects of the source electrode of the source electrode of the source electrode of the source electrode of described the first field effect transistor, described the 6th field effect transistor, described the 7th field effect transistor, the source electrode of described the 11 field effect transistor and described the 12 field effect transistor.
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| CN 201110213434 CN102355244B (en) | 2011-07-28 | 2011-07-28 | Frequency divider resetting circuit and system |
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| CN 201110213434 CN102355244B (en) | 2011-07-28 | 2011-07-28 | Frequency divider resetting circuit and system |
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| CN102355244B true CN102355244B (en) | 2013-04-24 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3754391A (en) * | 1970-12-26 | 1973-08-28 | Suwa Seikosha Kk | Driving arrangement for quartz vibrator timepieces |
| CN1196509A (en) * | 1997-04-14 | 1998-10-21 | 精工爱普生株式会社 | Oscillation circuit, electronic circuit and semiconductor device, electronic equipment, and timepiece |
| US6181209B1 (en) * | 1998-12-04 | 2001-01-30 | Winbond Electronics Corp. | All-digital frequency following system |
| CN1510860A (en) * | 2002-12-24 | 2004-07-07 | 深圳市中兴通讯股份有限公司 | Frequency locking testing circuit of lock phase ring |
| CN202145636U (en) * | 2011-07-28 | 2012-02-15 | 四川和芯微电子股份有限公司 | Frequency divider reset circuit |
-
2011
- 2011-07-28 CN CN 201110213434 patent/CN102355244B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3754391A (en) * | 1970-12-26 | 1973-08-28 | Suwa Seikosha Kk | Driving arrangement for quartz vibrator timepieces |
| CN1196509A (en) * | 1997-04-14 | 1998-10-21 | 精工爱普生株式会社 | Oscillation circuit, electronic circuit and semiconductor device, electronic equipment, and timepiece |
| US6181209B1 (en) * | 1998-12-04 | 2001-01-30 | Winbond Electronics Corp. | All-digital frequency following system |
| CN1510860A (en) * | 2002-12-24 | 2004-07-07 | 深圳市中兴通讯股份有限公司 | Frequency locking testing circuit of lock phase ring |
| CN202145636U (en) * | 2011-07-28 | 2012-02-15 | 四川和芯微电子股份有限公司 | Frequency divider reset circuit |
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