CN102332533A - Hole-transmission type organic thin-film transistor and manufacturing method thereof - Google Patents
Hole-transmission type organic thin-film transistor and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a hole-transmission type organic thin-film transistor and a manufacturing method thereof. The hole-transmission type organic thin-film transistor has a bottom gate top contacting type or bottom gate bottom contacting type structure and comprises a substrate, a gate electrode, a gate insulation layer, a first transition layer, a P type organic semiconductor layer, a source electrode and a drain electrode, wherein the P type organic semiconductor layer comprises a first organic semiconductor layer and a second organic semiconductor layer; a hole barrier layer is arranged between the first organic semiconductor layer and the second organic semiconductor layer; and a second transition layer is arranged between the hole barrier layer and the second organic semiconductor layer. In the hole-transmission type organic thin-film transistor, a hole barrier layer is inserted into organic functional layers so as to turn a traditional single-channel transmission mode into a double-layer channel transmission mode, and the insulation layer and the hole barrier layer are respectively provided with a transition layer so as to promote the crystallizing degree of two organic functional layers and further to approach high migration rate characteristics of a mono-crystal organic transistor, thereby greatly lowering the manufacturing cost and being more suitable for large-scale industrialized production.
Description
Technical field
The present invention relates to technical field of electronic components, relate in particular to a kind of hole-transporting type OTFT and preparation method thereof.
Background technology
Since people such as Tsumura in 1986 have reported first OTFT (Organic thin film transistors; Be called for short OTFT), OTFT is because its potential using value at aspects such as Active Matrix LCD At, organic integration circuit, electronic trademark and transducers has obtained people's extensive concern.OTFT can be divided into electron-transporting type OTFT and hole-transporting type OTFT according to the difference of transmission carrier electric charge type.Charge carrier is an electronics in the electric transmission transistor npn npn, and electric charge is for negative; And charge carrier is the hole in the hole transport transistor npn npn, and electric charge is for just.
Field-effect mobility is as one of most important performance index of transistor; Compare electron-transporting OTFT; Hole-transporting type OTFT has better air stability; Through people's continuous effort, the mobility of the hole-transporting type organic transistor of based single crystal has has met or exceeded the inorganic transistors based on amorphous silicon.But the organic transistor of monocrystalline is very harsh to the preparation environmental requirement, thereby has improved preparation cost, and this has limited transistorized further developing greatly.Therefore, can effectively improve the performance of device based on the organic transistor of polycrystalline attitude through the structure preparation of reasonable change organic transistor.This also is a hole-transporting type OTFT problem demanding prompt solution.
Summary of the invention
To above-mentioned prior art, the technical problem that the present invention will solve provides a kind of high-performance, low-cost hole-transporting type OTFT based on the polycrystalline attitude and preparation method thereof.
In order to solve the problems of the technologies described above; The present invention adopts following technical scheme: a kind of hole-transporting type OTFT; Its structure is a contact at the bottom of touch of bottom gate apical grafting or the bottom gate; Comprise substrate, gate electrode, gate insulator, first transition zone, P type organic semiconductor layer, source electrode and drain electrode; Said P type organic semiconductor layer comprises first organic semiconductor layer and second organic semiconductor layer, is provided with hole blocking layer at first organic semiconductor layer and the second organic semiconductor interlayer, is provided with second transition zone at the hole blocking layer and the second organic semiconductor interlayer.
Further, said first transition zone and said second transition zone are processed by the thiophene-based organic material, and thickness is 0.5 ~ 5 nm.
Further, said hole blocking layer is made up of one or more of hole barrier materials, and thickness is 0.5 ~ 20 nm, and described hole barrier materials comprises metal organic complex, pyridines, o-phenanthroline Lei 、 oxadiazole class, glyoxaline compound material.
Further; Said first semiconductor layer and second semiconductor layer are one or both in the hole-transporting type organic semiconducting materials; The thickness of each layer is 10 ~ 100 nm, and said hole-transporting type organic semiconducting materials comprises aromatic series compounds, thiophene-based material, phthalocyanine dye.
Further, said gate insulator is processed by inorganic insulating material or organic insulating material, and thickness is 50 ~ 2000 nm.
Further, said gate electrode, source electrode and leak electricity very metal or conductive film, wherein, source electrode and drain electrode thickness are 10 ~ 300 nm.
A kind of preparation method of hole-transporting type OTFT comprises the steps:
1. earlier substrate is cleaned completely, it is dry to clean the back;
2. prepare gate electrode at substrate surface;
3. handle at gate electrode above-prepared gate insulator and to insulating barrier;
4. on said gate insulator, prepare first transition zone;
5. on transition zone, prepare first organic semiconductor layer;
6. prepare hole blocking layer;
7. on said hole blocking layer, prepare second transition zone;
8. on second transition zone, prepare second organic semiconductor layer;
9. on second organic semiconductor layer, prepare source electrode and drain electrode;
Step is the 3. 4. 5. 6. 7. 8. organic semiconductor layer described in 9. 2.; Transition zone; Electrode layer and gate insulator are through vacuum evaporation; Ion cluster bundle deposition; Ion plating; Dc sputtering deposition; The radio frequency sputtering plated film; Ion beam sputtering deposition; Ion beam assisted depositing; Plasma reinforced chemical vapour deposition; High density inductance coupling high formula plasma source chemical vapor deposition; The catalyst chemical vapour deposition (CVD); Magnetron sputtering; Electroplate; Spin coating; Dip-coating; Inkjet printing; Roller coat; One or several modes in the LB film form.
A kind of preparation method of hole-transporting type OTFT comprises the steps:
1. earlier substrate is cleaned completely, it is dry to clean the back;
2. prepare gate electrode at substrate surface;
3. handle at gate electrode above-prepared gate insulator and to insulating barrier;
4. on said gate insulator, prepare source electrode and drain electrode;
5. between source electrode and drain electrode, prepare first transition zone;
6. on source electrode, drain electrode, first transition zone, prepare first organic semiconductor layer;
7. on first organic semiconductor layer, prepare hole blocking layer;
8. on said hole blocking layer, prepare second transition zone;
9. on second transition zone, prepare second organic semiconductor layer;
Step is the 3. 4. 5. 6. 7. 8. organic semiconductor layer described in 9. 2.; Transition zone; Electrode layer and gate insulator are through vacuum evaporation; Ion cluster bundle deposition; Ion plating; Dc sputtering deposition; The radio frequency sputtering plated film; Ion beam sputtering deposition; Ion beam assisted depositing; Plasma reinforced chemical vapour deposition; High density inductance coupling high formula plasma source chemical vapor deposition; The catalyst chemical vapour deposition (CVD); Magnetron sputtering; Electroplate; Spin coating; Dip-coating; Inkjet printing; Roller coat; One or several modes in the LB film form.
Compared with prior art; The present invention has following beneficial effect: hole-transporting type OTFT provided by the invention has adopted novel sandwich construction, promptly tell between the two-layer organic semiconductor layer to add on one deck hole blocking layer and said gate insulator and the hole blocking layer and prepared transition zone respectively.Through suitably introducing hole blocking layer, make device form two raceway grooves, reduced under the high bias condition that charge carrier collides each other in the transistor channel, scattering and quenching phenomenon, and then the output current of device and switch current ratio also are improved; Through suitably introducing transition zone at two channel interface places, make organic semiconductor layer better form the amorphous pattern, the hole transport speed of higher organic film is provided, and then has promoted transmittability and the carrier mobility of hole in raceway groove significantly; Organic film can reduce the trap of hole in film equally under good crystalline state; Therefore; The introducing of transition zone can reduce the threshold voltage of device significantly; Thereby make the approaching expensive monocrystalline OTFT of performance of the device of sandwich construction, reach the purpose that reduces cost, large-scale industrialized production preferably.
Description of drawings
Fig. 1 is a bottom gate apical grafting touch hole-transporting type OTFT structural representation of the present invention;
Fig. 2 is contact hole-transporting type OTFT structural representation at the bottom of the bottom gate of the present invention.
Wherein, 1 is substrate, and 2 is gate electrode, and 3 is gate insulator, and 4 is first transition zone, and 5 is first organic semiconductor layer, and 6 is hole blocking layer, and 7 is second transition zone, and 8 is second organic semiconductor layer, and 9 is the source electrode, and 10 is drain electrode.
Embodiment
To combine accompanying drawing and embodiment that the present invention is done further description below.
Like Fig. 1, shown in Figure 2, a kind of hole-transporting type OTFT provided by the invention, the structure of device comprises substrate 1; Gate electrode 2, gate insulator 3, the first transition zones 4; First organic semiconductor layer 5, hole blocking layer 6, the second transition zones 7; Second organic semiconductor layer 8, source electrode 9, drain electrode 10.
Said substrate 1 is rigid substrate or flexible substrate, and a kind of in silicon chip, glass, thin polymer film and the metal forming has the ability of certain anti-steam and oxygen infiltration, and surface smoothness is preferably arranged.
Said gate electrode 2; Source electrode 9 and drain electrode 10 are to constitute by having low-resistance material, comprise; But be not limited to; Gold (Au), silver (Ag), magnesium (Mg), aluminium (Al), copper (Cu), calcium (Ca), barium (Ba), nickel metal and alloy materials thereof such as (Ni), metal oxide is like tin indium oxide (ITO); Zinc-tin oxide (IZO) conductive film and conducing composite material (like gold size, elargol, carbon paste etc.), the preparation method can be various deposition processs such as the chemical vapour deposition (CVD) that strengthens of vacuum thermal evaporation, magnetron sputtering, plasma, silk screen printing, printing, spin coating.The thickness of said source electrode 9 and drain electrode 10 is 10 ~ 300 nm.
Described gate insulator 3 has excellent dielectric properties; Material comprises inorganic insulating material such as silicon dioxide (SiO2), silicon nitride (Si3N4), aluminium oxide (Al2O3), lithium fluoride (LiF), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5); Organic insulating material such as polyvinyl alcohol (PVA), polyvinyl chloride (PVC), polyvinylpyrrolidone (PVP), polystyrene (PS), polymethyl methacrylate (PMMA), gather ethyl propylene acid esters (PCA), polytetrafluoroethylene (PTFE) etc., the preparation method can be chemical vapour deposition (CVD), thermal oxidation, spin coating or the vacuum evaporation etc. that plasma strengthens.The thickness of said gate insulator is 50 ~ 2000 nm.
Said first transition zone 4 and second transition zone 7 are processed by the thiophene-based organic material, comprise fluoro six thiophene (DFH-6T), chloro six thiophene (DCIH-6T), 2,5-2 4-xenyl thiophene (BP2T), 5,5 ' ' ' '-two (2-naphthyl)-2; 2 '-two thiophene (NaT2), 5,5 ' ' ' '-two (2-naphthyl)-2,2 ': 5 ', 2 ' '-three thiophene (NaT3), 5,5 ' ' ' '-two (2-naphthyl)-2; 2 ': 5 ', 2 ' ': 5 ' ', 2 ' ' '-four thiophene (NaT4), 5,5 ' ' ' '-two (2-naphthyl)-2,2 ': 5 '; 2 ' ': 5 ' ', 2 ' ' ': 5 ' ' ', 2 ' ' ' '-five thiophene (NaT5), 5,5 ' ' ' '-two (2-naphthyl)-2,2 ': 5 '; 2 ' ': 5 ' ', 2 ' ' ': 5 ' ' ', 2 ' ' ' ': 5 ' ' ' ', 2 ' ' ' '-six thiophene (NaT6), 2,5-two (2-naphthyl)-[3; 2-b] and two thiophene (NaTT2), 5,5 '-two (2-thianaphthenyl)-2,2 '-two thiophene (TNT2), 5,5 ' '-two (2-thianaphthenyl)-2,2 ': 5 '; 2 ' ' thiophene (TNT3), 5,5 ' '-two (2-thianaphthenyl)-2,2 ': 5 ', 2 '-three ': 5 ' ', 2 ' ' and '-four thiophene (TNT4), 5; 5 ' ' (2-thianaphthenyl)-2,2 ': 5 ', 2 '-two ': 5 ' ', 2 ' ' and '-four thiophene (TNT4), 5; 5 ' ' (2-thianaphthenyl)-2,2 ': 5 ', 2 '-two ': 5 ' ', 2 ' ' ': 5 ' ' '; 2 ' ' thiophene (TNT5), 2 ' '-five, 5-two (2-thianaphthenyl)-[3,2-b] and two thiophene (TNTT), 5,5 '-two (2-thianaphthenyl)-2; 2 '-[3,2-b] and two thiophene (TNTT2), 5,5 '-two (2-phenanthryl)-2,2 '-two thiophene (PhT2), 5; 5 '-two (2-phenanthryl)-2,2 ': 5 ', 2 ' '-three thiophene (PhT3), 5,5 '-two (2-phenanthryl)-2; 2 ': 5 ', 2 ' ': 5 ' ', 2 ' ' '-four thiophene (PhT4), 2,5 (2-phenanthryl)-[3; 2-b] and two thiophene (PhTT), 5,5 '-two (2-phenanthryl)-2,2 ' and two thiophene (PhTT2), polythiophene (Polythiophene, PT) 3-hexyl substituting polythiophene (P3HT); The thickness of said transition zone is 0.5 ~ 5 nm.
Said first organic semiconductor layer 5 and second organic semiconductor layer 8 adopt the hole-transporting type organic material with field effect behavior to process, and include, but not limited to aromatic series compounds, thiophene-based material or phthalocyanine dye.Wherein, the aromatic series compounds comprises pentacene, aphthacene, anthracene, rubrene.Wherein, the thiophene-based material comprise six thiophene (alpha-6T), gather (3-alkylthrophene) (P3AT), 3-hexyl substituting polythiophene (P3HT).Wherein, phthalocyanine dye CuPc (CuPc), Phthalocyanine Zinc (ZnPc), phthalocyanine nickel (NiPc), phthalocyanine cobalt (CoPc), free cyanines nickel (H2Pc), phthalocyanine platinum (PtPc), phthalocyanine plumbous (PbPc).The thickness of said each layer organic semiconductor layer is 10 ~ 100 nm.
Said hole blocking layer 6 is made up of one or more of hole barrier materials, and described hole barrier materials comprises a kind of material in metal organic complex, pyridines, o-phenanthroline Lei 、 oxadiazole class or the glyoxaline compound material.Wherein metal organic complex comprises oxine aluminium (Alq3) or two (2-methyl-8-quino)-4-(phenylphenol) aluminium (BAlq), pyridine compounds and their [2,4,6-trimethyl-3-(phenyl of pyridine-3-yl)]-borine (3TPYMB) that comprises three; The o-phenanthroline compounds comprises 2,9-dimethyl-4,7-biphenyl-1,10-phenanthrolene (BCP) or 4,7-biphenyl-1,10-phenanthrolene (BPhen); Oxadiazole class material is 2-(4-diphenyl)-5-(4-2-methyl-2-phenylpropane base)-1,3,4-oxadiazole (PBD) or 1,3-two [(4-tertiary amine-butyl phenyl)-1,3,4-diazo acid-5-yl] benzene (OXD-7); The imidazoles material is 1,3,5-three (N-phenyl-benzimidazolyl-2 radicals) benzene (TPBi).This hole blocking layer 6 and second transition zone 7 on it are positioned in the middle of first organic semiconductor layer 5 and second organic semiconductor layer 8, and the thickness of said hole blocking layer 6 is 0.5 ~ 20 nm.
The film build method of said first organic semiconductor layer 5, second organic semiconductor layer 8 and hole blocking layer 6 when material is small molecule material, adopts vacuum evaporation, spin coating, drips film, impression, printing, gas blowout; When material is polymeric material, adopts spin coating, drip film, printing, gas blowout.
Below be specific embodiment of the present invention:
Device architecture is as shown in Figure 1, is bottom gate apical grafting touch structure.Material of each layer of device and thickness are: substrate 1 is glass; Gate electrode 2 is ITO (180 nm); Gate insulator 3 is PMMA (500 nm), and first transition zone 4 and second transition zone 7 are six thiophene (2 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 8 are CuPc (25 nm); Hole blocking layer 6 is TPBi (5 nm), and source electrode 9 is Au (50 nm) with drain electrode 10.
The preparation method of this hole-transporting type OTFT is following:
1. earlier the glass substrate of the good ITO of sputter is cleaned completely, clean the back and dry up with drying nitrogen;
2. adopt spin-coating method on ITO, to prepare the PMMA film and form gate insulator;
3. to the good PMMA film of spin coating through the row heated baking;
4. adopt vacuum evaporation to prepare the one or six thiophene transition zone;
5. adopt vacuum evaporation to prepare the organic semiconductor layer of ground floor CuPc;
6. adopt vacuum evaporation to prepare the TPBi hole blocking layer;
7. adopt vacuum evaporation to prepare the two or six thiophene transition zone;
8. adopt vacuum evaporation to prepare second layer CuPc organic semiconductor layer;
9. adopt vacuum evaporation to prepare source electrode and drain electrode;
10. device is tested under atmospheric environment;
Transistorized structure is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate 1 is glass; Gate electrode 2 is ITO (180 nm); Gate insulator 3 is PS (50 nm), and first transition zone 4 and second transition zone 7 are six thiophene (2 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 6 are CuPc (25 nm); Hole blocking layer 6 is TPBi (5 nm), and source electrode 9 is Au (50 nm) with drain electrode 10.
Transistorized preparation flow is similar with embodiment 1.
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate 1 is glass; Gate electrode 2 is ITO (180 nm); Gate insulator 3 is PVA (2000 nm), and first transition zone 4 and second transition zone 7 are six thiophene (2 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 6 are CuPc (25 nm); Hole blocking layer 6 is BCP (5 nm), and source electrode 9 is Au (50 nm) with drain electrode 10.
Transistorized preparation flow is similar with embodiment 1.
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate 1 is glass; Gate electrode 2 is ITO (180 nm); Gate insulator 3 is PS (500 nm), and first transition zone 4 and second transition zone 7 are six thiophene (0.5 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 8 are CuPc (25 nm); Hole blocking layer 6 is BCP (5 nm), and source electrode 9 is Au (50 nm) with drain electrode 10.
Transistorized preparation flow is similar with embodiment 1.
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate 1 is glass; Gate electrode 2 is ITO (180 nm); Gate insulator 3 is PMMA (500 nm), and first transition zone 4 and second transition zone 7 are six thiophene (5 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 8 are CuPc (25 nm); Hole blocking layer is TPBi (5 nm), and source electrode and drain electrode are Ag (50 nm).
Transistorized preparation flow is similar with embodiment 1.
Embodiment 6
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate 1 is glass; Gate electrode 2 is ITO (180 nm); Gate insulator 3 is PMMA (500 nm), and first transition zone 4 and second transition zone 7 are 3-hexyl substituting polythiophene (2 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 8 are CuPc (10 nm); Hole blocking layer 6 is TPBi (5 nm), and source electrode 9 is Au (50 nm) with drain electrode 10.
Transistorized preparation flow is similar with embodiment 1.
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate 1 is glass; Gate electrode 2 is ITO (180 nm); Gate insulator 3 is PMMA (500 nm), and first transition zone 4 and second transition zone 7 are six thiophene (2 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 8 are pentacene (100 nm); Hole blocking layer 6 is BCP (5 nm), and source electrode 9 is Au (50 nm) with drain electrode 10.
Transistorized preparation flow is similar with embodiment 1.
Transistor arrangement is as shown in Figure 2.Material of each layer of transistor and thickness are: substrate 1 is silicon chip; Gate electrode 2 is silicon (300 nm); Gate insulator 3 is SiO2 (200 nm), and first transition zone 4 and second transition zone 7 are six thiophene (2 nm), and first organic semiconductor layer 5 and second organic semiconductor layer 8 are CuPc (25 nm); Hole blocking layer 6 is TPBi (5 nm), and source electrode 9 is Au (50 nm) with drain electrode 10.
The preparation method of this OTFT is following:
1. earlier silicon substrate is cleaned completely, clean the back and dry up with drying nitrogen;
2. adopt the method for thermal oxidation or vapour deposition to generate one deck SiO2 as gate insulator;
3. the method through vacuum evaporation or sputter prepares source electrode and drain electrode on the SiO2 surface;
4. adopt vacuum evaporation to prepare the one or six thiophene transition zone;
5. adopt vacuum evaporation to prepare the first CuPc organic semiconductor layer;
6. adopt vacuum evaporation to prepare the TPBi hole blocking layer;
7. adopt vacuum evaporation to prepare the two or six thiophene transition zone;
8. adopt vacuum evaporation to prepare the second CuPc organic semiconductor layer;
9. transistor is tested under atmospheric environment;
Transistor arrangement is as shown in Figure 2.Material of each layer of transistor and thickness are: adopt silicon substrate; Gate electrode is silicon (300 nm); Gate insulator is SiO2 (200 nm), and first transition zone and second transition zone are six thiophene (2 nm), and first organic semiconductor layer and second organic semiconductor layer are CuPc (25 nm); Hole blocking layer is TPBi (5 nm), and source electrode and drain electrode are Ag (10 nm).
Transistorized preparation flow is similar with embodiment 8.
Transistor arrangement is as shown in Figure 2.Material of each layer of transistor and thickness are: adopt silicon substrate; Gate electrode is silicon (300 nm); Gate insulator is SiO2 (200 nm), and first transition zone and second transition zone are six thiophene (2 nm), and first organic semiconductor layer and second organic semiconductor layer are CuPc (25 nm); Hole blocking layer is Bphen (5 nm), and source electrode and drain electrode are Au (300 nm).
Transistorized preparation flow is similar with embodiment 8.
Embodiment 11
Transistor arrangement is as shown in Figure 2.Material of each layer of transistor and thickness are: adopt silicon substrate; Gate electrode is silicon (300 nm); Gate insulator is SiO2 (200 nm), and first transition zone and second transition zone are six thiophene (2 nm), and first organic semiconductor layer and second organic semiconductor layer are CuPc (25 nm); Hole blocking layer is BCP (0.5 nm), and source electrode and drain electrode are Au (300 nm).
Transistorized preparation flow is similar with embodiment 8.
Embodiment 12
Transistor arrangement is as shown in Figure 2.Material of each layer of transistor and thickness are: adopt silicon substrate; Gate electrode is silicon (300 nm); Gate insulator is SiO2 (200 nm), and first transition zone and second transition zone are six thiophene (2 nm), and first organic semiconductor layer and second organic semiconductor layer are pentacene (25 nm); Hole blocking layer is BCP (20 nm), and source electrode and drain electrode are Au (300 nm).
Transistorized preparation flow is similar with embodiment 8.
Embodiment 13
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate is a glass; Gate electrode is Al (10 nm); Gate insulator is PMMA (500 nm), and first transition zone and second transition zone are six thiophene (2 nm), and first organic semiconductor layer and second organic semiconductor layer are pentacene (100 nm); Hole blocking layer is BCP (5 nm), and source electrode and drain electrode are Au (50 nm).
The preparation method of this OTFT is following:
1. earlier glass substrate is cleaned completely, clean the back and dry up with drying nitrogen;
2. prepare one deck Al conductive membrane layer as grid at glass substrate surface through vacuum evaporation;
3. adopt vacuum evaporation to prepare one deck LiF as gate insulator;
4. adopt vacuum evaporation to prepare the one or six thiophene transition zone;
5. adopt vacuum evaporation to prepare the first pentacene organic semiconductor layer;
6. adopt vacuum evaporation to prepare the BCP hole blocking layer;
7. adopt vacuum evaporation to prepare the two or six thiophene transition zone;
8. adopt vacuum evaporation to prepare the second pentacene organic semiconductor layer;
9. adopt vacuum evaporation to prepare source electrode and drain electrode;
10. transistor is tested under atmospheric environment;
Embodiment 14
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate is a glass; Gate electrode is Al (100 nm); Gate insulator is LiF (500 nm), and first transition zone and second transition zone are chloro six thiophene (2 nm), and first organic semiconductor layer and second organic semiconductor layer are pentacene (100 nm); Hole blocking layer is Bphen (10 nm), and source electrode and drain electrode are Au (50 nm).
Transistorized preparation flow is similar with embodiment 13.
Embodiment 15
Transistor arrangement is as shown in Figure 1.Material of each layer of transistor and thickness are: substrate is a glass; Gate electrode is Al (100 nm), and gate insulator is LiF (500 nm), and first transition zone and second transition zone are chloro six thiophene (2 nm); First organic semiconductor layer is CuPc (25 nm); Second organic semiconductor layer is pentacene (100 nm), and hole blocking layer is Bphen (10 nm), and source electrode and drain electrode are Au (50 nm).
Transistorized preparation flow is similar with embodiment 13.
Claims (8)
1. hole-transporting type OTFT; Its structure is a contact at the bottom of touch of bottom gate apical grafting or the bottom gate; Comprise substrate, gate electrode, gate insulator, first transition zone, P type organic semiconductor layer, source electrode and drain electrode; It is characterized in that: said P type organic semiconductor layer comprises first organic semiconductor layer and second organic semiconductor layer; Be provided with hole blocking layer at first organic semiconductor layer and the second organic semiconductor interlayer, be provided with second transition zone at the hole blocking layer and the second organic semiconductor interlayer.
2. hole-transporting type OTFT according to claim 1 is characterized in that: said first transition zone and said second transition zone are processed by the thiophene-based organic material, and thickness is 0.5 ~ 5 nm.
3. hole-transporting type OTFT according to claim 1 and 2; It is characterized in that: said hole blocking layer is made up of one or more of hole barrier materials; Thickness is 0.5 ~ 20 nm, and described hole barrier materials comprises metal organic complex, pyridines, o-phenanthroline Lei 、 oxadiazole class, glyoxaline compound material.
4. hole-transporting type OTFT according to claim 1; It is characterized in that: said first semiconductor layer and second semiconductor layer are one or both in the hole-transporting type organic semiconducting materials; The thickness of each layer is 10 ~ 100 nm, and said hole-transporting type organic semiconducting materials comprises aromatic series compounds, thiophene-based material, phthalocyanine dye.
5. hole-transporting type OTFT according to claim 1 is characterized in that: said gate insulator is processed by inorganic insulating material or organic insulating material, and thickness is 50 ~ 2000 nm.
6. hole-transporting type OTFT according to claim 1 is characterized in that: said gate electrode, source electrode and leak electricity very metal or conductive film, wherein, source electrode and drain electrode thickness are 10 ~ 300 nm.
7. the preparation method of a hole-transporting type OTFT is characterized in that, comprises the steps: 1. earlier substrate to be cleaned completely, and it is dry to clean the back;
2. prepare gate electrode at substrate surface;
3. handle at gate electrode above-prepared gate insulator and to insulating barrier;
4. on said gate insulator, prepare first transition zone;
5. on transition zone, prepare first organic semiconductor layer;
6. prepare hole blocking layer;
7. on said hole blocking layer, prepare second transition zone;
8. on second transition zone, prepare second organic semiconductor layer;
9. on second organic semiconductor layer, prepare source electrode and drain electrode;
Step is the 3. 4. 5. 6. 7. 8. organic semiconductor layer described in 9. 2.; Transition zone; Electrode layer and gate insulator are through vacuum evaporation; Ion cluster bundle deposition; Ion plating; Dc sputtering deposition; The radio frequency sputtering plated film; Ion beam sputtering deposition; Ion beam assisted depositing; Plasma reinforced chemical vapour deposition; High density inductance coupling high formula plasma source chemical vapor deposition; The catalyst chemical vapour deposition (CVD); Magnetron sputtering; Electroplate; Spin coating; Dip-coating; Inkjet printing; Roller coat; One or several modes in the LB film form.
8. the preparation method of a hole-transporting type OTFT is characterized in that, comprises the steps:
1. earlier substrate is cleaned completely, it is dry to clean the back;
2. prepare gate electrode at substrate surface;
3. handle at gate electrode above-prepared gate insulator and to insulating barrier;
4. on said gate insulator, prepare source electrode and drain electrode;
5. between source electrode and drain electrode, prepare first transition zone;
6. on source electrode, drain electrode, first transition zone, prepare first organic semiconductor layer;
7. on first organic semiconductor layer, prepare hole blocking layer;
8. on said hole blocking layer, prepare second transition zone;
9. on second transition zone, prepare second organic semiconductor layer;
Step is the 3. 4. 5. 6. 7. 8. organic semiconductor layer described in 9. 2.; Transition zone; Electrode layer and gate insulator are through vacuum evaporation; Ion cluster bundle deposition; Ion plating; Dc sputtering deposition; The radio frequency sputtering plated film; Ion beam sputtering deposition; Ion beam assisted depositing; Plasma reinforced chemical vapour deposition; High density inductance coupling high formula plasma source chemical vapor deposition; The catalyst chemical vapour deposition (CVD); Magnetron sputtering; Electroplate; Spin coating; Dip-coating; Inkjet printing; Roller coat; One or several modes in the LB film form.
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