CN102299111B - Method for manufacturing complementary metal oxide semiconductor device structure - Google Patents
Method for manufacturing complementary metal oxide semiconductor device structure Download PDFInfo
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- CN102299111B CN102299111B CN2010102180180A CN201010218018A CN102299111B CN 102299111 B CN102299111 B CN 102299111B CN 2010102180180 A CN2010102180180 A CN 2010102180180A CN 201010218018 A CN201010218018 A CN 201010218018A CN 102299111 B CN102299111 B CN 102299111B
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Abstract
The invention discloses a method for manufacturing a complementary metal oxide semiconductor (CMOS) device structure. The method comprises the following steps: providing a first front-end device structure comprising a substrate and a grid insulation layer, wherein the substrate is divided into a first region containing a P well and a second region containing an N well, and forming an N-type covering layer and a metal barrier layer in sequence on the upper surface of the grid insulation layer; then removing the metal barrier layer and the N-type covering layer corresponding to the second region; forming P-type covering layers above the first region and the second region; and removing a P-type covering layer corresponding to the first region by adopting a mask-shielding mode; obtaining a second front-end device structure, and further preparing the CMOS device structure provided with a first grid structure and a second grid structure on the second front-end device structure. The CMOS device structure prepared by the method disclosed by the invention preferably meets the actual technological requirements and the product yield can be improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of method of making the CMOS (Complementary Metal Oxide Semiconductor) device architecture.
Background technology
Along with the development of semiconductor fabrication, also more and more less as the live width of the grid of weighing the semiconductor fabrication technological level.At present, the live width of grid can accomplish that 65nm is even less.Little grid live width can reduce the driving voltage of the semiconductor device of formation, and then reduces power consumption.In addition, little grid live width also can make the dimensions of semiconductor devices formed reduce, and improves integrated level, increases the quantity of unit are semiconductor-on-insulator device, reduces costs.Grid structure how to prepare thus less live width becomes the current research focus.
Figure 1A to Fig. 1 J prepares CMOS (CMOS (Complementary Metal Oxide Semiconductor)) device architecture generalized section in prior art.As shown in Figure 1A, at first, provide the first front end device architecture, this first front end device architecture comprises substrate 100 and gate insulator 103.Wherein, substrate 100 comprises P trap 101 and N trap 102, and this P trap 101 and N trap 102 are by shallow trench isolation from (STI) structure separately.Gate insulator 103 is formed at the upper surface of described substrate 100 by chemical vapour deposition (CVD).Described substrate 100 is divided into first area 101A and second area 102A, and wherein the first area 101A shown in Figure 1A comprises the fleet plough groove isolation structure of described P trap 101 and part, and second area 102A comprises the fleet plough groove isolation structure of N trap 102 and another part.
Shown in Figure 1B, upper surface at above-mentioned gate insulator 103 forms one deck N-type cover layer, this N-type cover layer has correspondingly covered first area 101A and second area 102A, for convenience of describing, name is the first N-type cover layer 104A corresponding to the N-type cover layer of first area 101A top, corresponding to the N-type cover layer above second area 102A, is the second N-type cover layer 104B.Then, as shown in Figure 1 C, form the first mask 110 above the first N-type cover layer 104A, this first mask 110 is covered in the upper surface of the first N-type cover layer 104A, exposes the second N-type cover layer 104B.
Then, as shown in Fig. 1 D, utilize the first mask 110 to fall the second N-type cover layer 104B for mask etching.Then, as shown in Fig. 1 E, remove the first mask 110 corresponding to first area 101A.
Next, as shown in Fig. 1 F, at the deposition of the superstructure shown in above-mentioned Fig. 1 E one deck P type cover layer, the P type cover layer corresponding to first area 101A top is a P type cover layer 105A, corresponding to the P type cover layer above second area 102A, is the 2nd P type cover layer 105B.Then, as shown in Figure 1 G, form the second mask 111 above the 2nd P type cover layer 105B, this second mask 111 is covered in the upper surface of the 2nd P type cover layer 105B, exposes a P type cover layer 105A.Utilize the second mask 111 to fall a P type cover layer 105A for mask etching, then, remove the second mask 111 of the upper surface of the 2nd P type cover layer 105B.As shown in Fig. 1 H, obtain needed the second front end device architecture of cmos device structure.
With above-mentioned the first front end device architecture relatively, this second front end device architecture comprises the first front end device architecture, corresponding to the first N-type cover layer 104A of first area 101A top with corresponding to the 2nd P type cover layer 105B of second area 102A top.Then, as shown in Figure 1 I, depositing metal layers 106, polysilicon layer 107 and hard mask layer 108 successively above the second front end device architecture.By existing technique, gate insulator 103, the first N-type cover layer 104A, metal level 106, polysilicon layer 107 and hard mask layer 108 corresponding to first area 101A top are carried out to etching and form the needed first grid structure 112 of cmos device structure, and gate insulator 103, the 2nd P type cover layer 105B, metal level 106, polysilicon layer 107 and hard mask layer 108 corresponding to second area 102A top are carried out to the needed second grid structure 113 of etching formation cmos device structure, as shown in Fig. 1 J.Described first grid structure 112, second grid structure 113 and substrate 100 form described cmos device structure.
In the technique of above-mentioned preparation the second front end device architecture, how making above-mentioned the first N-type cover layer 104A and the 2nd P type cover layer 105B not be damaged becomes the key of preparation the second front end device architecture.In actual preparation process, the first N-type cover layer and the tectal deposit thickness of the 2nd P type only have several dusts (being less than ten dusts) usually, when obtaining above-mentioned cmos device structure, usually cause the thickness of the first N-type cover layer 104A and the 2nd P type cover layer 105B not meet technological requirement.Its reason is, when first deposit the N-type cover layer above substrate, during rear deposition P type cover layer, when a P type cover layer 105A who removes corresponding to first area, the tectal thickness of the first N-type (as shown in Fig. 1 G and Fig. 1 H) of meeting loss the one P type cover layer 105A below, and then the cmos device structure of the actual process demand that is not being met.Conversely, when first deposit P type cover layer above substrate, during rear deposition N-type cover layer, thickness that may loss the 2nd P type cover layer 105B, can't obtain satisfactory cmos device structure thus.Further, the leakage current of the cmos device structure of utilizing said method to be prepared into increases, and threshold voltage descends.
Therefore, how to avoid when preparing above-mentioned cmos device structure, needed the 2nd P type cover layer of needed the first N-type cover layer of the first grid structure of this cmos device structure and second grid structure is not worn to as the current technical issues that need to address.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order effectively to address the above problem, the present invention proposes a kind of method of making the CMOS (Complementary Metal Oxide Semiconductor) device architecture, comprise the following steps:
The first front end device architecture is provided, and this first front end device architecture comprises the gate insulator of substrate and this substrate top surface, and described substrate is divided into first area and second area, and described first area comprises the P trap, and described second area comprises the N trap;
Upper surface at described gate insulator forms the N-type cover layer;
Form metal barrier on this N-type cover layer, this metal barrier comprises corresponding to the first metal barrier of described first area with corresponding to the second metal barrier of described second area;
Adopt first masking film the first metal barrier, and remove described the second metal barrier and corresponding to the N-type cover layer of described second area;
Remove described the first mask;
Form P type cover layer above corresponding to described first area and described second area;
Adopt the P type cover layer of the second masking film corresponding to described second area, and remove the P type cover layer corresponding to described first area;
Remove described the second mask, obtain the second front end device architecture, and
Depositing metal layers above described the second front end device architecture successively, polysilicon layer and hard mask layer, and etching is corresponding to the hard mask layer of described first area, polysilicon layer, metal level, the first metal barrier, N-type cover layer and gate insulator, obtain the first grid structure, etching is corresponding to the hard mask layer of described second area, polysilicon layer, metal level, P type cover layer and gate insulator, obtain the second grid structure, described substrate, described first grid structure and described second grid structure form described CMOS (Complementary Metal Oxide Semiconductor) device architecture.
Further, the generation type of described N-type cover layer, described P type cover layer and described metal barrier is selected from a kind of in high density plasma CVD, aumospheric pressure cvd and low-pressure chemical vapor deposition.
Further, described N-type cover layer is hafnium, and described P type cover layer is for being different from the tectal hafnium of this N-type.
Further, the tectal material of described N-type is La
2o
3.
Further, the tectal material of described P type is A1
2o
3.
Further, the tectal thickness of described N-type is 5 dust to 10 dusts, and the tectal thickness of described P type is 5 dust to 10 dusts.
Further, described the second metal barrier of described removal and corresponding to the N-type cover layer of described second area for adopting wet etching to remove described the second metal barrier and corresponding to the N-type cover layer of described second area.
Further, the solution that described wet etching adopts is for being mixed the solution formed with water by HCL, and the weight ratio of described HCL and water is between 1: 18 to 1: 54, and the temperature of described solution is between 20 degrees centigrade to 50 degrees centigrade.
Further, described removal is removed the P type cover layer corresponding to described first area corresponding to the P type cover layer of described first area for the employing wet etching.
Further, the solution that described wet etching adopts is by H
2o
2and NH
4the solution that OH mixes, in described solution, NH
4oH and H
2o
2weight ratio between 1: 0.24 to 1: 2.4.
Further, the thickness of described metal barrier is 5 dust to 10 dusts.
Further, the material of described metal barrier and described metal level is identical.
Further, described removal comprises corresponding to the P type cover layer of described first area, removes corresponding to the P type cover layer of described first area and removes at least in part described the first metal barrier.
According to a further aspect in the invention, the present invention also proposes a kind of method of making the CMOS (Complementary Metal Oxide Semiconductor) device architecture, and described method comprises the following steps:
The first front end device architecture is provided, and this first front end device architecture comprises the gate insulator of substrate and this substrate top surface, and described substrate is divided into first area and second area, and described first area comprises the P trap, and described second area comprises the N trap;
Upper surface at described gate insulator forms P type cover layer;
Form metal barrier on this P type cover layer, this metal barrier comprises corresponding to the first metal barrier of described first area with corresponding to the second metal barrier of described second area;
Adopt described the second metal barrier of the first masking film, and remove described the first metal barrier and corresponding to the P type cover layer of described first area;
Remove described the first mask;
Form the N-type cover layer above corresponding to described first area and described second area;
Adopt the N-type cover layer of the second masking film corresponding to described first area, and remove the N-type cover layer corresponding to described second area;
Remove described the second mask, obtain the second front end device architecture, and
Depositing metal layers above described the second front end device architecture successively, polysilicon layer and hard mask layer, and etching is corresponding to the hard mask layer of described first area, polysilicon layer, metal level, N-type cover layer and gate insulator, obtain the first grid structure, etching is corresponding to the hard mask layer of described second area, polysilicon layer, metal level, the second metal barrier, P type cover layer and gate insulator, obtain the second grid structure, described substrate, described first grid structure and described second grid structure form described CMOS (Complementary Metal Oxide Semiconductor) device architecture.
According to the present invention; in the cmos device structure of preparation; first deposit N-type cover layer (comprising the first N-type cover layer and the second N-type cover layer) above substrate; rear deposition P type cover layer is when (comprising a P type cover layer and the 2nd P type cover layer); first deposit thinner metal barrier at the tectal upper surface of N-type, during for the P type cover layer above etching the first N-type cover layer, protect the first N-type cover layer below it not to be subject to loss.Conversely; first deposit P type cover layer (comprising a P type cover layer and the 2nd P type cover layer) above substrate; rear deposition N-type cover layer is when (comprising the first N-type cover layer and the second N-type cover layer); first deposit thinner metal barrier at the tectal upper surface of P type, during for the second N-type cover layer above etching the 2nd P type cover layer, protect the 2nd P type cover layer below it not to be subject to loss.Preferably, the metal barrier that in the present invention, selection material is identical and metal level, can further guarantee that the cmos device structure can not introduce other impurity, and then can improve the yields of the cmos device structure of preparation.
The accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A is the generalized section for preparing the cmos device structure in prior art to Fig. 1 J;
Fig. 2 A is to prepare the generalized section of cmos device structure according to embodiments of the invention to Fig. 2 K;
Fig. 3 is the process chart of the cmos device structure that according to an embodiment of the invention prepared by method.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, detailed step will be proposed in following description, so that how explanation the present invention improves the technique of making the cmos device structure to solve the problems of the prior art.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet, except these are described in detail, the present invention can also have other execution modes.
With reference to Fig. 2 A to Fig. 2 K, Fig. 2 A to Fig. 2 K illustrates the generalized section that method according to an embodiment of the invention prepares the cmos device structure.
Shown in Fig. 2 A, at first, the first front end device architecture (not marking in figure) is provided, this the first front end device architecture comprises substrate 200 and is positioned at the gate insulator 203 of substrate 200 upper surfaces, described substrate 200 comprises P trap 201 and N trap 202, and this P trap 201 and N trap 202 are by shallow trench isolation from (STI) structure separately.For convenience of describing, the substrate 200 in the present invention is divided into first area 201A and second area 202A, and the first area 201A shown in Fig. 2 A comprises the sti structure of P trap 201 and part, and second area 202A comprises the sti structure of N trap 202 and another part.Wherein, the material of gate insulator 203 can be HfO
2or the material of other insulating properties, this gate insulator 203 can form by chemical vapour deposition (CVD) formation or plasma gas phase deposition, and the thickness of this gate insulator 203 can be between 5 dust to 20 dusts.In the present embodiment, preferably with plasma gas phase deposition, prepare HfO
2layer, this HfO
2the thickness of layer can be 10 dusts.
Upper surface at the gate insulator 203 of the first front end device architecture forms the N-type cover layer, this N-type cover layer 204 has correspondingly covered first area 201A and second area 202A, wherein, name is the first N-type cover layer 204A corresponding to the N-type cover layer of first area 201A top, corresponding to the N-type cover layer above second area 202A, is the second N-type cover layer 204B.Wherein, the tectal material of this N-type can be hafnium (K is dielectric constant), or the metal oxide materials of other easy conductive, the tectal formation of this N-type can be implemented by aumospheric pressure cvd or low-pressure chemical vapor deposition, or implemented by plasma gas phase deposition, in addition, the tectal thickness range of this N-type is 5 dust to 10 dusts.N-type cover layer in the present embodiment is preferably used La
2o
3material, its mode by high density plasma CVD (HDP-CVD) is implemented, and thickness is 7 dusts.
Then, as shown in Fig. 2 B, on the tectal upper surface plated metal of described N-type barrier layer, this metal barrier can be implemented by chemical vapour deposition (CVD) or plasma gas phase deposition, wherein metal barrier is preferably used the aluminum or aluminum alloy material, and the thickness of this metal barrier is between 5 dust to 10 dusts.The material of metal barrier is preferably used aluminium in the present embodiment, and thickness is 6 dusts.The metal barrier that wherein is positioned at the first N-type cover layer 204A upper surface is the first metal barrier 206A, and the metal barrier that is positioned at the second N-type cover layer 204B upper surface is the second metal barrier 206B.
Secondly, as shown in Figure 2 C, form the first mask 210 above the first metal barrier 206A, the first mask 210 can be photoresist, this the first mask 210 is covered in the upper surface of the first metal barrier 206A, exposes the second N-type cover layer 204B of the second metal barrier 206B and its below.
As shown in Figure 2 D, utilize the first mask 210 to fall the second metal barrier 206B and the second N-type cover layer 204B below it for mask etching; Preferably adopt hydrochloric acid solution to remove the second N-type cover layer 204B of the second metal barrier 206B and its below, the temperature of hydrochloric acid solution can be between 20 degrees centigrade to 50 degrees centigrade further.Described hydrochloric acid solution is mixed with water by HCL gas and the solution that forms, the weight ratio of described HCL gas and water is between 1: 18 to 1: 54, hydrochloric acid solution in the present embodiment can be mixed with water by the concentrated hydrochloric acid of 36wt% and the solution, the concentrated hydrochloric acid of described 36wt% and the hydrochloric acid of the weight ratio of water between 1: 1000 to 1: 3000 that form.Then, as shown in Figure 2 E, remove the first mask 210 of the first metal barrier 206A upper surface, in the present embodiment, adopt ashing method to remove described the first mask 210.
Next, as shown in Figure 2 F, at the superstructure shown in Fig. 2 E, form one deck P type cover layer, at the first metal barrier 206A upper surface with corresponding to the upper surface of the gate insulator 203 of second area, form P type cover layer; The tectal material of this P type can be the hafnium different from N-type cover layer 204, or the metal material of other easy conductive or metal oxide materials.The tectal formation of described P type can be implemented by aumospheric pressure cvd or low-pressure chemical vapor deposition, or is implemented by plasma gas phase deposition (HDP-CVD), and its deposit thickness is 5 dust to 10 dusts.Preferably use in the present embodiment the mode of HDP-CVD to deposit P type cover layer, its material is preferably AL
2o
3, thickness is 5 dusts.Name is a P type cover layer 205A corresponding to the P type cover layer of first area 201A top, corresponding to the P type cover layer above second area 202A, is the 2nd P type cover layer 205B.It should be noted that, in the present invention, the deposit thickness of N-type cover layer 204 and P type cover layer 205 is to be determined by the target component of depositing device, in the process of deposition, difference is little, this difference does not affect the overall performance of the semiconductor device structure that the present invention finally obtains, and does not consider in the present invention thus.
Then, as shown in Figure 2 G, forming the second mask 211, the second masks 211 above the 2nd P type cover layer 205B can be photoresist, and this second mask 211 has covered the upper surface of the 2nd P type cover layer 205B, exposes a P type cover layer 205A.
As shown in Fig. 2 H, utilize the second mask 211 to fall a P type cover layer 205A for mask etching, then, adopt ashing method to remove described the second mask 211, obtain the second front end device architecture of the cmos device structure as shown in Fig. 2 I, this the second front end device architecture comprises the first front end device architecture, corresponding to the first N-type cover layer 204A and the first metal barrier 206A of first area 201A top, and corresponding to the 2nd P type cover layer 205B of second area 202A top.Certainly, according to actual process equipment, can remove the P type cover layer 205A corresponding to described first area fully, remove at least in part the first metal barrier 206A simultaneously.Perhaps can remove a P type cover layer 205A and the first metal barrier 206A (scheming not shown) corresponding to described first area fully.In the present invention, thinner thickness due to the above-mentioned metal barrier deposited above the N-type cover layer, and can partly be removed or all be removed in etching process, and then affect little on the first grid structure of follow-up preparation and the difference in height of second grid structure, in addition, can the performance of finally prepd semiconductor device structure not exerted an influence yet.
Preferably, the solution of removing a P type cover layer 205A in the present embodiment is preferably used H
2o
2and NH
4the solution that OH (Ammonia) mixes, in described solution, NH
4oH and H
2o
2weight ratio between 1: 0.24 to 1: 2.4.In actual process, can also use by H
2o
2nH with 29wt%
4the solution that the OH aqueous solution forms, in described solution, 29wt%NH
4the OH aqueous solution and H
2o
2weight ratio between 1: 10 to 1: 100.
And then, as shown in Fig. 2 J, depositing metal layers 206 ' above the second front end device architecture, and form polysilicon layer 207 and hard mask layer 208 on the upper surface of this metal level 206 ', preferably, material, the thickness of material, thickness and the first metal barrier 206A, the second metal barrier 206B of this place's metal level 206 ' can be identical, and its thickness and material can be changed according to actual process requirements.
Finally, as shown in Fig. 2 K, successively hard mask layer 208, polysilicon layer 207, metal level 206 ', the first metal barrier 206A, the first N-type cover layer 204A and gate insulator 203 corresponding to first area 201A top are carried out to etching, obtain the needed first grid structure 212 of cmos device structure; And hard mask layer 208, polysilicon layer 207, metal level 206 ', the 2nd P type cover layer 205B and the gate insulator 203 corresponding to second area 202A top carried out to etching, obtain the needed second grid structure 213 of cmos device structure.Described first grid structure 212, second grid structure 213 and substrate form the cmos device structure.In addition, above-mentioned polysilicon layer 207 can also adopt amorphous silicon to replace, and preferred amorphous silicon can be a-Si.
Preferably, in the present invention, the order for preparing above-mentioned the second front end device architecture can also be, at first the upper surface at the gate insulator of the first front end device architecture forms P type cover layer (comprising a P type cover layer and the 2nd P type cover layer) and metal barrier (comprising the first metal barrier and the second metal barrier), adopt described the second metal barrier of the first masking film, secondly, remove a P type cover layer of described the first metal barrier and its below, then remove the first mask, and above-mentioned integrally-built above the top of described first area and described second area (corresponding to) form N-type cover layer (comprising the first N-type cover layer and the second N-type cover layer), then adopt second masking film the first N-type cover layer, and remove the second N-type cover layer.Last depositing metal layers successively, polysilicon layer and hard mask layer are above described the second front end device architecture, and etching is corresponding to the hard mask layer of described first area, polysilicon layer, metal level, the first N-type cover layer and gate insulator, obtain the first grid structure, etching is corresponding to the hard mask layer of described second area, polysilicon layer, metal level, the second metal barrier, the 2nd P type cover layer and gate insulator, obtain the second grid structure, described substrate, described first grid structure and described second grid structure form described CMOS (Complementary Metal Oxide Semiconductor) device architecture.
It should be noted that, at the material of above-mentioned metal barrier (the first metal barrier 206A, the second metal barrier 206B) and metal level 206 ', can also be chosen as tungsten, titanium or other suitable metals or its alloy.
The needed N-type cover layer of the first grid structure of cmos device structure and the needed P type of second grid structure cover layer often are depleted in the prior art, and then cause the cmos device structure of finally obtaining not meet actual process requirements.
In the present invention, first deposit the N-type cover layer above substrate, during rear deposition P type cover layer, above the needed N-type cover layer of the first grid structure of cmos device structure in advance the plated metal barrier layer as etching barrier layer.Perhaps above substrate, first deposit P type cover layer, during rear deposition N-type cover layer, above the needed P type of the second grid structure cover layer of cmos device structure, the plated metal barrier layer is as etching barrier layer in advance, and above-mentioned two kinds of depositional modes are mainly to prevent that the P type cover layer that N-type cover layer (the first N-type cover layer 204A as shown in Figure 2 G) that the first grid structure below this metal barrier needs or second grid structure need is depleted.Preferably, the first metal barrier in the present embodiment, the second metal barrier and metal level adopt identical material, can not introduce other impurity like this.The cmos device structure that includes first grid structure 212 and second grid structure 213 prepared by the present embodiment is less, and the live width of this cmos device structure is little, and correspondingly the leakage current of this grid structure reduces.That is to say, the electrical parameter of this cmos device structure (as saturation current, grid voltage etc.) is better than the electrical parameter of cmos device structure prepared by prior art.As can be seen here, adopt method of the present invention can play the electric property that improves the cmos device structure.
Fig. 3 is the process chart of semiconductor device structure prepared according to the methods of the invention, and it comprises:
Step 301: the first front end device architecture is provided, this the first front end device architecture comprises the gate insulator of substrate and this substrate top surface, for convenience of describing, in the present invention described substrate is divided into to first area and second area, described first area comprises the P trap, and described second area comprises the N trap;
Step 302: at the upper surface of described gate insulator, form N-type cover layer (the N-type cover layer corresponding to first area is the first N-type cover layer, is the second N-type cover layer corresponding to the N-type cover layer of second area);
Step 303: form metal barrier at the tectal upper surface of this N-type, this metal barrier comprises corresponding to the first metal barrier of described first area with corresponding to the second metal barrier of described second area;
Step 304: adopt first masking film the first metal barrier, and remove the second metal barrier and, corresponding to the N-type cover layer (removing the second metal barrier and the second N-type cover layer) of described second area, then remove the first mask;
Step 305: above corresponding to described first area and second area, form P type cover layer;
Step 306: (the P type cover layer corresponding to first area is a P type cover layer corresponding to the P type cover layer of second area to adopt the second masking film, P type cover layer corresponding to second area is the 2nd P type cover layer), and remove corresponding to the P type cover layer (removing a P type cover layer) above described first area, then remove the second mask, obtain the second front end device architecture, and
Step 307: depositing metal layers above described the second front end device architecture successively, polysilicon layer and hard mask layer, and etching is corresponding to the hard mask layer of described first area, polysilicon layer, metal level, the first metal barrier, N-type cover layer and gate insulator, obtain the first grid structure of cmos device structure, etching is corresponding to the hard mask layer of described second area, polysilicon layer, metal level, P type cover layer and gate insulator, obtain the second grid structure of cmos device structure, described substrate, first grid structure and second grid structure form described CMOS (Complementary Metal Oxide Semiconductor) device architecture (cmos device structure).
According to the cmos device structure of embodiment manufacture as above, can be applicable in multiple integrated circuit (IC).According to IC of the present invention, be for example memory circuitry, as random access memory (RAM), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) etc.According to IC of the present invention, can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio-frequency devices or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
It is pointed out that each structure in cutaway view only shows with schematic form, does not represent the proportionate relationship between each structure.A certain zone described in the invention or certain one deck structure " on ", " top ", " upper surface ", mean corresponding to directly over this zone or this one deck structure, and do not comprise the part of top of other zone or layer structure.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the purpose for giving an example and illustrating just, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (17)
1. a method of making the CMOS (Complementary Metal Oxide Semiconductor) device architecture, is characterized in that, described method comprises the following steps:
The first front end device architecture is provided, and this first front end device architecture comprises the gate insulator of substrate and this substrate top surface, and described substrate is divided into first area and second area, and described first area comprises the P trap, and described second area comprises the N trap;
Upper surface at described gate insulator forms the N-type cover layer;
Form metal barrier on this N-type cover layer, this metal barrier comprises corresponding to the first metal barrier of described first area with corresponding to the second metal barrier of described second area;
Adopt described the first metal barrier of the first masking film, and remove described the second metal barrier and corresponding to the N-type cover layer of described second area;
Remove described the first mask;
Form P type cover layer above corresponding to described first area and described second area;
Adopt the P type cover layer of the second masking film corresponding to described second area, and remove the P type cover layer corresponding to described first area;
Remove described the second mask, obtain the second front end device architecture, and
Depositing metal layers above described the second front end device architecture successively, polysilicon layer and hard mask layer, and etching is corresponding to the hard mask layer of described first area, polysilicon layer, metal level, the first metal barrier, N-type cover layer and gate insulator, obtain the first grid structure, etching is corresponding to the hard mask layer of described second area, polysilicon layer, metal level, P type cover layer and gate insulator, obtain the second grid structure, described substrate, described first grid structure and described second grid structure form described CMOS (Complementary Metal Oxide Semiconductor) device architecture.
2. the method for claim 1, it is characterized in that, the generation type of described N-type cover layer, described P type cover layer and described metal barrier is selected from a kind of in high density plasma CVD, aumospheric pressure cvd or low-pressure chemical vapor deposition.
3. the method for claim 1, is characterized in that, described N-type cover layer is hafnium, and described P type cover layer is for being different from the tectal hafnium of this N-type.
4. the method for claim 1, is characterized in that, the tectal material of described N-type is La
2o
3.
5. the method for claim 1, is characterized in that, the tectal material of described P type is Al
2o
3.
6. as arbitrary described method in claim 1 to 5, it is characterized in that, the tectal thickness of described N-type is 5 dust to 10 dusts, and the tectal thickness of described P type is 5 dust to 10 dusts.
7. the method for claim 1, it is characterized in that, described the second metal barrier of described removal and corresponding to the N-type cover layer of described second area for adopting wet etching to remove described the second metal barrier and corresponding to the N-type cover layer of described second area.
8. method as claimed in claim 7, is characterized in that, the solution that described wet etching adopts is for being mixed the solution formed with water by HCL, and the weight ratio of described HCL and water is between 1:18 to 1:54.
9. method as claimed in claim 8, is characterized in that, the temperature of described solution is between 20 degrees centigrade to 50 degrees centigrade.
10. the method for claim 1, is characterized in that, described removal is removed the P type cover layer corresponding to described first area corresponding to the P type cover layer of described first area for the employing wet etching.
11. method as claimed in claim 10, is characterized in that, the solution that described wet etching adopts is by H
2o
2and NH
4the solution that OH mixes, in described solution, NH
4oH and H
2o
2weight ratio between 1:0.24 to 1:2.4.
12. the method for claim 1, is characterized in that, the thickness of described metal barrier is 5 dust to 10 dusts.
13. the method for claim 1, is characterized in that, the material of described metal barrier and described metal level is identical.
14. the method for claim 1, is characterized in that, described removal comprises corresponding to the P type cover layer of described first area, removes corresponding to the P type cover layer of described first area and removes at least in part described the first metal barrier.
15. an integrated circuit that comprises the CMOS (Complementary Metal Oxide Semiconductor) device architecture of manufacturing by the method for claim 1, wherein said integrated circuit is selected from dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC) and radio circuit.
16. an electronic equipment that comprises the CMOS (Complementary Metal Oxide Semiconductor) device architecture of manufacturing by the method for claim 1, wherein said electronic equipment is selected from portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
17. a method of making the CMOS (Complementary Metal Oxide Semiconductor) device architecture is characterized in that described method comprises the following steps:
The first front end device architecture is provided, and this first front end device architecture comprises the gate insulator of substrate and this substrate top surface, and described substrate is divided into first area and second area, and described first area comprises the P trap, and described second area comprises the N trap;
Upper surface at described gate insulator forms P type cover layer;
Form metal barrier on this P type cover layer, this metal barrier comprises corresponding to the first metal barrier of described first area with corresponding to the second metal barrier of described second area;
Adopt described the second metal barrier of the first masking film, and remove described the first metal barrier and corresponding to the P type cover layer of described first area;
Remove described the first mask;
Form the N-type cover layer above corresponding to described first area and described second area;
Adopt the N-type cover layer of the second masking film corresponding to described first area, and remove the N-type cover layer corresponding to described second area;
Remove described the second mask, obtain the second front end device architecture, and
Depositing metal layers above described the second front end device architecture successively, polysilicon layer and hard mask layer, and etching is corresponding to the hard mask layer of described first area, polysilicon layer, metal level, N-type cover layer and gate insulator, obtain the first grid structure, etching is corresponding to the hard mask layer of described second area, polysilicon layer, metal level, the second metal barrier, P type cover layer and gate insulator, obtain the second grid structure, described substrate, described first grid structure and described second grid structure form described CMOS (Complementary Metal Oxide Semiconductor) device architecture.
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