CN105390496B - A kind of semiconductor devices and preparation method thereof and electronic device - Google Patents
A kind of semiconductor devices and preparation method thereof and electronic device Download PDFInfo
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- CN105390496B CN105390496B CN201410451995.3A CN201410451995A CN105390496B CN 105390496 B CN105390496 B CN 105390496B CN 201410451995 A CN201410451995 A CN 201410451995A CN 105390496 B CN105390496 B CN 105390496B
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Abstract
A kind of semiconductor devices of present invention offer and preparation method thereof and electronic device, including：Semiconductor substrate and the epitaxial layer on the substrate are provided, wherein the epitaxial layer is divided into deep trench area and active area, deep trench is formed in the deep trench area, and be filled with N-type polycrystalline silicon layer in the deep trench；The first shallow trench and the second shallow trench are formed in the epitaxial layer, wherein first shallow trench is located at the top of the N-type polycrystalline silicon floor in the deep trench area, second shallow trench is located in the active area；Laser thermal anneal is carried out, to form thermally grown silicon oxide layer in the bottom of first shallow trench and the second shallow trench；Oxide liner layer is formed in the bottom and side wall of first shallow trench and the second shallow trench；Spacer material layer is formed in first shallow trench and the second shallow trench.The method of the present invention, when effectivelying prevent liner deposition, dispersal events cause phosphorus to pollute same batch of wafer to the phosphorus in N-type polycrystalline silicon layer outward.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and preparation method thereof and electronics
Device.
Background technology
In technical field of semiconductors, imaging sensor is a kind of semiconductor device that optical imagery can be converted into electric signal
Part.Imaging sensor can generally be divided into charge coupled cell (CCD) and complementary metal oxide semiconductor (CMOS) image
Sensor.The advantages of ccd image sensor is higher to image sensitivity, and noise is small, but ccd image sensor and other devices
Integrating for part is relatively difficult, and the power consumption of ccd image sensor is higher.In contrast, cmos image sensor has technique
Simply, easily with other devices are integrated, small, light-weight, small power consumption, it is at low cost the advantages that.Cmos image sensor quilt at present
It is widely used in digital camera, camera cell phone, DV, medical photographic device (such as gastroscope), automobile-used photographic device
Among equal fields.
In the manufacturing process of cmos image sensor, in order to ensure the production capacity of production line, padded in shallow trench oxide
When layer deposition, often the inhomogeneous wafer for being scheduled for same process produce with batch.It is as shown in Figure 1A
Schematic diagram when cmos image sensor wafer carries out shallow trench oxide liner deposition was depositing as seen from the figure
Cheng Zhong is located at the foreign matter of phosphor in the n-type doping polysilicon of the filling deep trench below shallow trench to external diffusion, and it is this spread it is past
Toward the problem of other wafers below cmos image sensor wafer cause phosphorus to pollute can be located to same batch, for example, Figure 1B institutes
Show that wafer, phosphorus (P) diffuse into silicon substrate, and then RS_NW and RS_DNW is caused to generate fluctuation, eventually leads to its performance and yield
Decline.
Therefore, in order to solve the above-mentioned technical problem, it is necessary to propose a kind of production method of new semiconductor devices.
Invention content
A series of concept of reduced forms is introduced in Summary, this will in the detailed description section into
One step is described in detail.The Summary of the present invention is not meant to attempt to limit technical solution claimed
Key feature and essential features do not mean that the protection domain for attempting to determine technical solution claimed more.
In order to overcome the problems, such as that presently, there are the embodiment of the present invention one provides a kind of production method of semiconductor devices, packet
It includes：
Semiconductor substrate and the epitaxial layer on the substrate are provided, wherein the epitaxial layer be divided into deep trench area and
Active area is formed with deep trench in the deep trench area, and is filled with N-type polycrystalline silicon layer in the deep trench；
The first shallow trench and the second shallow trench are formed in the epitaxial layer, wherein first shallow trench is located at the depth
The top of the N-type polycrystalline silicon layer in trench area, second shallow trench are located in the active area；
Laser thermal anneal is carried out, to form thermally grown oxide silicon in the bottom of first shallow trench and the second shallow trench
Layer；
Oxide liner layer is formed in the bottom and side wall of first shallow trench and the second shallow trench；
Spacer material layer is formed in first shallow trench and the second shallow trench.
Further, it forms first shallow trench and the step of second shallow trench includes：
Pad oxide skin(coating), pad nitride layer and pad oxynitride layer are sequentially formed on said epitaxial layer there；
The pad oxynitride layer, pad nitride layer, the pad oxide skin(coating) and epitaxial layer are patterned, to form described the
One shallow trench and the second shallow trench.
Further, the semiconductor substrate is N-type semiconductor substrate, and the epitaxial layer is N-type epitaxy layer.
Further, the wave-length coverage of the laser is 200~350nm.
Further, the energy density of the laser ranging from 1~2J/cm2。
Further, under air or oxygen atmosphere, the laser thermal anneal is carried out.
Further, the thickness of thermally grown silicon oxide layer is 30~70 angstroms.
Further, include the step of formation spacer material layer in first shallow trench and the second shallow trench：
Isolated material is filled in first shallow trench and the second shallow trench and is overflowed；
Planarisation step is executed, the top of the pad nitride layer is stopped at, to form spacer material layer；
Remove the pad nitride layer and pad oxide skin(coating).
Further, the top surface of the spacer material layer of formation is higher than the top surface of the epitaxial layer.
Further, the pad oxide skin(coating) is silicon oxide layer, and the pad nitride layer is silicon nitride layer, the pad nitrogen oxidation
Nitride layer is silicon oxynitride layer.
Further, the N-type polycrystalline silicon layer is phosphorus doped polysilicon layer.
Second embodiment of the present invention provides a kind of semiconductor devices that the method using described in embodiment one makes.
The embodiment of the present invention three provides a kind of electronic device, including the semiconductor devices described in embodiment two.
In conclusion according to the method for the embodiment of the present invention, it is formed in the oxide liner layer of fleet plough groove isolation structure
Before, laser thermal anneal is first carried out, thermally grown oxide silicon is formed in the top of the bottom of shallow trench, that is, N-type polycrystalline silicon layer, it can be effective
It prevents when carrying out oxide liner layer deposition, to same batch, other wafers cause dispersal events the phosphorus in N-type polycrystalline silicon layer outward
Phosphorus pollutes, and the bilayer oxide laying being formed simultaneously may also function as the effect for reducing fleet plough groove isolation structure electric leakage, Jin Erti
The high performance and yield of device.
Description of the drawings
The following drawings of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, principle used to explain the present invention.
In attached drawing：
Figure 1A is schematic diagram when existing cmos image sensor wafer carries out shallow trench oxide liner deposition；
Figure 1B is the schematic diagram of the wafer polluted by phosphorus；
Fig. 2A -2E show for the section of the obtained device of corresponding steps according to existing cmos image sensor production method
It is intended to；
The section for the cmos image sensor that Fig. 3 A-3E are obtained by the corresponding steps of the method for the embodiment of the present invention one shows
It is intended to；
Fig. 4 is according to the process flow chart of the method for the embodiment of the present invention one successively implementation steps.
Specific implementation mode
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be understood that the present invention can be implemented in different forms, and should not be construed as being limited to propose here
Embodiment.Disclosure will be made thoroughly and complete on the contrary, providing these embodiments, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in the areas Ceng He may be exaggerated.From beginning to end
Same reference numerals indicate identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
There may be elements or layer between two parties by person.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or " being directly coupled to " other elements or when layer, then element or layer between two parties is not present.It should be understood that although can make
Various component, assembly units, area, floor and/or part are described with term first, second, third, etc., these component, assembly units, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish a component, assembly unit, area, floor or part with it is another
One component, assembly unit, area, floor or part.Therefore, do not depart from present invention teach that under, first element discussed below, portion
Part, area, floor or part are represented by second element, component, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and being used describe an elements or features shown in figure with
The relationship of other elements or features.It should be understood that other than orientation shown in figure, spatial relationship term intention further includes making
With the different orientation with the device in operation.For example, if the device in attached drawing is overturn, then, it is described as " under other elements
Face " or " under it " or " under it " elements or features will be oriented in other elements or features "upper".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when being used in this specification, determines the feature, whole
The presence of number, step, operations, elements, and/or components, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of component, assembly unit and/or group.Herein in use, term "and/or" includes any of related Listed Items and institute
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Illustrate technical solution proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, however in addition to these detailed descriptions
Outside, the present invention can also have other embodiment.
Referring to Fig. 2A -2E to a kind of existing production method of the fleet plough groove isolation structure of cmos image sensor into
Row description.
With reference to figure 2A, N-type semiconductor substrate 200 and the N-type epitaxy layer 201 on the substrate are provided, wherein institute
N-type epitaxy layer 201 is stated to divide for deep trench area DT and active area AA.
In deep trench area, DT is formed with deep trench 202, n-type doping polysilicon is filled in deep trench 202, wherein the N
Type impurity is phosphorus.
Pad silicon oxide layer 203, pad silicon nitride layer 204 and pad silicon oxynitride layer are sequentially formed in the N-type epitaxy layer 201
205。
Pattern the pad silicon oxynitride layer 205, pad silicon nitride layer 204, pad silicon oxide layer 203 and the N-type epitaxy layer
201, to form shallow trench 206.Shallow trench 206 in wherein deep trench area DT is located at the top of the deep trench 202.
With reference to figure 2B, oxidation is formed on the bottom and side wall of the pad silicon oxynitride layer 205 and the shallow trench 206
Object laying 207.
In deposition process, the impurity in the n-type doping polysilicon of the filling deep trench 202 of 206 lower section of shallow trench
Phosphorus (region in such as Fig. 2 B in oval marks) is to external diffusion, and this diffusion often causes phosphorus dirty the other wafers of same batch
The problem of dye.
With reference to figure 2C, in the shallow trench 206 and the pad silicon oxynitride layer 205 fills HDP oxide skin(coating)s 208.
With reference to figure 2D, chemical mechanical grinding is carried out to HDP oxide skin(coating)s 208, is stopped on pad silicon nitride layer 204.
With reference to figure 2E, removal pad silicon nitride layer 204 and pad silicon oxide layer 203 ultimately form fleet plough groove isolation structure.
In view of the problem of phosphorus being caused to pollute other wafers existing in the prior art, the present invention proposes a kind of new
Production method.
Embodiment one
In the following, being described in detail to the production method of cmos image sensor of the present invention with reference to Fig. 3 A-3E and Fig. 4.
First, step 401 is executed, semiconductor substrate and the epitaxial layer on the substrate are provided, wherein described outer
Prolong floor and be divided into deep trench area and active area, deep trench is formed in the deep trench area, and be filled with N in the deep trench
Type polysilicon layer.
With reference to figure 3A, semiconductor substrate 300 and the epitaxial layer 301 on the substrate are provided.In one example,
The semiconductor substrate is N-type semiconductor substrate, and the epitaxial layer is N-type epitaxy layer.
Low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical may be used in the growing method of the epitaxial layer
Vapor deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecule
One kind in beam epitaxy (MBE).When epitaxial layer is N-type epitaxy layer, also need to carry out n-type doping ion implanting to epitaxial layer with shape
At N-type epitaxy layer.
Wherein, the epitaxial layer 301 divides for deep trench area DT and active area AA.
It is formed with deep trench in deep trench area DT, N-type polycrystalline silicon layer 302 is filled in deep trench.In one example,
The N-type polycrystalline silicon layer 302 is phosphorus doped polysilicon layer.
Step 402 is executed, the first shallow trench and the second shallow trench are formed in the epitaxial layer, wherein first shallow ridges
Slot is located at the top of the N-type polycrystalline silicon floor in the deep trench area, and second shallow trench is located in the active area.
With reference to figure 3A, pad oxide skin(coating) 303, pad nitride layer 304 and pad nitrogen oxygen are sequentially formed on the epitaxial layer 301
Compound layer 305.
The pad oxide skin(coating) 303 can be the silicon oxide layer formed by thermal oxidation method, and general thickness is 100~160 angstroms,
Mainly as separation layer to protect active area when removing silicon nitride not by chemical spot (i.e. as isolating oxide layer).
Pad nitride layer 304 is formed on pad oxide skin(coating) 303, the preferred silicon nitride layer of material of nitride layer can be adopted
Pad nitride layer 304 is formed with boiler tube deposition method or Low Pressure Chemical Vapor Deposition, thickness is generally 600~1200
Angstrom, which is mainly used for protecting active area during the deposition oxide in fleet plough groove isolation structure, and is changing
It can be used as the barrier material of grinding when learning the silica that mechanical lapping is filled.
Pad oxynitride layer 305 is formed on pad nitride layer 304, the material of oxynitride layer 305 is preferably nitrogen oxidation
Silicon layer.
The pad oxynitride layer 305, pad nitride layer 304, pad oxide skin(coating) 303 and the epitaxial layer 301 are patterned,
To form the first shallow trench 306a and the second shallow trench 306b.The first shallow trench 306a in wherein deep trench area DT is located at described
The top of N-type polycrystalline silicon layer 302, the second shallow trench 306b are located in the active area AA.
Step 403 is executed, laser thermal anneal is carried out, to form heat in the bottom of first shallow trench and the second shallow trench
Growing silicon oxide layer.
With reference to figure 3B, laser thermal anneal is carried out, in the bottom of the first shallow trench 306a and the second shallow trench 306b
Form thermally grown silicon oxide layer 307.Optionally, the wave-length coverage of the laser is 200~350nm.Further, the laser
Energy density ranging from 1~2J/cm2.In one example, under air or oxygen atmosphere, the laser thermal anneal is carried out.Profit
The bottom that the first shallow trench 306a and the second shallow trench 306b are heated with laser makes its surface melting, absorbs and comes from ambient enviroment
In oxygen, form thermally grown silicon oxide layer 307 by melting recrystallization.Illustratively, the thickness of the thermally grown silicon oxide layer
Degree is 30~70 angstroms.But it is not limited to this thickness range, can be adjusted according to actual needs.
During carrying out laser thermal anneal, it is located at the pad oxynitride layer 305 of top surface and the first shallow trench 306a
It is both exposed to the side wall of the second shallow trench 306b in the air or oxygen atmosphere of heat, therefore also further, positioned at top surface
The pad nitride layer that the surface of pad oxynitride layer 305 and the side wall of the first shallow trench 306a and the second shallow trench 306b expose
The very thin SiON layers 308 of one layer of the formation on 304 surface, thickness are less than 20 angstroms.Meanwhile the first shallow trench 306a and second shallow
The surface of pad oxide skin(coating) 303 and epitaxial layer 301 that the side wall of groove 306b exposes forms thermally grown silicon oxide layer.
Laser thermal anneal process may be implemented quickly to aoxidize, for example, its oxidization time is less than 1 μ s.Due to being that part adds
Heat, and the time is short, therefore not will produce what the phosphorus in N-type polycrystalline silicon layer 302 discharged outward in laser thermal anneal processing procedure
Problem.
Step 404 is executed, oxide liner layer is formed in the bottom and side wall of first shallow trench and the second shallow trench.
As shown in Figure 3 C, oxide liners are formed in the bottom and side wall of the first shallow trench 306a and the second shallow trench 306b
Layer 309.
The oxide liner layer 309 is silicon oxide layer.Chemical vapor deposition, the formation of the methods of atomic layer deposition can be used
The oxide liner layer.Due in 403 steps before, in the bottom of the first shallow trench 306a and the second shallow trench 306b,
Thermally grown silicon oxide layer 307 especially is formd in the top of N-type polycrystalline silicon layer 302, can be effectively prevent in oxide liners
In 309 deposition process of layer, phosphorus in N-type polycrystalline silicon layer 302 dispersal events outward.Therefore same process will not be carried out to same batch
Other wafers cause phosphorus pollution problem, can be improved the yield and performance of device, and production production capacity.
Thermally grown silicon oxide layer 307 and the oxide liner layer 309 being positioned above form double-layer structure simultaneously, can be common
As the laying of the first shallow trench 306a and the second shallow trench 306b, it can play and reduce fleet plough groove isolation structure leakage
The effect of electricity.
Step 405 is executed, spacer material layer is formed in first shallow trench and the second shallow trench.
Specifically, isolated material is filled in first shallow trench and the second shallow trench and is overflowed, and isolated material is usual
It is described that there is high-k for the combination of oxide (such as HARP, HDP), the material with high-k or the two
The dielectric constant of material be usually 3.9 or more.Preferably, the isolated material is HDP oxides.Using HDP oxides
The problems such as first shallow trench and the second shallow trench can be filled well, and not will produce filling cavity.
Preferably, being further comprised after filling isolated material in first shallow trench and the second shallow trench flat
The step of smoothization, can realize the planarization on surface using flattening method conventional in field of semiconductor manufacture.This is flat
The non-limiting examples of change method include mechanical planarization method and chemically mechanical polishing flattening method.Chemically mechanical polishing is flat
Smoothization method is more often used.
As shown in Figure 3D, planarisation step is executed, the top of pad nitride layer 304 is stopped at, to form spacer material layer
310。
With reference to figure 3E, the pad nitride layer 304 and pad oxide skin(coating) 303 are removed.In one example, it is gone using wet method
Except technique removes the pad nitride layer 304 and pad oxide skin(coating) 303, it is important to note that using wet method removal technique
When removing the pad nitride layer 304, the spacer material layer 310 of filling can't be removed, to fill spacer material layer 310
Top surface be apparently higher than pad oxide skin(coating) 303；When subsequently using wet method removal technique removal pad oxide skin(coating) 303, portion can be removed
Divide spacer material layer 310, but since the spacer material layer 310 has relatively high step, in removal pad oxide skin(coating) 303
Afterwards, spacer material layer 310 still can fill the first shallow trench 306a and the second shallow trench 306b, and spacer material layer
310 top surface can be higher than the top surface of the epitaxial layer 301.
So far the making of the fleet plough groove isolation structure of cmos image sensor is completed, method through the invention, shallow
Before the oxide liner layer of groove isolation construction is formed, laser thermal anneal is first carried out, in bottom, that is, N-type polycrystalline silicon of shallow trench
The top of layer forms thermally grown oxide silicon, can effectively prevent when carrying out oxide liner layer deposition, the phosphorus in N-type polycrystalline silicon layer
For dispersal events to causing phosphorus to pollute with batch other wafers, it is shallow that the bilayer oxide laying being formed simultaneously may also function as reduction outward
The effect of groove isolation construction electric leakage, and then improve the performance and yield of device.
Embodiment two
The embodiment of the present invention also provides a kind of semiconductor devices made of method in embodiment one, and structure is as follows：
Semiconductor substrate and the epitaxial layer on the substrate, wherein the epitaxial layer is divided into deep trench area and active
Area is formed with deep trench in the deep trench area, and is filled with N-type polycrystalline silicon layer in the deep trench.In an example
In, the semiconductor substrate is N-type semiconductor substrate, and the epitaxial layer is N-type epitaxy layer.Optionally, the N-type polycrystalline silicon layer
For phosphorus doped polysilicon layer.
The first isolation structure for being formed in the epitaxial layer above the N-type polycrystalline silicon layer and have positioned at described
The second isolation structure in source region.
Wherein, first isolation structure and second isolation structure include the thermally grown silicon oxide layer positioned at bottom,
And the oxygen above the thermally grown silicon oxide layer and on first isolation structure and the second isolation structure side wall
Compound laying, and the spacer material layer above the oxide liner layer.
In one example, the top surface of first isolation structure and second isolation structure is higher than the epitaxial layer
Top surface.
Optionally, the thickness of the thermally grown silicon oxide layer is 30~70 angstroms.Institute is formed using the method for laser thermal anneal
State thermally grown silicon oxide layer.
In conclusion semiconductor devices according to the ... of the embodiment of the present invention, isolation structure includes thermally grown oxide silicon and oxygen
The bilayer oxide laying of compound laying, bilayer oxide laying can play the work for reducing fleet plough groove isolation structure electric leakage
With, and then improve the performance and yield of device.
Embodiment three
The present invention also provides a kind of electronic devices comprising semiconductor devices in embodiment two or including using embodiment
The semiconductor devices that method makes in one.
Due to including semiconductor devices have higher performance and yield, which equally has the advantages that above-mentioned.
The electronic device, can be mobile phone, tablet computer, laptop, net book, game machine, television set, VCD,
Any electronic product such as DVD, navigator, camera, video camera, recording pen, MP3, MP4, PSP or equipment, can also be to have
The intermediate products of above-mentioned semiconductor device, such as：Cell phone mainboard etc. with the integrated circuit.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
The purpose of citing and explanation, and be not intended to limit the invention within the scope of described embodiment.In addition people in the art
It is understood that the invention is not limited in above-described embodiment, introduction according to the present invention can also be made more kinds of member
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (13)
1. a kind of production method of semiconductor devices, including：
Semiconductor substrate and the epitaxial layer on the substrate are provided, wherein the epitaxial layer is divided into deep trench area and active
Area is formed with deep trench in the deep trench area, and is filled with N-type polycrystalline silicon layer in the deep trench；
The first shallow trench and the second shallow trench are formed in the epitaxial layer, wherein first shallow trench is located at the deep trench
The top of the N-type polycrystalline silicon floor in area, second shallow trench are located in the active area；
Laser thermal anneal is carried out, to form thermally grown silicon oxide layer in the bottom of first shallow trench and the second shallow trench；
Oxide liner layer is formed in the bottom and side wall of first shallow trench and second shallow trench；
Spacer material layer is formed in first shallow trench and second shallow trench.
2. according to the method described in claim 1, it is characterized in that, forming first shallow trench and second shallow trench
Step includes：
Pad oxide skin(coating), pad nitride layer and pad oxynitride layer are sequentially formed on said epitaxial layer there；
The pad oxynitride layer, pad nitride layer, pad oxide skin(coating) and the epitaxial layer are patterned, it is shallow to form described first
Groove and the second shallow trench.
3. described outer according to the method described in claim 1, it is characterized in that, the semiconductor substrate is N-type semiconductor substrate
It is N-type epitaxy layer to prolong layer.
4. according to the method described in claim 1, it is characterized in that, the wave-length coverage of the laser is 200~350nm.
5. according to the method described in claim 1, it is characterized in that, the energy density of the laser ranging from 1~2J/cm2。
6. according to the method described in claim 1, it is characterized in that, under air or oxygen atmosphere, carries out the laser heat and move back
Fire.
7. according to the method described in claim 1, it is characterized in that, the thickness of thermally grown silicon oxide layer is 30~70 angstroms.
8. according to the method described in claim 2, it is characterized in that, in first shallow trench and the second shallow trench formed every
Include from the step of material layer：
Isolated material is filled in first shallow trench and the second shallow trench and is overflowed；
Planarisation step is executed, the top of the pad nitride layer is stopped at, to form spacer material layer；
Remove the pad nitride layer and pad oxide skin(coating).
9. according to the method described in claim 8, it is characterized in that, the top surface of the spacer material layer formed is outer higher than described
Prolong the top surface of layer.
10. according to the method described in claim 2, it is characterized in that, the pad oxide skin(coating) is silicon oxide layer, the pad nitrogenizes
Nitride layer is silicon nitride layer, and the pad oxynitride layer is silicon oxynitride layer.
11. according to the method described in claim 1, it is characterized in that, the N-type polycrystalline silicon layer is phosphorus doped polysilicon layer.
12. the semiconductor devices that a kind of method using described in any one of claim 1-11 makes.
13. a kind of electronic device, which is characterized in that including the semiconductor devices described in claim 12.
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| US7759731B2 (en) * | 2006-08-28 | 2010-07-20 | Advanced Analogic Technologies, Inc. | Lateral trench MOSFET with direct trench polysilicon contact and method of forming the same |
| CN101436565A (en) * | 2007-11-13 | 2009-05-20 | 上海华虹Nec电子有限公司 | Method for preparing shallow plow groove isolation |
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