CN102291950A - System and method for aligning a plurality of layers of device - Google Patents
System and method for aligning a plurality of layers of device Download PDFInfo
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- CN102291950A CN102291950A CN2011101099824A CN201110109982A CN102291950A CN 102291950 A CN102291950 A CN 102291950A CN 2011101099824 A CN2011101099824 A CN 2011101099824A CN 201110109982 A CN201110109982 A CN 201110109982A CN 102291950 A CN102291950 A CN 102291950A
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Abstract
The invention relates to a system and a method for aligning a plurality of layers of a device, and provides a system and a method for aligning a plurality of layers of a PCB (Printed Circuit Board), the method comprises: calculating a deformation factor of each key zone in a key zone group of each layer in a layer set of the PCB, the calculation is based on deviation between an interesting point in the key zone and an expected position of the interesting point; calculating a rotation angle of each key zone in the key zone group for each layer in the layer set of the PCB; calculating expected positions of a plurality of holes for each layer based on the deformation factor and the rotation angle of the key zone in the key zone group of each layer; punching at the expected positions to provided punched holes; aligning the plurality of layers of the PCB via the punched holes; and connecting the plurality of layers of the PCB to provide the PCB.
Description
Related application
The application requires in the priority of the U.S. Provisional Patent Application sequence number 61/354,730 of submission on June 15th, 2010, and its full content is incorporated into this.
Technical field
The present invention relates to be used to aim at a plurality of layers system and method for device.
Background technology
Printed circuit board (PCB) (PCB) comprises several layers, and they are made then independently of one another is laminated on together.Lamination process comprises by element being inserted in the hole that gets out in each layer aims at different layers.
In order to obtain the good connection between all layers, these layers and all key areas (for example pad, intensive circuit and trace (trace)) should accurately be positioned at top each other.
Nowadays, the most general solution is a spot of target hole of definition on the edge of dull and stereotyped (panel), and every layer is fixed on the alignment pin.The hole is produced by perforating press.
Each layer is provided to perforating press, and the position of the drift of perforating press is also regulated in camera recognition objective center, thus the target of passing and holing.
In the ideal case, target is aligned with each other, but actual flat board is out of shape in manufacture process.Different dull and stereotyped distortion may be different, and therefore the target that calculates based on desirable non-distortion manufacture process may cause misalignment.
Distortion can be reflected by so-called stretching factor.Thereby different layers have different stretching factors, and from a zone of flat board to another zone of same flat board, stretching factor may change.
Summary of the invention
A kind of method of a plurality of layers that is used to aim at printed circuit board (PCB) (PCB), according to one embodiment of present invention, this method can comprise: be the distortion factor of each key area in the key area group of this layer of each layer calculating in the layer set of PCB, this calculates the deviation based on the desired locations of the point-of-interest of this key area and this point-of-interest; Calculate the anglec of rotation of each key area in the key area group for each layer in the layer set of PCB; Based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, calculate the desired locations in a plurality of holes of this layer for each layer; In described desired locations punching so that the hole of going out to be provided; Use the described hole of going out to aim at a plurality of layers of PCB; And a plurality of layer of PCB is connected to each other so that PCB to be provided.
This method can comprise: the deviation to the point-of-interest of key area is used non-linear weight function, so that the distortion factor to be provided.
This method can comprise: ignore the deviation that is lower than allowable deviation.
This method can comprise: the desired locations that calculates the hole breaks down to prevent PCB.
This method can comprise: the desired locations that calculates the hole surpasses the key area acceptable threshold of allowing with the right misalignment of key area of the adjacent layer that prevents to expect to aim at.
This method can comprise: with a zone definitions is key area, and this definition reduces based on the expected PCB performance that causes owing to the misalignment between another key area of this key area aimed in expectation and adjacent layer.
This method can comprise: the desired locations that calculates the hole reduces to minimize the expected performance that causes owing to the misalignment of each layer of PCB.
This method can comprise: the image based on each layer of PCB calculates the distortion factor and the anglec of rotation.
This method can comprise: receive the image of each dull and stereotyped layer, each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s; And based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, select will be combined with a plurality of set of the layer printed circuit board of formation different printing different layers circuit board, that belong to described flat board.
This method can comprise: based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, for calculating the desired locations in a plurality of holes of this layer with combined with each layer in each the layer printed circuit board set that forms PCB.
This method can comprise: obtain the image of each dull and stereotyped layer, each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s; And based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, select will be combined with a plurality of set of the layer printed circuit board of formation different printing different layers circuit board, that belong to described flat board.
A kind of system that is used to aim at printed circuit board (PCB) (PCB), according to one embodiment of present invention, this system can comprise: processor, be used to the distortion factor of each key area in the key area group of this layer of each layer calculating in the layer set of PCB, this calculates the deviation based on the desired locations of the point-of-interest of this key area and this point-of-interest; Wherein, described processor is used to the anglec of rotation of each key area in each layer calculating key area group in the layer set of PCB; Wherein, described processor is used for the distortion factor and the anglec of rotation based on the key area of the key area group of each layer, calculates the desired locations in a plurality of holes of this layer for each layer; And perforating press, be used in described desired locations punching so that the hole of going out to be provided; The wherein said hole of going out is used to aim at a plurality of layers of PCB.
This system can comprise linkage unit, is used to utilize the described hole of going out to aim at described a plurality of layers of PCB, and described a plurality of layers of PCB are connected to each other so that PCB to be provided.
Described processor can be used for the deviation of the point-of-interest of described key area is used non-linear weight function, so that the distortion factor to be provided.
Described processor can be used to ignore the deviation that is lower than allowable deviation.
The desired locations that described processor can be used to calculate the hole breaks down to prevent PCB.
The desired locations that described processor can be used to calculate the hole surpasses the key area acceptable threshold of allowing with the right misalignment of key area of the adjacent layer that prevents to expect to aim at.
It is key area that described processor can be used for a zone definitions, and this definition reduces based on the expected PCB performance that causes owing to the misalignment between another key area of this key area aimed in expectation and adjacent layer.
Described processor can be used to calculate the desired locations in hole to minimize expected because the performance that the misalignment of each layer of PCB causes reduces.
Described processor can be used for calculating the distortion factor and the anglec of rotation based on the image of each layer of PCB.
Described processor can be used for: receive the image of each dull and stereotyped layer, each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s; And based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, select will be combined with a plurality of set of the layer printed circuit board of formation different printing different layers circuit board, that belong to described flat board.
Described processor can be used for the distortion factor and the anglec of rotation based on the key area of the key area group of each layer, for calculating the desired locations in a plurality of holes of this layer with combined with each layer in each the layer printed circuit board set that forms PCB.
This system can comprise automatic visual inspection (AOI) system, is used to obtain the image of each dull and stereotyped layer, and each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s.Described processor (it can be included among the AOI or be not included among the AOI) can be used for the distortion factor and the anglec of rotation based on the key area of the key area group of each layer, select will be combined with a plurality of set of the layer printed circuit board of formation different printing different layers circuit board, that belong to described flat board.
Description of drawings
At this, only, the present invention is described with reference to the drawings by the mode of example.Specifically with reference to the accompanying drawings the time, the details shown in should be emphasized that is exemplary, is used to illustrate the discussion to various embodiment of the present invention.In the accompanying drawings:
Fig. 1 shows method according to an embodiment of the invention;
Fig. 2 shows system according to an embodiment of the invention;
Fig. 3 shows according to one embodiment of present invention, a plurality of layers the physical alignment of PCB; And
Fig. 4 and Fig. 5 show method according to an embodiment of the invention.
Embodiment
Because implementing equipment major part of the present invention is formed by electronic device well known by persons skilled in the art and circuit, so, will the details of circuit not carried out unnecessary too much explanation in order to understand basic principle of the present invention and not make the fuzzy or transfer of instruction of the present invention.
In the specific descriptions below, a large amount of details are described to provide thorough of the present invention.Yet, it should be appreciated by those skilled in the art there are not these details, also can realize the present invention.In other cases, known method, process and parts do not specifically describe, thereby do not make the present invention fuzzy.
The method and system of being advised can provide better aligning between layer in lamination process, can improve the output of lamination process and PCB manufacture process, and can help to make on flat board more intensive conductor, this is because the aligning between the layer is more accurate.Conductor can be any conducting element.
Fig. 1 shows method 100 according to an embodiment of the invention.
After stage 110 is the stage 120, for every layer or be that each key area at least of this layer calculates and is out of shape factor (stretching factor), and in addition or as a replacement zoning (or key area) with respect to the anglec of rotation of plate edge.The anglec of rotation can reflect the longitudinal axis that this is regional and be parallel to angle between the coordinate system at edge of PCB.
After stage 120 is the stage 130, is the optimum punching coordinate of every layer of calculating perforating press based on the stretching factor and the anglec of rotation.
According to one embodiment of present invention, optimum punching is defined as making the output of maximization PCB.Especially, find compromise between the deviation of key area of adjacent layer to surpass and allow threshold value to guard against deviations.In case allow threshold value can be defined as being exceeded, just break down.Replacedly, though allow threshold value by just over, do not break down yet.
The distortion factor can be the linear weight of compose giving the deviation of the point-of-interest of key area and desired locations.This deviation can represent deviation along X-axis, along deviation or its combination of Y-axis.Replacedly, the distortion factor can be given non-linear weight to deviation.
According to one embodiment of present invention, this method comprises the image that obtains or receive each dull and stereotyped layer.Each dull and stereotyped layer comprises a plurality of layers of PCB.Therefore, Ping Ban certain one deck can comprise certain one deck of a plurality of PCB.In this embodiment, can be the stage 125 after the stage 120, select which PCB layer will form PCB.Therefore, the stage 125 can comprise that selection can be by (group) in groups to form the PCB layer set of PCB.This selects the stretching factor and the anglec of rotation in response to key area.Stage 125 is shown as frame of broken lines, its by a dotted line arrow be connected to stage 120 and 130.In case these PCB layer set are selected, just at each PCB layer set duplication stages 130,150 and 160 that should form a PCB.
Should be noted that then these deviations can be allowed to if some deviations are in the scope that does not influence the PCB function basically.If for example the width of conductor is 2 microns, then can be allowed to less than 1 micron deviation, and offer the weight of such deviation can be less relatively.
For example, pad diameter is 20 millimeters, and expects that the drill bit of 10 mm dias passes this pad.In this case, certain deviation (for example about 3 millimeters) can be tolerated.
After stage 130 is the stage 150, punching in every layer.
After stage 150 is the stage 160, utilizes the hole of going out to aim at each layer, and different layers is connected to each other.This aligning can be finished automatically or be finished by the operator of perforating press.
Fig. 2 shows system 200 according to an embodiment of the invention.
Processor 230 can be included in in AOI system 210 and the perforating press 220 any one.
AOI system 210 obtains every layer the image of PCB.AOI system 210 can define key area or receive the definition of key area from other people or machine.The key area of PCB layer can comprise conductor or other structural details that need aim at conductor or other structural details of adjacent PCB layer.Criticality can be because the function of the infringement that the performance that the misalignment between the layer causes reduces.
Processor 230 can calculate the stretching factor and/or the anglec of rotation in each key area and layer rotation, and determines punching position based on the stretching factor and/or the anglec of rotation.
Perforating press 220 receives the punching instruction (it points out optimum punching position) of from processor 230, correspondingly adjusts drift.It is based on punching instruction punching in every layer.
Fig. 3 shows according to one embodiment of present invention, the exploded view of four layer 11-14 of the PCB that the use alignment pin is aimed at.
Fig. 3 shows the alignment pin 31 that is inserted into by the hole, and these holes are drilled to the target of passing such as target 22.By after the method selecting hole of Fig. 2, hole.Different flat boards can relative to each other rotate a little or move, and allows aligning with the key area that maximum quantity is provided.
For example, the perforating press operator can be placed on flat board on the punching board, and based on the punching target location flat board is fixed.In next stage, perforating press receives additional information from processor---apart from the side-play amount of punching.Based on this additional information, perforating press is finely tuned (displacement and rotation) to flat position, and moves dull and stereotyped to obtain optimum punching position.Displacement and rotation will be limited according to conductor and pad size, so that any misalignment all will be in permissible range.For 4 millimeters conductors and 20 millimeters pad diameter technology, this displacement may all be limited to 2 millimeters on directions X and Y direction, and rotation is limited to about 1 degree.Note, also can use other numerical value.
Fig. 4 shows according to one embodiment of present invention, is used to aim at a plurality of layers the method 400 of printed circuit board (PCB) (PCB).
Can at least one stage in stage 420 and 430 after stage 410.
After stage 420 and 430 is the stage 440, based on the distortion factor and the anglec of rotation of the key area in the key area group of layer, is every layer of desired locations that calculates a plurality of holes of this layer.
For example: suppose in each PCB, to have the individual key area of n (for example n=4), and the individual PCB of k (for example k=20) is arranged on every layer, thereby these a plurality of layers can form nearly 20 PCB.Desired locations can be confirmed as making and move in the permission between given one deck and another layer under the situation of (for example maximum rotation, maximum x axle or y axle move), will have the hole of maximum quantity to be in the aligning of allowing.
After stage 440 is the stage 450, in the desired locations punching so that the hole of going out to be provided.
After stage 450 is the stage 460, utilizes the hole of going out to make a plurality of layers of aligning of PCB.
After stage 460 is the stage 470, and a plurality of layers of PCB are connected to each other so that PCB to be provided.
Fig. 5 shows according to one embodiment of present invention, is used to aim at a plurality of layers the method 900 of printed circuit board (PCB) (PCB).
Key area can be the pad in the close quarters, can be to compare the special area with more very thin circuit with other zone, can be zone crucial for PCB, boring etc. functional.
Stage 910 can comprise the image that obtains or receive each dull and stereotyped layer.Each dull and stereotyped layer comprises a plurality of layers of PCB.Thereby certain dull and stereotyped one deck can comprise certain one deck of a plurality of printed circuit board (PCB)s (PCB).Therefore, can be equal to a plurality of layers of imaging for a plurality of flat panel imagings for a plurality of PCB.
Can at least one stage in stage 920 and 930 after stage 910.
Stage 920 comprises: based on the deviation of the desired locations of the point-of-interest of key area and this point-of-interest, be the distortion factor that each layer in the layer set of PCB calculates each key area in the key area group of this layer.Therefore, each layer can comprise a plurality of key areas.The key area group can comprise all these key areas or only comprise in these key areas some.The deviation of key area and its desired locations can be by assessing this key area point-of-interest and the deviation of its desired locations measure.Point-of-interest can be positioned at the edge of key area, but must be not so.It can be the arbitrfary point of key area, especially the point that can be discerned easily.
Stage 930 is included as the anglec of rotation of each key area in each layer calculating key area group in the layer set of a plurality of PCB.This anglec of rotation can be key area with can with the angle between the coordinate set that the edge of this layer is aimed at.
After stage 920 and 930 is the stage 940, the stretching factor and the anglec of rotation in response to key area, selection can be gathered with the PCB layer that forms PCB in groups, and, be every layer of desired locations that calculates a plurality of holes of this layer based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer.
A non-limiting example of selection course is provided below.In brief, selection can comprise that selection is not the set that is positioned at the layer at dull and stereotyped same position place.This selection can comprise select the to have similar deviation plate part of (for example, being positioned at the deviation on the equidirectional).
Every layer that supposes flat board comprises 7 parts, and each part can form one deck of PCB, and four layers of L1, L2-3, L4 are arranged.Flat layer L1 and L4 are outside flat layers, and flat layer L2-3 can be an interior layer.Following table shows the selection to part, and each part set (from 4 different flat layers) can be assembled so that single PCB to be provided.The numbering of the part of each digitized representation among row L1, L2-3 and the L4.Thereby first's set comprises the 3rd part of layer L1, the part 1 of the 6th part of layer L2-3 and layer L4.
| L1 | L2-3 | L4 | |
| First's set is to provide a PCB | 3 | 6 | 1 |
| The second portion set is to provide the 2nd PCB | 6 | 3 | 7 |
| The third part set is to provide the 3rd PCB | 5 | 4 | 2 |
| The set of the 4th part is to provide the 4th PCB | 1 | 1 | 6 |
| The set of the 5th part is to provide the 5th PCB | 7 | 2 | 3 |
| The set of the 6th part is to provide the 6th PCB | 2 | 5 | 5 |
| The set of the 7th part is to provide the 7th PCB | 4 | 7 | 4 |
Table 1
Stage 940 can comprise at least one or its combination in the following operation: (i) deviation of the point-of-interest of key area is used non-linear weight function, so that the distortion factor to be provided; (ii) use non-linear weight function, this non-linear weight function when deviation is lower than first threshold and deviation be inversely proportional to, when deviation is between the first threshold and second threshold value, fix, and be directly proportional with deviation during greater than second threshold value in deviation; (iii) ignore the deviation that is lower than allowable deviation; (iv) calculate the desired locations in hole, break down to prevent PCB; (v) calculate the desired locations in hole, surpass the key area acceptable threshold of allowing with the right misalignment of key area of the adjacent layer that prevents to expect to aim at; And (vi) calculate the desired locations in hole, to minimize expected because the performance that the misalignment of the layer of PCB causes reduces.
After stage 940 is the stage 950, in the desired locations punching so that the hole of going out to be provided.
After stage 950 is the stage 960, utilizes the hole of going out to make a plurality of layers of aligning of each PCB layer set.
After stage 960 is the stage 970, and a plurality of layers that each PCB layer is gathered are connected to each other so that PCB to be provided.
In addition, those skilled in the art should understand that the boundary line between the function of aforesaid operations only is exemplary.The function of a plurality of operations can be combined into single operation, and/or the function of single operation can be dispersed in other operations.In addition, alternative embodiment can comprise a plurality of examples of specific operation, and the order of operation can be changed in various other embodiment.
Therefore, should be appreciated that structure described here only is exemplary, and in fact, can adopt many other structures that realize identical function.Concise and to the point but clear and definite, any arrangements of components quilt effective " association " of realizing identical function is to realize the function of expectation.Therefore, can be regarded each other as " association " function with any two parts of realizing specific function to realize expecting in this combination, and irrelevant with structure or intermediate member.Equally, any two so related parts also can be regarded each other as " being operably connected " or " operationally coupling " to realize function of expectation.
Yet other are revised, are out of shape and replace also is feasible.Therefore specification and accompanying drawing are regarded as exemplary, and are not used in restriction.
Term " comprises " not repelling except those elements listed in the claims or step and also has other elements or step.
In addition, term " " or " one " can be defined as one or more than one as used herein.Equally, use lead vocabulary should not be interpreted as hinting in the claims such as " at least one " and " one or more ", another claim element of introducing by indefinite article " " or " one " will comprise that any specific rights of the claim element of such introducing requires to be restricted to the present invention and only comprises such element, even comprise lead vocabulary " one or more " or " at least one " and during such as the indefinite article of " " or " " when identical claim.Use to definite article also is like this.Except as otherwise noted, the term such as " first " and " second " is used to distinguish arbitrarily between the element of these term descriptions.Therefore, these terms must not be intended to represent that these elements are preferential aspect time or other.Certain measures this situation that only is cited in mutually different claims does not represent that the combination of these measures can not be carried out utilization.
Although illustrated and described some feature of the present invention at this, for a person skilled in the art, many modifications, replacement, change and equivalent can appear.Therefore, should be appreciated that appended claim is intended to cover all these and drops on modification and change in the true spirit of the present invention.
Claims (23)
1. method of a plurality of layers that is used to aim at printed circuit board (PCB) (PCB), described method comprises:
Be the distortion factor of each key area in the key area group of this layer of each layer calculating in the layer set of PCB, this calculates the deviation based on the desired locations of the point-of-interest of this key area and this point-of-interest;
Calculate the anglec of rotation of each key area in the key area group for each layer in the layer set of PCB;
Based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, calculate the desired locations in a plurality of holes of this layer for each layer;
In described desired locations punching so that the hole of going out to be provided;
Use the described hole of going out to aim at a plurality of layers of PCB; And
A plurality of layers of PCB are connected to each other so that PCB to be provided.
2. method according to claim 1 comprises: the deviation to the point-of-interest of key area is used non-linear weight function, so that the distortion factor to be provided.
3. method according to claim 1 comprises: ignore the deviation that is lower than allowable deviation.
4. method according to claim 1 comprises: the desired locations that calculates the hole breaks down to prevent PCB.
5. method according to claim 1 comprises: the desired locations that calculates the hole surpasses the key area acceptable threshold of allowing with the right misalignment of key area of the adjacent layer that prevents to expect to aim at.
6. method according to claim 1 comprises: with a zone definitions is key area, and this definition reduces based on the expected PCB performance that causes owing to the misalignment between another key area of this key area aimed in expectation and adjacent layer.
7. method according to claim 1 comprises: the desired locations that calculates the hole reduces to minimize the expected performance that causes owing to the misalignment of each layer of PCB.
8. method according to claim 1 comprises: the image based on each layer of PCB calculates the distortion factor and the anglec of rotation.
9. method according to claim 1 comprises: receive the image of each dull and stereotyped layer, each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s; And, select the set of the layer printed circuit board of a plurality of different layers that belong to described flat board based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, with in conjunction with forming a plurality of different printed circuit board (PCB)s.
10. method according to claim 9, comprise: based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, for calculating the desired locations in a plurality of holes of this layer with each layer in each the layer printed circuit board set that forms PCB combined.
11. method according to claim 1 comprises: obtain the image of each dull and stereotyped layer, each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s; And, select the set of the layer printed circuit board of a plurality of different layers that belong to described flat board based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, with in conjunction with forming a plurality of different printed circuit board (PCB)s.
12. a system that is used to aim at printed circuit board (PCB) (PCB), described system comprises:
Processor is used to the distortion factor of each key area in the key area group of this layer of each layer calculating in the layer set of PCB, and this calculates the deviation based on the desired locations of the point-of-interest of this key area and this point-of-interest;
Wherein, described processor is used to the anglec of rotation of each key area in each layer calculating key area group in the layer set of PCB;
Wherein, described processor is used for the distortion factor and the anglec of rotation based on the key area of the key area group of each layer, calculates the desired locations in a plurality of holes of this layer for each layer; And
Perforating press is used in described desired locations punching so that the hole of going out to be provided; The wherein said hole of going out is used to aim at a plurality of layers of PCB.
13. system according to claim 12 comprises linkage unit, is used to utilize the described hole of going out to aim at described a plurality of layers of PCB, and described a plurality of layers of PCB are connected to each other so that PCB to be provided.
14. system according to claim 12, wherein said processor is used for the deviation of the point-of-interest of described key area is used non-linear weight function, so that the distortion factor to be provided.
15. system according to claim 12, wherein said processor is used to ignore the deviation that is lower than allowable deviation.
16. system according to claim 12, the desired locations that wherein said processor is used to calculate the hole breaks down to prevent PCB.
17. system according to claim 12, the desired locations that wherein said processor is used to calculate the hole surpasses the key area acceptable threshold of allowing with the right misalignment of key area of the adjacent layer that prevents to expect to aim at.
18. system according to claim 12, it is key area that wherein said processor is used for a zone definitions, and this definition reduces based on the expected PCB performance that causes owing to the misalignment between another key area of this key area aimed in expectation and adjacent layer.
19. system according to claim 12, wherein said processor is used to calculate the desired locations in hole to minimize expected because the performance that the misalignment of each layer of PCB causes reduces.
20. system according to claim 12, wherein said processor is used for calculating the distortion factor and the anglec of rotation based on the image of each layer of PCB.
21. system according to claim 12, wherein said processor also is used for: receive the image of each dull and stereotyped layer, each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s; And, select the set of the layer printed circuit board of a plurality of different layers that belong to described flat board based on the distortion factor and the anglec of rotation of the key area in the key area group of each layer, with in conjunction with forming a plurality of different printed circuit board (PCB)s.
22. system according to claim 21, wherein said processor also is used for the distortion factor and the anglec of rotation based on the key area of the key area group of each layer, for calculating the desired locations in a plurality of holes of this layer with combined with each layer in each the layer printed circuit board set that forms PCB.
23. system according to claim 12 comprises automatic visual inspection (AOI) system, is used to obtain the image of each dull and stereotyped layer, each dull and stereotyped layer comprises the array of the identical in the ideal case layer of a plurality of printed circuit board (PCB)s; And wherein said processor is used for the distortion factor and the anglec of rotation based on the key area of the key area group of each layer, selects the set of the layer printed circuit board of a plurality of different layers that belong to described flat board, with in conjunction with forming a plurality of different printed circuit board (PCB)s.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US35473010P | 2010-06-15 | 2010-06-15 | |
| US61/354,730 | 2010-06-15 |
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| Publication Number | Publication Date |
|---|---|
| CN102291950A true CN102291950A (en) | 2011-12-21 |
| CN102291950B CN102291950B (en) | 2015-11-18 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110109982.4A Active CN102291950B (en) | 2010-06-15 | 2011-04-29 | For the system and method for multiple layers of alignment feature |
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| CN (1) | CN102291950B (en) |
| IL (1) | IL210656A0 (en) |
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| US20030130826A1 (en) * | 2002-01-08 | 2003-07-10 | International Business Machines Corporation | Model for modifying drill data to predict hole locations in a panel structure |
| CN2587131Y (en) * | 2002-10-25 | 2003-11-19 | 楠梓电子股份有限公司 | Aligning degree and expansion-contraction degree measuring construction for multiple-layer printed circuit board |
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- 2011-01-13 IL IL210656A patent/IL210656A0/en unknown
- 2011-04-29 CN CN201110109982.4A patent/CN102291950B/en active Active
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| WO2002033492A1 (en) * | 1999-07-06 | 2002-04-25 | Creo Il. Ltd. | Nonlinear image distortion correction in printed circuit board manufacturing |
| US20030130826A1 (en) * | 2002-01-08 | 2003-07-10 | International Business Machines Corporation | Model for modifying drill data to predict hole locations in a panel structure |
| CN2587131Y (en) * | 2002-10-25 | 2003-11-19 | 楠梓电子股份有限公司 | Aligning degree and expansion-contraction degree measuring construction for multiple-layer printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102291950B (en) | 2015-11-18 |
| IL210656A0 (en) | 2011-03-31 |
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