CN102288941A - Intermediate frequency linear frequency modulation-pulse Doppler (LFM-PD) radar signal real-time processing system based on field programmable gate array (FPGA) and digital signal processor (DSP) and processing method - Google Patents

Abstract

The invention discloses an intermediate frequency linear frequency modulation-pulse Doppler (LFM-PD) radar signal real-time processing system based on field programmable gate array (FPGA) and digital signal processor (DSP) and a method for realizing the system. The system consists of an intermediate frequency sampling module, a digital down-conversion module, a pulse compression module, a coherent accumulation module, a motion compensation module and a constant false alarm detection module. A processed radar signal enters the intermediate frequency sampling module at first; the dispersed signal is sent into the digital down-conversion module for digital down-conversion processing; then the signal enters the pulse compression module for pulse compression processing; after the coherent accumulation module accumulates out a result, the signal enters the motion compensation module to calculate the motion compensation quantity; and finally, the coherent accumulation result enters the constant false alarm detection module to detect out an object. The intermediate frequency LFM-PD radar signal real-time processing system based on FPGA and DSP can meet real-time processing requirements, is short in development cycle and strong in flexibility, and is suitable to be applied to large-scale radar detection systems.

Description

A kind of intermediate frequency LFM-PD radar signal real time processing system and disposal route based on FPGA and DSP

Technical field

The present invention relates to a kind of intermediate frequency LFM-PD (linear frequency modulation-coherent) radar signal real time processing system and disposal route, belong to the radar detection technique field based on FPGA and DSP.

Background technology

Radar is the main tool of the detection of a target in the military and civilian field.When having relative motion between radar and the target, will there be the difference on the frequency that is proportional to relative radial rate between the frequency of echoed signal and the frequency that transmits, the embodiment of Here it is Doppler effect.The radar that utilizes Doppler effect to carry out the target information extraction and handle is called radar Doppler, if radar emission is pulse modulated radiofrequency signal, promptly is referred to as pulse Doppler radar, is called for short the PD radar.The PD radar is the pulsed radar of a kind of advanced person's of growing up on the moving-target indication radar basis full coherent system.And the PD radar that adopts linear frequency modulation (LFM) signal combines the advantage of pulse Doppler system and pulse compression system, because the characteristics of wide bandwidth product when signal is big, make that radar can be with the broad pulse transmitted waveform, under the situation that does not increase pulse repetition rate, increase the average power of radar, improve the operating distance of radar, when receiving, adopt matched filter to carry out pulse compression, obtain narrow pulse signal, with the range resolution that keeps narrow pulse system and the speed resoluting force of doppler system, be implemented in the strong clutter environment detection to moving-target.In modern PD-pulse compression radar system, the Data Update of target echo signal is very fast, and this just requires radar processor to finish processing to a frame echo data in the extremely short time, has the ability of real-time processing, otherwise just may lose.Therefore, intermediate frequency LFM-PD radar real-time processing technique becomes a standard technique of modern radar gradually.

Eighties of last century is since the eighties, and along with the rapid progress of infotech and semiconductor technology, very high speed integrated circuit (VHSIC) and VLSI (very large scale integrated circuit) (VLSI) technology have obtained increasing substantially.The single-chip microcomputer and the small-scale integrated circuit of low speed, low reliability more and more can not be satisfied the demand, and are replaced by programmable logic device (PLD) (as FPGA, CPLD) and DSP just gradually.Present Digital Down Convert and process of pulse-compression device have multiple implementation method, and main implementation method comprises that PC software is realized, DSP realizes and FPGA realizes.

Hanoverian, Germany university uses 6 HiPAR-DSP 16 and FPGA to realize a REAL TIME SAR IMAGES processor.This processor adopts 6 HiPAR-DSP 16 interconnected, and its processing speed is 28GOPS, can handle 4096 * 4096 8bit plural number FFT under the repetition of 1200Hz in real time, and system has handling property height, low in energy consumption, advantage that volume is little.Virginia Polytechnic Institute and State University (Virginia Polytechnic Institute and State University) adopts high speed FPGA, by controlling 8 high-speed ADCs, designed the hypervelocity sampled digital transceiver of speed up to 8G-samples/s, can realize the sampling of the hypervelocity of UWB pulse, for signal Processing follow-up in the UWB system and data handling system are laid a good foundation.

In the method that above-mentioned realization intermediate frequency LFM-PD radar is handled in real time, utilize PC software to realize Digital Down Convert and pulse compression exploitation simply, but speed can not reach the requirement of real-time processing usually, and is not suitable for being applied in the large-scale radar sensing system.

Summary of the invention

Technology of the present invention is dealt with problems: overcome the deficiencies in the prior art, a kind of intermediate frequency LFM-PD radar signal real time processing system and disposal route based on FPGA and DSP is provided, can satisfy the requirement of real-time processing, and the construction cycle is short, dirigibility is strong, is fit to be applied in the large-scale radar sensing system.

Technical solution of the present invention: a kind of intermediate frequency LFM-PD radar signal real time processing system based on FPGA and DSP comprises: FPGA and DSP.Wherein FPGA comprises if sampling module, Digital Down Converter Module, pulse compression module; DSP comprises coherent accumulation module, motion compensating module and CFAR detection (CFAR) module.The signal that enters FPGA if sampling module is the if radar signal, and the direct IF Sampling by the if sampling module has obtained digital medium-frequency signal; Digital medium-frequency signal enters Digital Down Converter Module, carries out Digital Down Convert, has obtained I, Q two paths of signals; I, Q two paths of signals enter the pulse compression module, and the pulse compression module produces matching factor to I, Q two paths of signals, carries out process of pulse-compression.Signal after the pulse compression enters DSP coherent accumulation module, and this module is FFT to signal, obtains accumulating the result; Signal after the coherent accumulation enters the CFAR detection module and detects, and judges whether to exist target.

The pulse compression module comprises matching factor generation module, FFT module, takes advantage of module and IFFT module again.The each several part annexation as shown in the figure.I, Q signal are introduced into the FFT module and do the FFT computing, the coefficient of generation simultaneously and I, Q signal coupling, coefficient after producing is done the FFT computing, after the result that twice FFT draws enters and takes advantage of module to carry out multiple multiplication again, enter the IFFT module and carry out the IFFT computing, the IFFT calculated result is the result after the pulse compression.

Motion compensating module has adopted movement compensating algorithm.Native system adopts the envelope delay backoff algorithm, the target velocity result that this algorithm goes out by the previous frame data computation calculates the required motion compensation quantity of making of next frame data, the sequential that the parameter adjustment gate signal that FPGA revises according to DSP generates, simultaneously by adding up to corrected parameter, determine in the frame pulse string, the clock periodicity that each pulse gate signal demand is adjusted is realized motion compensation by the gate signal of adjusting straight ripple, echo.

Described CFAR detection module is realized by DSP; this module is by sliding window module; detection threshold computing module and signal detection module are formed; signal after the coherent accumulation is introduced into sliding window module; filter out detecting unit through sliding window module; protected location and reference unit; described detection unit refers to the zone that will detect; the protection unit is the unit adjacent with the detecting unit left and right sides; reference unit is the unit of detecting unit the right and left; calculate required detection threshold via the detection threshold computing module then, judge in the detecting unit whether have target by signal detection module at last.

A kind of intermediate frequency LFM-PD radar signal real-time processing method based on FPGA and DSP, performing step is as follows:

(1) by the intermediate frequency LFM-PD radar signal discretize of if sampling module, intermediate frequency LFM-PD radar signal is carried out quadrature sampling of medium frequency signal with simulation;

(2) digital signal that obtains of sampling is carried out Digital Down Convert by Digital Down Converter Module, obtains I road signal and Q road signal;

(3) I road signal and Q road signal are by the pulse compression module among the FPGA, do the FFT computing earlier by the FFT module, the matching factor generation module generates the coefficient with Signal Matching, coefficient is done the FFT computing, the result of twice FFT computing enters and takes advantage of module to take advantage of again again, result after taking advantage of again enters the IFFT module and carries out the IFFT computing, finishes pulse compression;

(4) utilize the signal after the coherent accumulation module paired pulses compression of DSP to carry out the FFT computing, finish the coherent accumulation;

(5) utilize DSP that the result after the coherent accumulation is carried out motion compensation calculations, and the parameter that calculates is fed back to the controlling of sampling module of FPGA (13), finish motion compensation radar signal;

(6) utilize CFAR detection (CFAR) module among the DSP that the result after the coherent accumulation is carried out CFAR detection (CFAR).Signal after the coherent accumulation is introduced into sliding window module; filter out detecting unit, protected location and reference unit via sliding window module; calculate required detection threshold via the detection threshold computing module then, judge in the detecting unit whether have target by signal detection module at last.

The present invention's advantage compared with prior art is:

(1) the present invention is when doing process of pulse-compression, and essence is that the complex signal of base band is FFT, and frequency domain pulse pressure coefficient is taken advantage of and IFFT again.What the hardware implementation structure of fft algorithm adopted is pipeline organization, can calculate uninterruptedly.The maximum data percent of pass of the present invention is 210MSPS, and finishing a pulse pressure processing time is 0.25ms only, can satisfy the data processing of nearly all radar now.

(2) the present invention adopts the method for time domain motion compensation, realizes motion compensation by the gate signal of adjusting straight ripple, echo.The sequential that the parameter adjustment gate signal that FPGA revises according to DSP generates by to the adding up of corrected parameter, is determined in the frame pulse string clock periodicity that each pulse gate signal demand is adjusted simultaneously.This method realizes simple, and does not exist pulse signal to overflow the problem of gate signal scope.

(3) the present invention is based on the Digital Down Convert and the pulse compression theory of classics, data are being carried out direct IF Sampling, realizing digital I/Q, broad pulse LFM echo is being carried out compression pulse handle based on multiphase filtering, make it become burst pulse, thereby obtained high range resolution.

(4) adopt programmable device FPGA and DSP as the digital signal processing core device, have very strong dirigibility and adaptability, shortened the construction cycle greatly.

(5) the present invention adopts two-level cache, makes the data that collect realize sufficient buffer memory.Adopt the first order buffer memory of the FIFO of FPGA generation as raw data, SDRAM links to each other with DSP as the second level buffer memory of data, thereby makes the sequential better matching of data.

(6) as far as possible little for the hardware system volume that guarantees to design, therefore under the prerequisite of the hardware burden that does not increase system, utilize existing FPGA in the system, designed with FPGA internal resource Block RAM and realized that asynchronous FIFO memory is as Cache, the different hardware environment of read-write clock frequency before and after it satisfies, make and have very strong extendability by acquisition system flexible design, simple, convenient.

Description of drawings

Fig. 1 realizes the schematic diagram of multiphase filtering numeral I/Q for the present invention;

Fig. 2 is the ultimate principle figure of LFM pulse pressure of the present invention; Wherein, four parts are represented frequency delay character, the compression network pulse output of input pulse envelope, pulse carrier frequency frequency modulation characteristic, compression network respectively from top to bottom;

Fig. 3 is a structure composition frame chart of the present invention;

The realization of Digital Down Convert figure as a result among this present invention of Fig. 4; The original signal figure of radar is represented on the left side; The right expression radar original signal is through the figure as a result after the pulse compression;

Fig. 5 is decimation in frequency FFT and decimation in time IFFT figure.

Embodiment

The present invention adopts direct quadrature sampling of medium frequency signal and digital pulse compression mode, thereby realizes pulse compression fast.Schematic diagram as depicted in figs. 1 and 2.Digital Down Convert schematic diagram of the present invention as shown in Figure 1, in digital information processing system, usually need be with the intermediate-freuqncy signal that receives by quadrature sampling, become the digital baseband signal that I, Q two-way represent and handle.I/Q passage inconsistency for fear of conventional simulation territory quadrature sampling brings adopts direct IF Sampling in this processor.Extract again by direct IF Sampling, avoided of the influence of pre-amplifier dc shift, obtained higher image-frequency rejection ratio the back end signal processing accuracy.

In Fig. 1, the intermediate-freuqncy signal that receives by quadrature sampling, is become the digital baseband signal that I, Q two-way represent and handles.If input

Wherein a (t) is a signal envelope,

Be first phase, f ₀Be carrier frequency.

According to bandpass sample theory, for guarantee to real signal x (t) when sampling positive and negative frequency spectrum aliasing, sample frequency f do not take place _sWith f ₀And signal bandwidth B should satisfy relation:

f _s〉=2B reaches

M is any positive integer (2.1) in the formula

With f _sInput is sampled, obtains the sampled signal sequence:

$x\left(n\right)=a\left(n\right)\·\cos [2\mathrm{\π}\frac{f_0}{f_s}n+\mathrm{\φ}\left(n\right)]=a\left(n\right)\·\cos [2\mathrm{\π}\frac{(2m+1)}{4}n+\mathrm{\φ}\left(n\right)]$

$=a\left(n\right)\cos \mathrm{\φ}\left(n\right)\·\cos \left(\frac{2m+1}{2}\mathrm{\πn}\right)-a\left(n\right)\sin \mathrm{\φ}\left(n\right)\·\sin \left(\frac{2m+1}{2}\mathrm{\πn}\right)$

$=I\left(n\right)\cos \left(\frac{2m+1}{2}\mathrm{\πn}\right)-Q\left(n\right)\sin \left(\frac{2m+1}{2}\mathrm{\πn}\right)---\left(2.2\right)$

In the formula, I (n)=a (n) cos φ (n), Q (n)=a (n) sin φ (n) is respectively the in-phase component and the quadrature component of signal, and wherein a (n) is the sample sequence of envelope, and φ (n) is the phase place of sequence.Digital down converter method is in this processor: because

x(2n)＝I(2n)cos[(2m+1)πn]＝I(2n)·(-1) ⁿ (2.3)

x(2n+1)＝-Q(2n+1)sin[(2m+1)/2·π(2n+1)]＝Q(2n+1)·(-1) ⁿ (2.4)

The order: I ' (n)=x (2n) (1) ⁿ, Q ' (n)=x (2n+1) (1) ⁿ, can get:

$\left\{\begin{array}{c}{I}^{\′}\left(n\right)=I\left(2n\right)\\ Q^{\′}\left(n\right)=Q(2n+1)\end{array}\right.---\left(2.5\right)$

That is to say that I (n) and two sequences of Q (n) are respectively the 2 frequency divisions extraction sequences of in-phase component I (2n) and quadrature component Q (2n).According to extracting principle, as long as the digital spectral of I (n) and Q (n) (is f less than pi/2 _s〉=4B), its 2 times extract sequence I ' (n), Q ' (n) can represent former sequence undistortedly.Easy proof, I ' is (n), Q ' digital spectral (n) is:

$\left\{\begin{array}{c}{I}^{\′}\left(e^{\mathrm{j\ω}}\right)=\frac{1}{2}I\left(e^{j\frac{\mathrm{\ω}}{2}}\right)\\ Q^{\′}\left(e^{\mathrm{j\ω}}\right)=\frac{1}{2}Q\left(e^{j\frac{\mathrm{\ω}}{2}}\right)\·e^{j\frac{\mathrm{\ω}}{2}}\end{array}\right.---\left(2.6\right)$

Both digital spectral differ a delay factor as can be seen

Thereby this is owing to adopted odd even extraction phase difference of half sampled point caused on time domain.This temporal " misalignment " can adopt two time delay wave filters to be proofreaied and correct, and the frequency response of these two wave filters should be satisfied:

$\frac{H_Q\left(e^{\mathrm{j\ω}}\right)}{H_I\left(e^{\mathrm{j\ω}}\right)}=e^{-j\frac{\mathrm{\ω}}{2}}$ And | H _Q(e ^{J ω}) |=| H _I(e ^{J ω}) |=1 (2.7)

I ' is the sequence of the 2 frequency divisions extraction of I road sequence I (n) (n), and Q ' is the sequence that sequence Q ' 2 frequency divisions (n) in Q road extract (n), I ' (e ^{J ω}) be I ' digital spectral (n), Q ' (e ^{J ω}) be Q ' digital spectral (n), H _Q(e ^{J ω}) the wave filter amplitude response of expression Q road signal, H _I(e ^{J ω}) the wave filter amplitude response of expression I road signal.

The pulse compression schematic diagram carries out compression pulse to the broad pulse LFM echo that receives and handles as shown in Figure 2 among the present invention, makes it become burst pulse, and its essence is the process of matched filtering.First's input pulse envelope, second portion pulse carrier frequency frequency modulation characteristic represent that the signal of receiver input is the LFM signal of a broad pulse in Fig. 2, and suppose that its carrier frequency increases by constant speed in pulse, and it is by the pulse pressure wave filter.This pulse pressure wave filter has the time delay-frequency characteristic shown in the frequency delay character of third part compression network among Fig. 2, its time delay t _dReduce with frequency linearity, and speed is advanced the speed identical with the interior frequency of the arteries and veins of echo.So it is long by the time lag of wave filter to part after than high frequency to make that low frequency in the echo-pulse arrives first part, therefore each frequency component in the arteries and veins is compressed in together in time domain, the pulse signal that the formation amplitude increases, width reduces, its desirable envelope is shown in the 4th part compression network pulse output among Fig. 2.

Fire pulse width τ and system be (compressed) pulsewidth τ effectively ₀Ratio, be called pulse compression ratio, promptly

D=τ/τ ₀Or D=τ B wherein, B=1/ τ ₀(2.8)

D is exactly a pulse compression ratio, and B is the bandwidth of signal.

Be time wide-bandwidth product that ratio of compression equals signal, it is one of the key technical indexes of weighing the pulse pressure processing.

Be workbench with the high-performance fpga chip XC4VSX55 of the Virterx4 series of Xilinx company and the High Performance DSP ADSP-TS201 Tiger SHARC (TS201) of AD company during specific implementation of the present invention, the ADC chip that the discretize of intermediate-freuqncy signal adopts is the AD9430 chip of AD company, AD9430 is the digital-to-analog conversion device of a 12bit high sampling rate low-power consumption, in system of the present invention, be operated under the LVDS pattern, data pass rate is 210MSPS, two-way output.Fpga chip XC4VSX55 has the piece storage unit of 512 hardware multipliers and 11.5Mbits, and directly links to each other with AD9430 by the LVDS signal wire, and a pulse pressure processing time only is 0.25ms, can satisfy the data processing requirement of nearly all radar now.

Core processor of the present invention is selected the XC4VSX55FPGA of the Virtex4 series of Xilinx company product for use, this chip is one of representative of high-performance FPGA, be the FPGA of a 1,000,000 gate leves, the piece storage unit that has 512 hardware multipliers and 11.5Mbits is primarily aimed at high performance signal and handles application.

Among the present invention simultaneously the signal to two passages carry out identical processing, handle realization flow as shown in Figure 3, comprise FPGA13 and DSP 20, wherein FPGA 13 comprises if sampling module 3, Digital Down Converter Module 4, pulse compression module 12; If sampling module 3 is made up of A/D module 1 and A/D controlling of sampling module 2.DSP20 comprises coherent accumulation module 14, motion compensating module 15 and CFAR detection (CFAR) module 19; The if radar signal enters in the if sampling module 3 of FPGA13, and the direct IF Sampling of controlling A/D modules 1 by A/D controlling of sampling module 2 obtains digital medium-frequency signal; Digital medium-frequency signal enters Digital Down Converter Module 4, carries out Digital Down Convert, has obtained I, Q two paths of signals; I, Q two paths of signals enter pulse compression module 12 and carry out process of pulse-compression; Signal after the process of pulse-compression enters in the DSP coherent accumulation module 14 and carries out FFT, obtains coherent accumulation result; Signal after the coherent accumulation enters motion compensating module 15, calculates the motion compensation quantity that need make by movement compensating algorithm, and the controlling of sampling module 2 that the parameter that draws is fed back to FPGA13 is adjusted the gate signal sequential; Signal after the last coherent accumulation enters CFAR detection (CFAR) module 19 and detects, and judges whether to exist target.

Among the present invention, intermediate frequency LFM-PD radar signal at first enters the if sampling module of being made up of A/D module 1 and A/D controlling of sampling module 23, and the ADC chip that uses in the if sampling module is AD9430, and this chip has two sampling channels, can two-way output.The if radar signal is through the digital signal of if sampling module 3 sampling back output two-way.A/D controlling of sampling module 2 in the if sampling module 3 is realized according to the feedback parameter of motion compensating module 15 computings of DSP20 by FPGA 13, the sampling time sequence of A/D controlling of sampling module 2 control A/D modules 1, and then realization is to the controlling of sampling of LFM-PD radar signal.Finish digital signal after the sampling and send into Digital Down Converter Module 4 and finish Digital Down Convert, generated the I/Q two paths of signals after the Digital Down Convert.Enter pulse compression module 12 after the I/Q two paths of signals generates and do process of pulse-compression.Pulse compression module 12 comprises matching factor generation module 5, FFT module 6, takes advantage of module 10 and IFFT module 11 again.After the I/Q two paths of signals enters pulse compression module 12, the matching factor generation module 5 of pulse compression module 12 produces the coefficient that matches according to the I/Q two paths of signals that enters, 6 pairs of I/Q two paths of signals of FFT module are done the FFT computing simultaneously, and calculated result is stored among the RAM.The coefficient that matching factor generation module 5 produces is finished at FFT computing module 6 and is entered FFT computing module 6 after the FFT computing of I/Q two paths of signals and carry out the FFT computing module, and operation result is stored among the RAM.After FFT module 6 is finished the FFT computing of matching factor, take advantage of the FFT result of 10 pairs of I/Q two paths of signals of module and the result of matching factor FFT to do multiple multiplication again, and the result after will taking advantage of again is stored among the RAM.After taking advantage of module 10 to finish multiple multiplication again, the IFFT11 module is done the IFFT computing to taking advantage of the result again, and the IFFT calculated result is exactly the result of pulse compression.

The result of pulse compression sends into the coherent accumulation module 14 in the DSP20 module, and coherent accumulation module 14 paired pulses compression result are done the FFT computing, finish pulse compression result's coherent accumulation.Result after the coherent accumulation sends into motion compensating module 15, motion compensating module 15 calculates the parameter of needs according to the result of coherent accumulation, and correlation parameter fed back to A/D controlling of sampling module 2, A/D controlling of sampling module 2 can be according to the parameter that feedback the obtains adjustment of sampling.The result of coherent accumulation also is admitted to CFAR detection (CFAR) module 19, and CFAR detection (CFAR) module 19 comprises sliding window module 16, detection threshold computing module 17 and signal detection module 18.Sliding window module 16 is done the sliding window processing that CFAR detects needs according to the result of coherent accumulation, result after the sliding window processing is sent into signal detection module 18, detection threshold computing module 17 can calculate according to the result of coherent accumulation and detect the needed detection threshold of target simultaneously, and sends detection threshold value to signal detection module 18.The result of last coherent accumulation detects whether there is target in signal detection module 18, and testing result is exported.

DSP and FPGA work in the SOMD pattern, with identical signal processing flow work.Here only analyze with passage 1.Because the needs of digital I/Q; system samples with the frequency of 160MHz; each impulse sampling is considered the protected location of a few μ s in the time; the last sampling time is 50 μ s; the complex sampling that obtains behind digital I/Q is counted totally 80 * 50=4000; therefore in the process of pulse compression, adopted 4096 FFT, IFFT and taking advantage of again.For each complex points, need the storage space of two words (word) to be respectively applied for storage real part and imaginary part, so the data volume of each pulse is 4096 * 2=8KWords=256Kbits; And because the pulse number of a frame signal is 170～256, so adopt 256 FFT when the coherent accumulation is Doppler, be that Doppler's unit number is 256, therefore to a frame signal carry out before the coherent accumulation data volume be 4096 * 256 * 2=2M Words=64Mbits; And after the coherent accumulation, because plural number has been carried out asking mould, data volume is 4096 * 256=1M Words=32Mbits.The Task Distribution of each chip is as shown in table 1 in the processor.In conjunction with the processing speed of XC4VSX55 and ADSP-TS201S, calculate the processing time of algorithm in processor, the traffic of front and back, the memory space that needs, the time of long permission is as shown in table 2.

Processing tasks in each processor of table 1

Each subalgorithm operand of table 2LFM-PD

According to the present invention, utilize FPGA and DSP design to realize a high speed intermediate frequency LFM-PD radar real-time processor, and Digital Down Convert and process of pulse-compression process are optimized, have the following advantages:

The processing speed height, the performance brilliance.

Utilize the method for designing of software and combination of hardware, the user can revise flexibly.

The algorithm of Digital Down Convert and pulse compression can be generalized in other digital signal processing algorithms among the present invention.

As seen, utilize FPGA and DSP design and Digital Down Convert and the intermediate frequency LFM-PD radar real-time processor realized that very high using value is arranged, can be applied in the military radar input, also can good development space be arranged simultaneously in the performance great role of civilian Data Detection field.

Claims (5)

1. intermediate frequency LFM-PD radar signal real time processing system based on FPGA and DSP, it is characterized in that comprising: FPGA (13) and DSP (20), wherein FPGA (13) comprises if sampling module (3), Digital Down Converter Module (4), pulse compression module (12), and if sampling module (3) is made up of A/D module (1) and A/D controlling of sampling module (2); DSP (20) comprises coherent accumulation module (14), motion compensating module (15) and CFAR detection (CFAR) module (19); The if radar signal enters in the if sampling module (3) of FPGA (13), and the direct IF Sampling of being controlled A/D module (1) by A/D controlling of sampling module (2) obtains digital medium-frequency signal; Digital medium-frequency signal enters Digital Down Converter Module (4), carries out Digital Down Convert, has obtained I, Q two paths of signals; I, Q two paths of signals enter pulse compression module (12) and carry out process of pulse-compression; Signal after the process of pulse-compression enters in the DSP coherent accumulation module (14) and carries out FFT, obtains coherent accumulation result; Signal after the coherent accumulation enters motion compensating module (15), calculates the motion compensation quantity that need make by movement compensating algorithm, and the controlling of sampling module (2) that the parameter that draws is fed back to FPGA (13) is adjusted the gate signal sequential; Signal after the last coherent accumulation enters CFAR detection (CFAR) module (19) and detects, and judges whether to exist target.

2. according to the described intermediate frequency LFM-PD radar signal real time processing system based on FPGA and DSP of claim 1, it is characterized in that: described pulse compression module (12) comprises matching factor generation module (5), FFT module (6), takes advantage of module (10) and IFFT module (11) again; I, Q signal are introduced into FFT module (6) and do the FFT computing, the coefficient of matching factor generation module (5) generation simultaneously and I, Q signal coupling, coefficient after producing is done the FFT computing, after the result that twice FFT draws enters and takes advantage of module (10) to carry out multiple multiplication again, enter IFFT module (11) and carry out the IFFT computing, the IFFT calculated result is the result after the process of pulse-compression.

3. according to the described intermediate frequency LFM-PD radar signal real time processing system of claim 1 based on FPGA and DSP, it is characterized in that: described motion compensating module adopts the envelope delay backoff algorithm, the target velocity result that described envelope delay backoff algorithm goes out by the previous frame data computation calculates the required motion compensation quantity of making of next frame data, feed back to controlling of sampling module (2) then, controlling of sampling module (2) is according to the sequential of the parameter adjustment gate signal of envelope delay backoff algorithm feedback.

4. according to the described intermediate frequency LFM-PD radar signal real time processing system based on FPGA and DSP of claim 1, it is characterized in that: described CFAR detection module (19) comprises sliding window module (16), detection threshold computing module (17) and signal detection module (18); Signal after the coherent accumulation is introduced into sliding window module (16); filter out detecting unit, protected location and reference unit via sliding window module (16); described detection unit refers to the zone that will detect; the protection unit is the unit adjacent with the detecting unit left and right sides; reference unit is the unit of detecting unit the right and left; calculate required detection threshold via detection threshold computing module (17) then, judge in the detecting unit whether have target by signal detection module (18) at last.

5. intermediate frequency LFM-PD radar signal real-time processing method based on FPGA and DSP is characterized in that performing step is as follows:

Step 1:, intermediate frequency LFM-PD radar signal is carried out quadrature sampling of medium frequency signal by the intermediate frequency LFM-PD radar signal discretize of if sampling module (3) with simulation;

Step 2: the digital signal that sampling obtains is carried out Digital Down Convert by Digital Down Converter Module (4), obtains I road signal and Q road signal;

Step 3:I road signal and Q road signal are by the pulse compression module (12) among the FPGA (13), earlier signal is done the FFT computing by FFT module (6), matching factor generation module (5) generates the coefficient with Signal Matching, FFT module (6) is again to doing the FFT computing with the coefficient of Signal Matching, the result of twice FFT computing enters and takes advantage of module (10) to take advantage of again again, result after taking advantage of again enters IFFT module (11) and carries out the IFFT computing, finishes pulse compression;

Step 4: utilize the signal after coherent accumulation module (14) the paired pulses compression of DSP (20) to carry out the FFT computing, finish the coherent accumulation;

Step 5: utilize DSP (20) that the result after the coherent accumulation is carried out motion compensation calculations, and the parameter that calculates is fed back to the controlling of sampling module (2) of FPGA (13), finish motion compensation to radar signal;

Step 6: utilize CFAR detection (CFAR) module (19) among the DSP (20) that the result after the coherent accumulation is carried out CFAR detection (CFAR); signal after the coherent accumulation is introduced into sliding window module (16); filter out detecting unit, protected location and reference unit via sliding window module (16); calculate required detection threshold via detection threshold computing module (17) then, judge in the detecting unit whether have target by signal detection module (18) at last.

Images