CN110297219A - A kind of FPGA coherent pulse signalf test method based on Ethernet data transmission - Google Patents
A kind of FPGA coherent pulse signalf test method based on Ethernet data transmission Download PDFInfo
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- CN110297219A CN110297219A CN201910623841.0A CN201910623841A CN110297219A CN 110297219 A CN110297219 A CN 110297219A CN 201910623841 A CN201910623841 A CN 201910623841A CN 110297219 A CN110297219 A CN 110297219A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/40—Means for monitoring or calibrating
- G01S7/4052—Means for monitoring or calibrating by simulation of echoes
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Abstract
The present invention discloses a kind of FPGA coherent pulse signalf test method based on Ethernet data transmission, solves coherent pulse signalf assessment inaccuracy, the low problem of debugging efficiency.This method passes through FPGA signal processing module first and obtains digital original echo matrix, and pulse pressure is carried out to original echo matrix and handles to obtain echo pulse pressure matrix, matrix is intercepted, clip pulse width, only leave significant wave door, obtain effective echo pulse pressure matrix, then by Ethernet card by echo pulse pressure Transfer-matrix to debugging computer, debugging computer carries out correlative accumulation processing to echo pulse pressure matrix, finally the peak point for extracting obtained echo accumulation matrix and amplitude threshold are compared, complete coherent pulse signalf assessment.It is poor according to single PRT range stability progress coherent pulse signalf accuracy of judgement degree that this method effectively solves the problems, such as conventional method, and debugging efficiency is high, is suitble to engineer application.
Description
Technical field
The present invention relates to FPGA module coherent pulse signalf the field of test technology, it is especially a kind of based on Ethernet data transmission
FPGA coherent pulse signalf test method.
Background technique
Coherent pulse signalf is particularly significant for coherent radar, will directly affect the pass such as power, DOPPLER RESOLUTION of radar
Key index.Coherent pulse signalf difference will lead to the decline of signal echo peak energy, or even cause echo splitting, generate false target, seriously
Influence radar performance.Therefore, can FPGA module correctly assess the coherent performance for receiving echo in signal processor, after guaranteeing
The correct implementation of continuous signal processing is of great significance in the application of the radar.
The coherent pulse signalf method that traditional FPGA module assessment receives echo is: debugging computer and FPGA module being passed through imitative
True device connection, opens debugging enironment software, acquires single PRT echo, after pulse pressure, records peak point amplitude size；It repeats
The above process receives echo coherent pulse signalf until obtaining all peak point amplitude situations of a frame echo with judgement.This method is being realized
Deficiency in the process is mainly: coherent pulse signalf is very sensitive for the variation of phase, but when phase change is smaller, amplitude variation
It is not obvious, judge by PRT from amplitude size, hardly result in the coherent characteristic of accurate whole frame echo；And connection is imitative
True device is acquired single echo, takes a long time, debugging efficiency is very low.
Summary of the invention
It is an object of that present invention to provide a kind of FPGA coherent pulse signalf test methods based on Ethernet data transmission, solve coherent
Property assessment inaccuracy, the low problem of debugging efficiency.
In this regard, the present invention proposes that a kind of FPGA coherent pulse signalf test method based on Ethernet data transmission, the first step are built
Coherent pulse signalf assessment system, coherent pulse signalf assessment system include: receiving channel, FPGA signal processing module, Ethernet card and debugging meter
Calculation machine；Receiving channel output end is connect with FPGA signal processing module input terminal conducting wire；FPGA signal processing module output end with
The connection of Ethernet card input terminal cable；Ethernet card output end is connect with debugging computer input terminal cable；Second step, FPGA letter
Number processing module echo sequence is sampled；Third step, FPGA signal processing module carry out pulse pressure processing to original echo sequence；
4th step, Ethernet card transmit echo pulse pressure matrix；5th step, debugging computer carry out coherent to echo pulse pressure matrix
Accumulation processing；6th step judges FPGA signal processing module coherent pulse signalf.
Wherein, it includes: signal echo through coherent radar that second step, FPGA signal processing module echo sequence, which carry out sampling,
Receiving channel receives, and is sampled by FPGA signal processing module to it, converts digital original echo matrix for analogue echo,
Digital original echo matrix is denoted as z (i, j), and wherein j is the sampling number of each echo impulse, and j=1,2 ... N, N are single return
Total sampling number of wave impulse, i=1,2 ... M, M are that single frames echo accumulates pulse sum.
Wherein, it includes: at FPGA signal that third step, FPGA signal processing module, which carry out pulse pressure processing to original echo sequence,
Reason module carries out pulse pressure to original echo matrix Echo (i, j) and handles to obtain echo pulse pressure matrix Echo_Acc (i, j)；
Echo_Acc (i, j)=IFFT [conj (FFT [Echo (i, j)]) * FFT [exp { j π kt2}]] (1)
Wherein k is echo-signal chirp rate, and t is the pulse duration.
Wherein, it includes: FPGA signal processing module to echo that the 4th step, Ethernet card, which carry out transmission to echo pulse pressure matrix,
Pulse pressure matrix is intercepted, and pulse width is clipped, and only leaves significant wave door, obtain effective echo pulse pressure matrix Echo_AccS (i,
j)；The matrix package is sent to debugging computer at data packet format, and by high speed cable by Ethernet card.
Wherein, it includes: that debugging computer will that the 5th step, debugging computer, which carry out correlative accumulation processing to echo pulse pressure matrix,
Obtained data packet carries out unpacking processing, retrieves effective echo pulse pressure matrix Echo_AccS (i, j), carries out to the matrix
Correlative accumulation obtains echo accumulation matrix Echo_AccA (i, j)；
Echo_AccA (i, j)=FFT [Echo_AccS (i, j)]
(2)。
Wherein, the 6th step, judge FPGA signal processing module coherent pulse signalf include: choose echo accumulation matrix Echo_AccA
(i, j) peak point amplitude is Speak, with amplitude threshold SthIt is compared, if Speak≥Sth, then FPGA signal processing module coherent
Property is met the requirements；Otherwise, after adjustment FPGA signal processing module processing timing, step 2 is repeated to step 6.At FPGA signal
Reason module coherent pulse signalf test process terminates, the high echo of output coherent pulse signalf.
Present invention is mainly applied to pulses to compress coherent radar system, can effectively solve conventional method according to single PRT amplitude
Stability carries out the problem of coherent pulse signalf accuracy of judgement degree difference, and debugging efficiency is high, is suitble to engineer application.
Specific embodiment
A specific embodiment of the invention is explained in detail below.
A kind of specific steps of FPGA coherent pulse signalf test method based on Ethernet data transmission disclosed by the invention are as follows:
The first step builds coherent pulse signalf assessment system
Coherent pulse signalf assessment system, comprising: receiving channel, FPGA signal processing module, Ethernet card and debugging computer；
Receiving channel output end is connect with FPGA signal processing module input terminal conducting wire；FPGA signal processing module output end
It is connect with Ethernet card input terminal cable；Ethernet card output end is connect with debugging computer input terminal cable；
Second step, FPGA signal processing module echo sequence are sampled
Signal echo is received through the receiving channel of coherent radar, is sampled by FPGA signal processing module to it, by mould
Quasi- echo is converted into digital original echo matrix, is denoted as z (i, j), wherein sampling number of the j for each echo impulse, j=1,
2 ... N, N are total sampling number of single echo impulse, and i=1,2 ... M, M are that single frames echo accumulates pulse sum；
Third step, FPGA signal processing module carry out pulse pressure processing to original echo sequence
FPGA signal processing module carries out pulse pressure to original echo matrix Echo (i, j) and handles to obtain echo pulse pressure matrix
Echo_Acc(i,j)；
Echo_Acc (i, j)=IFFT [conj (FFT [Echo (i, j)]) * FFT [exp { j π kt2}]] (1)
Wherein k is echo-signal chirp rate, and t is the pulse duration；
4th step, Ethernet card transmit echo pulse pressure matrix
FPGA signal processing module intercepts echo pulse pressure matrix, clips pulse width, only leaves significant wave door, obtains
To effective echo pulse pressure matrix Echo_AccS (i, j)；Ethernet card by the matrix package at data packet format, and pass through high speed
Cable is sent to debugging computer.
5th step, debugging computer carry out correlative accumulation processing to echo pulse pressure matrix
Obtained data packet is carried out unpacking processing by debugging computer, retrieves effective echo pulse pressure matrix Echo_
AccS (i, j) carries out correlative accumulation to the matrix, obtains echo accumulation matrix Echo_AccA (i, j).
Echo_AccA (i, j)=FFT [Echo_AccS (i, j)] (2)
6th step judges FPGA signal processing module coherent pulse signalf
Choosing echo accumulation matrix Echo_AccA (i, j) peak point amplitude is Speak, with amplitude threshold SthIt is compared,
If Speak≥Sth, then FPGA signal processing module coherent pulse signalf is met the requirements；Otherwise, adjustment FPGA signal processing module handles timing
Afterwards, step 2 is repeated to step 6.
FPGA signal processing module coherent pulse signalf test process terminates, the high echo of output coherent pulse signalf.
Present invention is mainly applied to pulses to compress coherent radar system, can effectively solve conventional method according to single PRT amplitude
Stability carries out the problem of coherent pulse signalf accuracy of judgement degree difference, and debugging efficiency is high, is suitble to engineer application.
Claims (6)
1. a kind of FPGA coherent pulse signalf test method based on Ethernet data transmission, which is characterized in that
The first step builds coherent pulse signalf assessment system, the coherent pulse signalf assessment system include: receiving channel, FPGA signal processing module,
Ethernet card and debugging computer；Receiving channel output end is connect with FPGA signal processing module input terminal conducting wire；FPGA signal
Processing module output end is connect with Ethernet card input terminal cable；Ethernet card output end and debugging computer input terminal cable connect
It connects；
Second step, FPGA signal processing module echo sequence are sampled；
Third step, FPGA signal processing module carry out pulse pressure processing to original echo sequence；
4th step, Ethernet card transmit echo pulse pressure matrix；
5th step, debugging computer carry out correlative accumulation processing to echo pulse pressure matrix；
6th step judges FPGA signal processing module coherent pulse signalf.
2. with according to method described in claim 1, which is characterized in that
Second step, FPGA signal processing module echo sequence carry out sampling
Signal echo is received through the receiving channel of coherent radar, is sampled, will be simulated back to it by FPGA signal processing module
Wave is converted into digital original echo matrix, and digital original echo matrix is denoted as z (i, j), and wherein j is the sampling of each echo impulse
Points, j=1,2 ... N, N are total sampling number of single echo impulse, and i=1,2 ... M, M are that the accumulation pulse of single frames echo is total
Number.
3. with according to method as claimed in claim 2, which is characterized in that
Third step, FPGA signal processing module carry out pulse pressure processing to original echo sequence and include:
FPGA signal processing module carries out pulse pressure to original echo matrix Echo (i, j) and handles to obtain echo pulse pressure matrix Echo_
Acc(i,j)；
Echo_Acc (i, j)=IFFT [conj (FFT [Echo (i, j)]) * FFT [exp { j π kt2}]] (1)
Wherein k is echo-signal chirp rate, and t is the pulse duration.
4. with according to method as claimed in claim 3, which is characterized in that
4th step, Ethernet card carry out transmission to echo pulse pressure matrix and include:
FPGA signal processing module intercepts echo pulse pressure matrix, clips pulse width, only leaves significant wave door, is had
It imitates echo pulse pressure matrix Echo_AccS (i, j)；Ethernet card by the matrix package at data packet format, and pass through high speed cable
It is sent to debugging computer.
5. with according to method as claimed in claim 4, which is characterized in that
5th step, debugging computer carry out correlative accumulation processing to echo pulse pressure matrix and include:
Obtained data packet is carried out unpacking processing by debugging computer, retrieve effective echo pulse pressure matrix Echo_AccS (i,
J), correlative accumulation is carried out to the matrix, obtains echo accumulation matrix Echo_AccA (i, j)；
Echo_AccA (i, j)=FFT [Echo_AccS (i, j)] (2).
6. with according to the method described in claim 5, which is characterized in that
6th step judges that FPGA signal processing module coherent pulse signalf includes:
Choosing echo accumulation matrix Echo_AccA (i, j) peak point amplitude is Speak, with amplitude threshold SthIt is compared, if Speak
≥Sth, then FPGA signal processing module coherent pulse signalf is met the requirements；Otherwise, after adjustment FPGA signal processing module processing timing, weight
Step 2 is answered to step 6.
FPGA signal processing module coherent pulse signalf test process terminates, the high echo of output coherent pulse signalf.
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