CN110927676A - Radar signal processing device and method thereof - Google Patents
Radar signal processing device and method thereof Download PDFInfo
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- CN110927676A CN110927676A CN201911141601.3A CN201911141601A CN110927676A CN 110927676 A CN110927676 A CN 110927676A CN 201911141601 A CN201911141601 A CN 201911141601A CN 110927676 A CN110927676 A CN 110927676A
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Abstract
A radar signal processing device and method thereof, comprising an FPGA processor and a DSP processor; the FPGA processor is connected with the DSP processor; the FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the flight path processing of radar signals. And the FPGA processor and the DSP processor are connected through 4 paths of RapidIO interfaces. The FPGA processor is used for carrying out pulse pressure processing on the radar signal; and the DSP is used for carrying out signal detection, trace point processing and track processing on the radar signal. By combining other structures or methods, the defects of excessive burden, low efficiency and high error rate of pulse pressure processing, signal detection, trace point processing and track processing of radar signals by a single processor in the prior art are effectively overcome.
Description
Technical Field
The invention relates to the technical field of radar signals and signal processing, in particular to a radar signal processing device and a method thereof.
Background
Radar, which finds objects and determines their spatial position by radio. Therefore, radar is also referred to as "radiolocation". Radars are electronic devices that detect objects using electromagnetic waves. The radar emits electromagnetic waves to irradiate a target and receives the echo of the target, so that information such as the distance from the target to an electromagnetic wave emission point, the distance change rate (radial speed), the azimuth and the altitude is obtained. The typical frequency band occupied by radar signals is from 500 mhz to 18 ghz, with millimeter wave radars operating at frequencies up to 40 ghz and beyond.
The pulse pressure processing, the signal detection, the trace point processing and the trace track processing are all integrated in one processor at present, so that the single processor can carry out the pulse pressure processing, the signal detection, the trace point processing and the trace track processing with heavy burden, low efficiency and high error rate.
Disclosure of Invention
In order to solve the above problems, the present invention provides a radar signal processing apparatus and a method thereof, which effectively avoid the defects of excessive load, low efficiency and high error rate of pulse pressure processing, signal detection, trace point processing and track processing performed on radar signals by a single processor in the prior art.
In order to overcome the defects in the prior art, the invention provides a radar signal processing device and a solution of the method thereof, which specifically comprise the following steps:
a radar signal processing device comprises an FPGA processor and a DSP processor;
the FPGA processor is connected with the DSP processor;
the FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the flight path processing of radar signals.
And the FPGA processor and the DSP processor are connected through 4 paths of RapidIO interfaces.
The FPGA processor is used for carrying out pulse pressure processing on the radar signal;
and the DSP is used for carrying out signal detection, trace point processing and track processing on the radar signal. The DSP processor is connected with the four-channel ADC;
the four-channel ADC is used for receiving radar signals and performing analog-to-digital conversion on the radar signals, and the digital signals after the analog-to-digital conversion are sent to the DSP processor.
The DSP processor is also connected with the input end of the DAC;
the DAC is used as a waveform generation channel of the radar signal.
The FPGA processor, the four-channel ADC and the DAC are all connected with the clock generator;
the clock generator is used for providing clock signals for the FPGA processor, the four-channel ADC and the DAC;
the clock generator is also used for distributing and processing the clock signals provided for the FPGA processor and the four-channel ADC;
the FPGA processor is also connected with a first Flash memory, an RS422 interface and an SATA interface;
the DSP processor is also connected to the SEP interface, DDR3 memory, and 88E 1111.
The input end of the DAC is a passive coupling structure, and the passive coupling structure is directly coupled to the input end of the DAC through a transformer;
the DDR3 memory is in a plurality of numbers, the DDR3 memory adopts a serial topology structure, and the DDR3 memory is added with a termination resistor.
The DSP processor is a TMS6678 type DSP processor, the FPGA processor is an XC6VLX240T-1FFG1156 type FPGA processor, the four-channel ADC is an AD9653 type four-channel ADC, the DAC is an AD9739 type DAC, and the clock generator is an AD9516 type clock generator.
The method of the radar signal processing device comprises the following steps:
step 1: the four-channel ADC receives radar signals and performs analog-to-digital conversion on the radar signals, and digital signals after analog-to-digital conversion are sent to the DSP;
step 2: the DSP processor performs signal detection, trace point processing and track processing on the radar signal;
and step 3: and the DSP processor forwards the radar signals to the FPGA processor, so that the radar signals are subjected to pulse pressure processing.
The invention has the beneficial effects that:
the invention shares the pulse pressure processing, the signal detection, the trace point processing and the flight path processing to radar signals through the FPGA processor and the DSP processor, uses the two processors to carry out the pulse pressure processing, the signal detection, the trace point processing and the flight path processing, can reduce the problems of overweight burden, low efficiency and high error rate of the single processor to the pulse pressure processing, the signal detection, the trace point processing and the flight path processing to the radar signals, therefore, the burden of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is reduced, the efficiency of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is improved, and the error rate of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor can also be reduced.
Drawings
Fig. 1 is an overall configuration diagram of a radar signal processing device according to the present invention.
Fig. 2 is a schematic diagram of the clock generator of the present invention.
Fig. 3 is a functional block diagram of an AD9653 type four-channel ADC of the present invention.
Fig. 4 is a functional block diagram of an AD9739 DAC of the present invention.
Detailed Description
The invention will be further described with reference to the following figures and examples.
Example 1:
as shown in fig. 1-4, the radar signal processing device includes an FPGA processor and a DSP processor; the FPGA processor is connected with the DSP processor; the FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the flight path processing of radar signals. Thus, the FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the track processing to radar signals, and the two processors are used for the pulse pressure processing, the signal detection, the trace point processing and the track processing, so that the problems of overweight burden, low efficiency and high error rate of the pulse pressure processing, the signal detection, the trace point processing and the track processing to radar signals by a single processor can be reduced, therefore, the burden of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is reduced, the efficiency of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is improved, and the error rate of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor can also be reduced. And the FPGA processor and the DSP processor are connected through 4 paths of RapidIO interfaces. The 4-way RapidIO interface serving as the high-speed interface can enable the communication between the FPGA processor and the DSP processor to be very efficient and convenient. The FPGA processor is used for carrying out pulse pressure processing on the radar signal; and the DSP is used for carrying out signal detection, trace point processing and track processing on the radar signal. The FPGA processor is used for carrying out pulse pressure processing on the radar signals, and the DSP processor is used for carrying out signal detection, trace point processing and track processing on the radar signals, so that the division of work for processing the radar signals can be definitely carried out between the FPGA processor and the DSP processor, and the processing of the radar signals is efficient and orderly. The DSP processor is connected with the four-channel ADC; the four-channel ADC is used for receiving radar signals and performing analog-to-digital conversion on the radar signals, and the digital signals after the analog-to-digital conversion are sent to the DSP processor. The DSP processor is also connected with the input end of the DAC; the DAC is used as a waveform generation channel of the radar signal. The FPGA processor, the four-channel ADC and the DAC are all connected with the clock generator; the clock generator is used for providing clock signals for the FPGA processor, the four-channel ADC and the DAC; the clock generator is also used for distributing and processing the clock signals provided for the FPGA processor and the four-channel ADC; the FPGA processor is also connected with a first Flash memory, an RS422 interface and an SATA interface; the DSP processor is also connected to the SEP interface, DDR3 memory, and 88E 1111. Therefore, the FPGA processor and the DSP processor can buffer or store data through the memories connected with the FPGA processor and the DSP processor, and can be connected with external equipment through various interfaces, so that the communication with the outside is more flexible. The input end of the DAC is a passive coupling structure, and the passive coupling structure is directly coupled to the input end of the DAC through a transformer; the DDR3 memory is a plurality of memories, the DDR3 memory adopts a series topology structure instead of a star topology structure in view of simple wiring, and the DDR3 memory is additionally connected with a termination resistor in view of signal integrity. The DSP processor is a TMS6678 type DSP processor, the FPGA processor is an XC6VLX240T-1FFG1156 type FPGA processor, the four-channel ADC is an AD9653 type four-channel ADC, the DAC is an AD9739 type DAC, and the clock generator is an AD9516 type clock generator. Because the ADC works at a lower frequency, the clock generator is required to carry out frequency division on the basis of a new number of 2GHz for the clock of the ADC, and the clock generator is also required to carry out frequency division processing on the clock of the FPGA.
The AD9653 type four-channel ADC has the following characteristics:
a) 1.8V power supply
b) Low power consumption: 164 mW per channel (125 MSPS)
c) Signal-to-noise ratio (SNR): 76.5 dBFS (70 MHz, 2.0V p-p input range)
d) Signal-to-noise ratio (SNR): 77.5 dBFS (70 MHz, 2.6V p-p input range)
e) SFDR: 90 dBc (to Nyquist, 2.0V p-p input range)
f) DNL: 0.7 LSB; INL: + -3.5 LSB (2.0V p-p input range)
g) Serial LVDS (ANSI-644, default), low power, reduced range options (similar to IEEE 1596.3)
h) 650 MHz full-power analog bandwidth
i) 2V p-p input voltage range (supporting up to 2.6V p-p); serial port control; full chip and single channel power saving modes; flexible bit orientation; a built-in generated and user-defined digital test code is generated; a multi-chip synchronization and clock divider; programmable output clock and data alignment; a standby mode.
The AD9739 DAC is mainly characterized in that:
a) sampling rate: 2.5GHz
b) Precision: 14bit
c) Three interpolation modes are supported;
d) simulating bandwidth width;
e) interface: LVDS;
f) and the power consumption is low.
Example 2:
as shown in fig. 1-4, the radar signal processing device includes an FPGA processor and a DSP processor; the FPGA processor is connected with the DSP processor; the FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the flight path processing of radar signals. Thus, the FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the track processing to radar signals, and the two processors are used for the pulse pressure processing, the signal detection, the trace point processing and the track processing, so that the problems of overweight burden, low efficiency and high error rate of the pulse pressure processing, the signal detection, the trace point processing and the track processing to radar signals by a single processor can be reduced, therefore, the burden of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is reduced, the efficiency of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is improved, and the error rate of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor can also be reduced. And the FPGA processor and the DSP processor are connected through 4 paths of RapidIO interfaces. The 4-way RapidIO interface serving as the high-speed interface can enable the communication between the FPGA processor and the DSP processor to be very efficient and convenient. The FPGA processor is used for carrying out pulse pressure processing on the radar signal; and the DSP is used for carrying out signal detection, trace point processing and track processing on the radar signal. The FPGA processor is used for carrying out pulse pressure processing on the radar signals, and the DSP processor is used for carrying out signal detection, trace point processing and track processing on the radar signals, so that the division of work for processing the radar signals can be definitely carried out between the FPGA processor and the DSP processor, and the processing of the radar signals is efficient and orderly. The DSP processor is connected with the four-channel ADC; the four-channel ADC is used for receiving radar signals and performing analog-to-digital conversion on the radar signals, and the digital signals after the analog-to-digital conversion are sent to the DSP processor. The DSP processor is also connected with the input end of the DAC; the DAC is used as a waveform generation channel of the radar signal. The FPGA processor, the four-channel ADC and the DAC are all connected with the clock generator; the clock generator is used for providing clock signals for the FPGA processor, the four-channel ADC and the DAC; the clock generator is also used for distributing and processing the clock signals provided for the FPGA processor and the four-channel ADC; the FPGA processor is also connected with a first Flash memory, an RS422 interface and an SATA interface; the DSP processor is also connected to the SEP interface, DDR3 memory, and 88E 1111. Therefore, the FPGA processor and the DSP processor can buffer or store data through the memories connected with the FPGA processor and the DSP processor, and can be connected with external equipment through various interfaces, so that the communication with the outside is more flexible. The input end of the DAC is a passive coupling structure, and the passive coupling structure is directly coupled to the input end of the DAC through a transformer; the DDR3 memory is a plurality of memories, the DDR3 memory adopts a series topology structure instead of a star topology structure in view of simple wiring, and the DDR3 memory is additionally connected with a termination resistor in view of signal integrity. The DSP processor is a TMS6678 type DSP processor, the FPGA processor is an XC6VLX240T-1FFG1156 type FPGA processor, the four-channel ADC is an AD9653 type four-channel ADC, the DAC is an AD9739 type DAC, and the clock generator is an AD9516 type clock generator. Because the ADC works at a lower frequency, the clock generator is required to carry out frequency division on the basis of a new number of 2GHz for the clock of the ADC, and the clock generator is also required to carry out frequency division processing on the clock of the FPGA. The AD9653 type four-channel ADC has the following characteristics:
a) 1.8V power supply
b) Low power consumption: 164 mW per channel (125 MSPS)
c) Signal-to-noise ratio (SNR): 76.5 dBFS (70 MHz, 2.0V p-p input range)
d) Signal-to-noise ratio (SNR): 77.5 dBFS (70 MHz, 2.6V p-p input range)
e) SFDR: 90 dBc (to Nyquist, 2.0V p-p input range)
f) DNL: 0.7 LSB; INL: + -3.5 LSB (2.0V p-p input range)
g) Serial LVDS (ANSI-644, default), low power, reduced range options (similar to IEEE 1596.3)
h) 650 MHz full-power analog bandwidth
i) 2V p-p input voltage range (supporting up to 2.6V p-p); serial port control; full chip and single channel power saving modes; flexible bit orientation; a built-in generated and user-defined digital test code is generated; a multi-chip synchronization and clock divider; programmable output clock and data alignment; a standby mode.
The AD9739 DAC is mainly characterized in that:
a) sampling rate: 2.5GHz
b) Precision: 14bit
c) Three interpolation modes are supported;
d) simulating bandwidth width;
e) interface: LVDS;
f) and the power consumption is low.
The method of the radar signal processing device comprises the following steps:
step 1: the four-channel ADC receives radar signals and performs analog-to-digital conversion on the radar signals, and digital signals after analog-to-digital conversion are sent to the DSP;
step 2: the DSP processor performs signal detection, trace point processing and track processing on the radar signal;
and step 3: and the DSP processor forwards the radar signals to the FPGA processor, so that the radar signals are subjected to pulse pressure processing. The FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the track processing to radar signals, and the two processors are used for the pulse pressure processing, the signal detection, the trace point processing and the track processing, so that the problems of overweight burden, low efficiency and high error rate of the pulse pressure processing, the signal detection, the trace point processing and the track processing to radar signals by a single processor can be reduced, therefore, the burden of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is reduced, the efficiency of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor is improved, and the error rate of pulse pressure processing, signal detection, trace point processing and track processing on the radar signals by the FPGA processor and the DSP processor can also be reduced. The FPGA processor is used for carrying out pulse pressure processing on the radar signals, and the DSP processor is used for carrying out signal detection, trace point processing and track processing on the radar signals, so that the division of work for processing the radar signals can be definitely carried out between the FPGA processor and the DSP processor, and the processing of the radar signals is efficient and orderly.
In order to realize the purpose of remote monitoring data, the DSP processor also needs to transmit the obtained digital signal data to a background server in real time to be displayed for remote monitoring, so that the DSP processor is connected with a wireless communication module, the wireless communication module is connected with the background server in a wireless network through the wireless network, the wireless communication module can be a 3G module or a 4G module, the wireless network can be a 3G network or a 4G network, and the background server can be a PC (personal computer), so the DSP processor also needs to transmit the obtained digital signal data to the background server through the wireless communication module in real time to be displayed for remote monitoring, and the background server also needs to return a response message to the DSP processor after receiving the digital signal data; however, the current wireless data transmission mode can achieve data exchange between the background server and the DSP processor; however, due to the constraint that the reliability of data communication between the DSP processor and the backend server, which is easily compromised, is not high via the wireless network, the disadvantage of low reliability performance of data communication between the backend server and the DSP processor is often accompanied; therefore, it is an urgent objective to provide a data transfer method and system to improve the performance of data transfer between the background server and the DSP processor.
Through improvement, in order to achieve the purpose of remote data monitoring, the DSP processor further needs to transmit the obtained digital signal data to a background server in real time for displaying for remote monitoring, so that the DSP processor is connected to the wireless communication module, the wireless communication module is connected to the background server in a wireless network through the wireless network, the wireless communication module can be a 3G module or a 4G module, the wireless network can be a 3G network or a 4G network, and the background server can be a PC, so the DSP processor further needs to transmit the obtained digital signal data to the background server through the wireless communication module in real time for displaying for remote monitoring, and the background server needs to return a response message to the DSP processor after receiving the digital signal data;
the DSP processor transmits the obtained digital signal data to the background server through the wireless communication module, and the method comprises the following steps:
step A-1: receiving a first data transmitted by the DSP through the USB port; the first data is the digital signal data.
Further, when data transfer between the DSP processor and the background server needs to be achieved, the DSP processor needs to be connected to the wireless communication module through a structure connected to the USB port to achieve physical connection between the DSP processor and the wireless communication module, and the wireless communication module is connected to the background server through a wireless network to achieve link connection between the wireless communication module and the background server.
Furthermore, during the period of transferring the data to the background server by the DSP processor, the wireless communication module initially receives the data transferred by the DSP processor through the USB port.
Step A-2: and when the first data is confirmed to meet the preset first transmission requirement, transmitting the first data to the background server in a wireless network transmission mode, and enabling the background server to respond to the first data to construct a second data.
Further, when the wireless communication module determines that the first data meets the first preset transfer requirement, the first data can be transferred to the background server in a wireless network transfer mode, and the background server responds to the first data to construct a second data; thus, the method for the wireless communication module to determine that the data conforms to the preset transmission requirement includes the following steps:
step B-1: receiving third data which is transmitted by the DSP through the USB port and encoded by applying a preset encoding parameter I, wherein the third data is encoded data constructed by applying the first data through the DSP by means of a preset encoder;
furthermore, a first coding parameter is preset in the DSP processor, and when the first data is determined to meet a first preset transmission requirement, the first data needs to be received and transmitted by the DSP processor through the USB port and coded by using the preset first coding parameter; here, the DSP processor is preset with an encoder, and the third data is encoded data constructed by the preset encoder through the DSP processor application data.
Step B-2: decoding the received coded data III by using a preset decoding parameter to obtain first processed data III;
further, the decoding parameters are parameters required for the encoder to decode the encoded data after the data-to-data encoding is performed using the encoding parameters.
Furthermore, a first decoding parameter is preset in the wireless communication module, and after receiving a third data which is transmitted by the DSP through the USB port and is encoded by using the first preset encoding parameter, the third data which is received and encoded can be decoded by using the decoding parameter preset in the wireless communication module, so that a third data which is processed by the first processing is obtained.
Step B-3: constructing second processed data III by using the data I through a preset encoder;
furthermore, an encoder is preset in the wireless communication module, and the encoder preset in the wireless communication module is the same as the encoder preset in the DSP processor.
Step B-4: judging whether the data III after the first processing is the same as the data III after the second processing; at the same time, executing step B-5;
step B-5: and confirming that the data one meets the preset transmission requirement one.
Further, when the third processed data is determined to be the same as the third processed data, the first processed data is determined to meet the transmission requirement, i.e., the first processed data received by the wireless communication module is indeed transmitted through the DSP processor connected with the wireless communication module.
Further, in the method for confirming that the data one conforms to the preset transmission requirement one, when the data three after the first processing is judged to be different from the data three after the second processing, the data one is confirmed not to conform to the preset transmission requirement one, namely, the data received by the wireless communication module is not transmitted through the DSP processor connected with the wireless communication module.
In order to further ensure the reliability of the method for transmitting the obtained digital signal data to the background server by the DSP processor through the wireless communication module, the first data can be set as the first initial data which is transmitted by the DSP processor and encoded by using the second encoding parameter.
Further, when the first data is initial data which is transmitted by the DSP processor and encoded by applying the encoding parameter two, the first data is transmitted to the background server via wireless transmission, so that the background server responds to the first data to construct the second data, which includes: and transmitting the first data to the background server in a wireless transmission mode, so that the background server can utilize two pairs of preset decoding parameters to execute decoding on the first data to obtain the first initial data and respond to the first initial data to construct the second data.
Further, the decoding parameter is a parameter required by the encoder to decode the encoded data encoded by applying the encoding parameter pair to the data one.
Furthermore, a second encoding parameter is preset in the DSP, and the first data is obtained after the DSP uses the first encoding parameter to perform encoding on the first initial data.
Furthermore, a second decoding parameter is preset in the background server, and when the first data is received by the background server and is obtained by encoding the first initial data, the first initial data is obtained by decoding the first data by using the preset second decoding parameter, so that the second data is constructed by responding to the first initial data.
The method is applied to a wireless communication module, and data I transmitted by a receiving DSP processor in a wireless transmission mode is received; when the first data is confirmed to meet the preset first transmission requirement, the first data is transmitted to the background server in a wireless transmission mode, the background server responds to the first data to construct a second data mode, the effect that the DSP processor uses the wireless communication module to achieve data transmission with the background server through the wireless network is achieved, the constraint that the reliability of data transmission between the DSP processor and the background server through the wireless network is not high, and the performance of data transmission between the background server and the DSP processor is improved.
The method for the background server to return the response message to the DSP processor is a method for transmitting a second data serving as the response message to the DSP processor through the background server by virtue of a connecting structure among the DSP processor, the wireless communication module and the background server after the background server receives the first data and constructs the second data serving as the response message for the DSP processor, and comprises the following steps:
step C-1: receiving data II transmitted by the background server in a wireless transmission mode;
further, after receiving the first data at the background server and obtaining the second data for responding to the DSP processor by means of the first data, the second data can be initially transferred to the wireless communication module via the background server in a wireless transfer manner, so that the wireless communication module can receive the second data transferred by the background server in a wireless transfer manner.
Step C-2: the second data is transmitted to the DSP in a wireless transmission mode, so that the second data is favorably applied to control the second data when the DSP determines that the second data meets the second preset transmission requirement.
Furthermore, after the wireless communication module receives the second data transmitted by the background server in a wireless transmission mode, the second data can be transmitted to the DSP through the USB port, and the second data is favorably used for achieving the control of the second data when the DSP receives the second data and the second data is determined to meet the second preset transmission requirement.
In order to further ensure the reliability of the method for the background server to return the response message to the DSP processor, the data II can be set as initial data II constructed by the background server to respond to the initial data I, and the preset decoding parameters are also used for executing coding construction on the initial data II.
As for example, when the received data at the background server is the initial data one encoded by using the encoding parameter two and transmitted by the DSP processor, the background server can perform decoding by using the decoding parameter two set in advance after receiving the data one to obtain the initial data one; then, the background server can obtain initial data II for responding to the DSP processor by means of the initial data I, and in order to ensure the reliability of the data transmission method, the background server can use the preset decoding parameters to execute coding on the initial data II to construct data II.
Further, when the second data is the second initial data constructed by the background server responding to the first initial data and using the preset decoding parameter pair to execute the coding construction to the second initial data, the second data is transmitted to the DSP processor in a wireless transmission manner, so that when the DSP processor determines that the second data meets the preset transmission requirement pair, the second data is used to achieve the control of the second data, including: and transmitting the second data to the DSP in a wireless transmission mode, so that the DSP can use the preset encoding parameters to decode the second data to obtain the second initial data and use the second initial data to control the second initial data.
The background server transmits the second data to the wireless communication module in a wireless transmission mode, and then transmits the second data to the DSP processor through the USB port through the wireless communication module, so that the effect that the background server uses the wireless communication module to achieve data transmission with the DSP processor is achieved, and the performance of data transmission between the background server and the DSP processor can be improved.
The present invention has been described in an illustrative manner by the embodiments, and it should be understood by those skilled in the art that the present disclosure is not limited to the embodiments described above, but is capable of various changes, modifications and substitutions without departing from the scope of the present invention.
Claims (9)
1. The radar signal processing device is characterized by comprising an FPGA processor and a DSP processor;
the FPGA processor is connected with the DSP processor;
the FPGA processor and the DSP processor share the pulse pressure processing, the signal detection, the trace point processing and the flight path processing of radar signals.
2. The radar signal processing apparatus of claim 1, wherein the FPGA processor and the DSP processor are connected via a 4-way RapidIO interface.
3. The radar signal processing apparatus of claim 1, wherein the FPGA processor is configured to perform pulse pressure processing on the radar signal;
and the DSP is used for carrying out signal detection, trace point processing and track processing on the radar signal.
4. The radar signal processing apparatus of claim 1, wherein the DSP is configured to perform the processing at
The processor is connected with the four-channel ADC;
the four-channel ADC is used for receiving radar signals and performing analog-to-digital conversion on the radar signals, and the digital signals after the analog-to-digital conversion are sent to the DSP processor.
5. The radar signal processing apparatus of claim 1, wherein the DSP processor is further connected to an input of the DAC;
the DAC is used as a waveform generation channel of the radar signal.
6. The radar signal processing apparatus of claim 1, wherein the FPGA processor, the four-channel ADC and the DAC are each connected to a clock generator;
the clock generator is used for providing clock signals for the FPGA processor, the four-channel ADC and the DAC;
the clock generator is also used for distributing and processing the clock signals provided for the FPGA processor and the four-channel ADC;
the FPGA processor is also connected with a first Flash memory, an RS422 interface and an SATA interface;
the DSP processor is also connected to the SEP interface, DDR3 memory, and 88E 1111.
7. The radar signal processing apparatus of claim 6, wherein the input of the DAC is a passive coupling structure, the passive coupling structure being directly coupled to the DAC input through a transformer;
the DDR3 memory is in a plurality of numbers, the DDR3 memory adopts a serial topology structure, and the DDR3 memory is added with a termination resistor.
8. The radar signal processing apparatus of claim 6, wherein the DSP processor is a TMS6678 type DSP processor, the FPGA processor is an XC6VLX240T-1FFG1156 type FPGA processor, the four-channel ADC is an AD9653 type four-channel ADC, the DAC is an AD9739 type DAC, and the clock generator is an AD9516 type clock generator.
9. A method of a radar signal processing apparatus, comprising:
step 1: the four-channel ADC receives radar signals and performs analog-to-digital conversion on the radar signals, and digital signals after analog-to-digital conversion are sent to the DSP;
step 2: the DSP processor performs signal detection, trace point processing and track processing on the radar signal;
and step 3: and the DSP processor forwards the radar signals to the FPGA processor, so that the radar signals are subjected to pulse pressure processing.
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