CN107276768B - C interface board circuit for ground electronic unit - Google Patents

C interface board circuit for ground electronic unit Download PDF

Info

Publication number
CN107276768B
CN107276768B CN201710516969.8A CN201710516969A CN107276768B CN 107276768 B CN107276768 B CN 107276768B CN 201710516969 A CN201710516969 A CN 201710516969A CN 107276768 B CN107276768 B CN 107276768B
Authority
CN
China
Prior art keywords
signal
processing unit
module
message
signal processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710516969.8A
Other languages
Chinese (zh)
Other versions
CN107276768A (en
Inventor
诸葛晓钟
李晓光
居礼
王勇
蒋耀东
唐俊
徐先良
潘雷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casco Signal Ltd
Original Assignee
Casco Signal Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casco Signal Ltd filed Critical Casco Signal Ltd
Priority to CN201710516969.8A priority Critical patent/CN107276768B/en
Publication of CN107276768A publication Critical patent/CN107276768A/en
Application granted granted Critical
Publication of CN107276768B publication Critical patent/CN107276768B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/02—Details
    • H04L12/06—Answer-back mechanisms or circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
    • B61L27/40—Handling position reports or trackside vehicle data
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L27/00—Central railway traffic control systems; Trackside control; Communication systems specially adapted therefor
    • B61L27/70—Details of trackside communication
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mechanical Engineering (AREA)
  • Computer Security & Cryptography (AREA)
  • Train Traffic Observation, Control, And Security (AREA)

Abstract

The invention relates to a C interface board circuit for a ground electronic unit, which comprises an FPGA (field programmable gate array) logic processing unit, a C6 signal processing unit, a C4 signal processing unit and a C1 signal processing unit, wherein the FPGA logic processing unit is respectively connected with the C6 signal processing unit, the C4 signal processing unit and the C1 signal processing unit, and the C6 signal processing unit is connected with the C4 signal processing unit; the FPGA logic processing unit converts the received message information into control signals corresponding to the hardware circuits corresponding to the C1 and C6 signals, so that the message is sent to the transponder, and the real-time accurate acquisition of the C4 signals is realized. Compared with the prior art, the invention can safely and effectively perform message receiving, message conversion, C6 signal and C1 signal transmission, and simultaneously can accurately detect the C4 signal in real time to judge the passing state of the train.

Description

C interface board circuit for ground electronic unit
Technical Field
The invention relates to the field of railway communication signals, in particular to a C interface board circuit for a ground electronic unit.
Background
The ground electronic unit (LEU) is a key device for transmitting variable messages in the transponder system, and forms a point type signal transmission system together with the ground transponder and the vehicle-mounted antenna, so that the trackside device and the vehicle-mounted device can transmit information at scattered points. The ground electronic unit (LEU) can generate or store data messages of not less than 256 kinds of change information according to the change of external control conditions; the system comprises the steps of modifying and updating the content of a data message stored in a ground electronic unit (LEU) through a station ground control center or an interlocking system; meanwhile, the requirement that the data message sent by a ground electronic unit (LEU) is kept unchanged when the train approaches to the ground active transponder is met.
The C interface board is an LEU and base connecting board and is responsible for converting digital message information into an analog signal and transmitting the analog signal to the base. The interface board refinement function definition interface is: the C1 interface is an LEU (Low-level Unit) for transmitting an Up-link message interface to the active transponder; the C4 interface is an interface for the active transponder to send train passing information to the LEU; the C6 interface provides a power interface for the LEU to the active transponder interface circuit.
The C1 interface is used for transmitting baseband signals, and the LEU carries out code pattern conversion on 1024-bit transponder transmission messages, converts the 1024-bit transponder transmission messages into DBPL codes and continuously transmits the DBPL codes to the active transponder through a cable. The LEU output end is connected with a 120Ω resistive load, and the signal amplitude Vpp is 14V-18V. The C6 interface provides power to the active beacon at a frequency of 8.82Khz with a Vpp of 20V-23V sine wave when the LEU is terminated with a 170 Ω resistive load. When the C4 signal appears, the load impedance is changed from 150 omega < Zia omega to Za <15 omega in the normal state, and the change-over time is 200< T <350uS and Td <150uS.
The C interface board plays a key role in LEU, and can accurately, safely and efficiently send ground data to an ATP system of a train through C1 signals and C6 signals, and meanwhile, can collect the generated C4 signals of the transponder as electric signals of the train passing through the transponder. Therefore, the design of the safe and efficient C interface board has important significance.
Disclosure of Invention
The present invention is directed to a C-interface board circuit for a ground electronics unit that overcomes the above-described deficiencies of the prior art.
The aim of the invention can be achieved by the following technical scheme:
the C interface board circuit for the ground electronic unit is characterized by comprising an FPGA logic processing unit, a C6 signal processing unit, a C4 signal processing unit and a C1 signal processing unit, wherein the FPGA logic processing unit is respectively connected with the C6 signal processing unit, the C4 signal processing unit and the C1 signal processing unit, and the C6 signal processing unit is connected with the C4 signal processing unit;
the FPGA logic processing unit converts the received message information into control signals corresponding to the hardware circuits corresponding to the C1 and C6 signals, so that the message is sent to the transponder, and the real-time accurate acquisition of the C4 signals is realized.
The C6 signal processing unit comprises a DDS chip, an I-V signal conversion circuit, an active amplifier and a transformer which are connected in sequence;
the DDS chip is used as an 8.82Khz sine wave signal generator to generate an I sine wave signal quantity, the I-V signal conversion circuit and the active amplifier are used for converting signals into V sine wave signal quantity, and finally the signals are input into the transformer to be coupled with C1 signals to be overlapped and output 8.82Khz energy carrier signals.
The DDS chip adopts an AD9851 chip.
The C1 signal processing unit comprises a C1_DBPL+ signal input end, a C1_DBPL-signal input end, a first switch tube combination circuit, a second switch tube combination circuit, a first constant current source, a second constant current source and a mutual inductor, wherein the C1_DBPL+ signal input end, the first switch tube combination circuit, the first constant current source and the mutual inductor are sequentially connected; and the C1_DBPL-signal input end, the second constant current source of the second switching tube combination circuit and the mutual inductor are sequentially connected.
The C4 signal processing unit comprises a primary end sampling resistor of the mutual inductance coil and a multipath comparison circuit, and the primary end sampling resistor of the mutual inductance coil, the multipath comparison circuit and the FPGA logic processing unit are sequentially connected;
c4 signals on the C interface line are collected through a sampling resistor at the primary end of the mutual inductance coil, and the occurrence of the C4 signals is detected through a level comparison mode of a multipath comparison circuit.
The multi-path comparison circuit adopts an LM2903D chip.
The FPGA logic processing unit comprises a C signal core processing module, a message transceiving module, a state quantity feedback module, a message analysis module, a C1 message RAM buffer area, a DBPL coding module, a C6 signal DDS configuration module, a stepping back signal preprocessing module and a C4 positive and negative code analysis module, wherein the C signal core processing module is respectively connected with the message transceiving module, the state quantity feedback module, the message analysis module, the C1 message RAM buffer area, the C6 signal DDS configuration module and the C4 positive and negative code analysis module, the C1 message RAM buffer area is connected with the C1 signal processing unit through the DBPL coding module, the C6 signal DDS configuration module is connected with the C6 signal processing unit, and the C4 positive and negative code analysis module is connected with the C4 signal processing unit through the stepping back signal preprocessing module.
The C1 message RAM buffer area is divided into an A area and a B area, the C signal core processing module and the DBPL coding module realize the occupation permission exchange through a control signal line, and the message error caused by repeated erasing and writing of the message in the reading process is avoided.
For the C1 signal, firstly, after being processed by a message analysis module, the message to be converted is stored in a corresponding 1-4 channel storage area of a C1 message RAM buffer area, and the DBPL coding module codes the message of the corresponding channel storage area and then gives a C1_DBPL+/C1_DBPL-signal control C1 signal processing unit.
For the C4 signal, according to the four-loop stepping signal quantity, the stepping-back signal preprocessing module is used for pre-judging whether the stepping-back C4 signal is in a short circuit, an open circuit and an abnormal state; if yes, changing the constant high or constant low of the positive and negative code state; if not, the C4 signal is normal, and the C4 positive and negative code analysis module is processed;
for the C6 signal, after the C interface board is electrified, the C6 signal DDS configuration module is automatically started to configure the external DDS chip AD 9851.
Compared with the prior art, the invention has the following advantages:
1) The autonomous design realizes a C interface board circuit in the LEU, and the structural solution of the FPGA system based on the Spartan 3E series is provided in the scheme.
2) According to the proposed system structure, each C signal processing module in the FPGA is designed autonomously.
3) In the implementation scheme, a part of C signal hardware implementation circuit is innovatively designed.
The invention realizes the message communication between the C interface board and the ALSTOM active beacon, can safely and effectively perform message receiving, message conversion and C signal transmission, and can accurately detect the C4 signal in real time to judge the passing state of the train. A message security conversion implementation scheme with feasibility and high efficiency is provided for the research and development of a C interface board in an LEU. Provides a new solution for the research and development of LEU in China, and enriches the innovation in the field of train control.
Drawings
FIG. 1 is a block diagram of a C interface board structure;
FIG. 2 is a schematic diagram of a C6 signal processing circuit;
FIG. 3 is a schematic diagram of a C1 signal processing circuit;
FIG. 4 is a schematic diagram of a C4 signal processing circuit;
fig. 5 is a schematic diagram of the internal structure of the FPGA.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The invention realizes a C interface board circuit in LEU according to SUBSET-036 European standard autonomous design, and provides a structural solution of a FPGA system based on Spartan 3E series and creatively designs a part of C signal hardware realization circuit.
The factor proposes to take an XC3S500E type FPGA as a core processing unit of a C interface board, and independently develops each signal processing module in the FPGA, and is mainly used for controlling a hardware circuit corresponding to C1 and C6 signals to convert received message information into analog signals and send the analog signals to a base, so that the real-time acquisition of C4 signals is realized, and the acquired signals are sent to an S interface board.
As shown in fig. 1, a C interface board circuit for a ground electronic unit includes an FPGA logic processing unit 1, a C6 signal processing unit 2, a C4 signal processing unit 3, and a C1 signal processing unit 4, where the FPGA logic processing unit is connected to the C6 signal processing unit, the C4 signal processing unit, and the C1 signal processing unit, and the C6 signal processing unit is connected to the C4 signal processing unit;
the FPGA logic processing unit gives corresponding control signals to the hardware circuits corresponding to the C1 and C6 signals, converts the received message information into analog signals, sends the analog signals to the transponder, and realizes real-time accurate acquisition of the C4 signals.
According to the invention, an XC3S500E type FPGA is used as a main logic processor, and through independently developing each signal processing module, message data receiving and transmitting are realized, the efficient coding of the four-channel DBPL of the C1 signal is realized, the configuration of the C6 signal module is realized, and the accurate acquisition of the C4 signal is realized.
As shown in fig. 2, the C6 signal processing unit 2 includes a DDS chip 21, an I-V signal conversion circuit 22, an active amplifier 23, and a transformer 24, which are sequentially connected;
the DDS chip is used as an 8.82Khz sine wave signal generator to generate an I sine wave signal quantity, the I-V signal conversion circuit and the active amplifier are used for converting signals into V sine wave signal quantity, and finally the signals are input into the transformer to be coupled with C1 signals to be overlapped and output 8.82Khz energy carrier signals. The DDS chip adopts an AD9851 chip.
As shown in fig. 3, the C1 signal processing unit 3 includes a c1_dbpl+ signal input end 31, a c1_dbpl-signal input end 32, a first switching tube combination circuit 33, a second switching tube combination circuit 34, a first constant current source 35, a second constant current source 36, and a transformer, where the c1_dbpl+ signal input end, the first switching tube combination circuit, the first constant current source, and the transformer are sequentially connected; and the C1_DBPL-signal input end, the second constant current source of the second switching tube combination circuit and the mutual inductor are sequentially connected.
And the C1 signal processing unit is used for directly receiving the C1_DBPL+/C1_DBPL-signal given by the FPGA and controlling the two MOS tubes and the mutual inductance coil to form a C1 signal generating module through the signal line driver. Firstly, a constant current source is constructed on two push-pull branches, and the primary terminal voltage of the mutual inductance coil is changed by changing the impedance value of the branches.
As shown in fig. 4, the C4 signal processing unit 4 includes a primary end sampling resistor 41 of the transformer coil and a multi-path comparison circuit 42, where the primary end sampling resistor 41 of the transformer coil, the multi-path comparison circuit 42 and the FPGA logic processing unit 1 are sequentially connected;
c4 signals (200 < T <350 uS) on the C interface line are collected through a primary end sampling resistor of the mutual inductance coil, and the occurrence of the C4 signals is detected through a level comparison mode of a multipath comparison circuit.
The multi-path comparison circuit adopts an LM2903D chip.
As shown in fig. 5, the FPGA logic processing unit 1 includes a C signal core processing module 11, a message transceiving module 12, a state quantity feedback module 13, a message parsing module 14, a C1 message RAM buffer area 15, a DBPL encoding module 16, a C6 signal DDS configuration module 17, a back stepping signal preprocessing module 18, and a C4 positive and negative code parsing module 19, where the C signal core processing module 1 is connected with the message transceiving module 12, the state quantity feedback module 13, the message parsing module 14, the C1 message RAM buffer area 15, the C6 signal DDS configuration module 17, and the C4 positive and negative code parsing module 19, the C1 message RAM buffer area 15 is connected with the C1 signal processing unit through the DBPL encoding module 16, the C6 signal DDS configuration module 17 is connected with the C6 signal processing unit, and the C4 positive and negative code parsing module 19 is connected with the C4 signal processing unit through the back stepping signal preprocessing module 18.
The FPGA processing unit independently develops and designs a control module of each processing unit. Two paths 232 of serial data receiving and transmitting interface modules are designed in the interior, one path is used for receiving messages, and the other path is used for sending back monitoring state quantity. The invention constructs a four-channel message conversion hardware structure in the FPGA, designs and realizes each internal C signal processing module, and realizes high-efficiency safe message conversion.
The C1 message RAM buffer area is divided into an A area and a B area, the C signal core processing module and the DBPL coding module realize the occupation permission exchange through a control signal line, and the message error caused by repeated erasing and writing of the message in the reading process is avoided.
For the C1 signal, firstly, after being processed by a message analysis module, the message to be converted is stored in a corresponding 1-4 channel storage area of a C1 message RAM buffer area, and the DBPL coding module codes the message of the corresponding channel storage area and then gives a C1_DBPL+/C1_DBPL-signal control C1 signal processing unit.
For the C4 signal, according to the four-loop stepping signal quantity, the stepping-back signal preprocessing module is used for pre-judging whether the stepping-back C4 signal is in a short circuit, an open circuit and an abnormal state; if yes, changing the constant high or constant low of the positive and negative code state; if not, the C4 signal is normal, and the C4 positive and negative code analysis module is processed;
for the C6 signal, after the C interface board is electrified, the C6 signal DDS configuration module is automatically started to configure the external DDS chip AD 9851.
The invention realizes the message communication between the C interface board and the ALSTOM active beacon, can safely and effectively perform message receiving, message conversion and C signal transmission, and can accurately detect the C4 signal in real time to judge the passing state of the train. A message security conversion implementation scheme with feasibility and high efficiency is provided for the research and development of a C interface board in an LEU. Provides a new solution for the research and development of LEU in China, and enriches the innovation in the field of train control.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.

Claims (9)

1. The C interface board circuit for the ground electronic unit is characterized by comprising an FPGA logic processing unit, a C6 signal processing unit, a C4 signal processing unit and a C1 signal processing unit, wherein the FPGA logic processing unit is respectively connected with the C6 signal processing unit, the C4 signal processing unit and the C1 signal processing unit, and the C6 signal processing unit is connected with the C4 signal processing unit;
the FPGA logic processing unit converts the received message information into control signals corresponding to the hardware circuits corresponding to the C1 and C6 signals, so that the message is sent to the transponder, and the real-time accurate acquisition of the C4 signals is realized;
the C6 signal processing unit comprises a DDS chip, an I-V signal conversion circuit, an active amplifier and a transformer which are connected in sequence;
the DDS chip is used as an 8.82Khz sine wave signal generator to generate an I sine wave signal quantity, the I-V signal conversion circuit and the active amplifier are used for converting signals into V sine wave signal quantity, and finally the signals are input into the transformer to be coupled with C1 signals to be overlapped and output 8.82Khz energy carrier signals.
2. The C interface board circuit for a ground electronics unit of claim 1, wherein the DDS chip is an AD9851 chip.
3. The C interface board circuit for a ground electronic unit according to claim 1, wherein the C1 signal processing unit includes a c1_dbpl+ signal input terminal, a c1_dbpl-signal input terminal, a first switching tube combination circuit, a second switching tube combination circuit, a first constant current source, a second constant current source, and a transformer, and the c1_dbpl+ signal input terminal, the first switching tube combination circuit, the first constant current source, and the transformer are sequentially connected; and the C1_DBPL-signal input end, the second constant current source of the second switching tube combination circuit and the mutual inductor are sequentially connected.
4. The C interface board circuit for the ground electronic unit according to claim 1, wherein the C4 signal processing unit comprises a primary end sampling resistor of the mutual inductance coil and a multi-path comparison circuit, and the primary end sampling resistor of the mutual inductance coil, the multi-path comparison circuit and the FPGA logic processing unit are sequentially connected;
c4 signals on the C interface line are collected through a sampling resistor at the primary end of the mutual inductance coil, and the occurrence of the C4 signals is detected through a level comparison mode of a multipath comparison circuit.
5. The C-interface board circuit for a terrestrial electronic unit of claim 4, wherein the multiple comparison circuit is an LM2903D chip.
6. The C interface board circuit for the ground electronic unit according to claim 1, wherein the FPGA logic processing unit comprises a C signal core processing module, a message receiving and transmitting module, a state quantity feedback module, a message analysis module, a C1 message RAM buffer area, a DBPL coding module, a C6 signal DDS configuration module, a stepping back signal preprocessing module and a C4 positive and negative code analysis module, wherein the C signal core processing module is respectively connected with the message receiving and transmitting module, the state quantity feedback module, the message analysis module, the C1 message RAM buffer area, the C6 signal DDS configuration module and the C4 positive and negative code analysis module, the C1 message RAM buffer area is connected with the C1 signal processing unit through the DBPL coding module, the C6 signal DDS configuration module is connected with the C6 signal processing unit, and the C4 positive and negative code analysis module is connected with the C4 signal processing unit through the stepping back signal preprocessing module.
7. The circuit of claim 6, wherein the buffer area of the C1 message RAM is divided into an a area and a B area, and the C signal core processing module and the DBPL encoding module implement the exchange of occupation authorities through control signal lines, so as to avoid errors of the message caused by repeated erasing and writing of the message in the reading process.
8. The C interface board circuit for a ground electronic unit according to claim 6, wherein for the C1 signal, after first being processed by the message parsing module, the message to be converted is stored in the corresponding 1-4 channel storage area of the C1 message RAM buffer area, and the DBPL encoding module encodes the corresponding channel storage area message to provide c1_dbpl+/c1_dbpl-signal control C1 signal processing unit.
9. The C interface board circuit for a ground electronic unit of claim 6, wherein for the C4 signal, the C4 signal is pre-determined by the back-stepping signal pre-processing module according to the four-circuit back-stepping signal amount whether it is a short circuit, an open circuit, and an abnormal state; if yes, changing the constant high or constant low of the positive and negative code state; if not, the C4 signal is normal, and the C4 positive and negative code analysis module is processed;
for the C6 signal, after the C interface board is electrified, the C6 signal DDS configuration module is automatically started to configure the external DDS chip AD 9851.
CN201710516969.8A 2017-06-29 2017-06-29 C interface board circuit for ground electronic unit Active CN107276768B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710516969.8A CN107276768B (en) 2017-06-29 2017-06-29 C interface board circuit for ground electronic unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710516969.8A CN107276768B (en) 2017-06-29 2017-06-29 C interface board circuit for ground electronic unit

Publications (2)

Publication Number Publication Date
CN107276768A CN107276768A (en) 2017-10-20
CN107276768B true CN107276768B (en) 2023-07-11

Family

ID=60070806

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710516969.8A Active CN107276768B (en) 2017-06-29 2017-06-29 C interface board circuit for ground electronic unit

Country Status (1)

Country Link
CN (1) CN107276768B (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107804345B (en) * 2017-10-26 2019-09-13 北京交大思诺科技股份有限公司 A kind of Ground Electronics Unit and its implementation that contact information is configurable
CN107942779B (en) * 2017-11-10 2020-10-23 北京全路通信信号研究设计院集团有限公司 LEU handles board
CN108674448B (en) * 2018-05-11 2020-06-09 北京交大思诺科技股份有限公司 Distributed shunting protection system
CN109634340B (en) * 2018-12-19 2023-10-13 卡斯柯信号有限公司 Voltage-controlled constant-current source output circuit
CN109884450B (en) * 2019-03-19 2024-04-16 卡斯柯信号有限公司 Device and method for detecting cable state of transponder
CN110336646B (en) * 2019-07-26 2023-06-06 卡斯柯信号有限公司 DBPL code stoping equipment and method suitable for LEU
CN110928274B (en) * 2019-12-09 2021-03-02 通号(北京)轨道工业集团有限公司轨道交通技术研究院 Test system of LEU equipment
CN112653690B (en) * 2020-12-18 2022-07-26 卡斯柯信号有限公司 Analog demodulation circuit for acquiring message by C interface of ground electronic unit

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103475311A (en) * 2013-09-03 2013-12-25 周健 Special circuit for signal generation in TDLAS (Tunable Diode Laser Absorption Spectroscopy)
WO2017016178A1 (en) * 2015-07-29 2017-02-02 国核自仪系统工程有限公司 Interface signal remapping method based on fpga
CN106560372A (en) * 2016-07-22 2017-04-12 卡斯柯信号有限公司 Obturation mode adaptive control system based on vehicle controller

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITTO20040325A1 (en) * 2004-05-14 2004-08-14 Ansaldo Segnalamento Ferroviario Spa DEVICE FOR THE SAFE TRANSMISSION OF DATA TO BOE FOR RAILWAY SIGNALING
CN102857366B (en) * 2012-06-08 2015-02-18 北京和利时系统工程有限公司 Trackside electronic device for transparent transmission of information of high-speed railway responder

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103475311A (en) * 2013-09-03 2013-12-25 周健 Special circuit for signal generation in TDLAS (Tunable Diode Laser Absorption Spectroscopy)
WO2017016178A1 (en) * 2015-07-29 2017-02-02 国核自仪系统工程有限公司 Interface signal remapping method based on fpga
CN106560372A (en) * 2016-07-22 2017-04-12 卡斯柯信号有限公司 Obturation mode adaptive control system based on vehicle controller

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
The Study on train separation control & safety braking model technology using balise for conventional lines;J. -h. Baek;INTELEC 2009 - 31st International Telecommunications Energy Conference, Incheon, Korea (South), 2009;1-4 *
一种高精度可调相差的多路正弦信号源设计;屈环宇;屈百达;;单片机与嵌入式系统应用(09);全文 *

Also Published As

Publication number Publication date
CN107276768A (en) 2017-10-20

Similar Documents

Publication Publication Date Title
CN107276768B (en) C interface board circuit for ground electronic unit
CN101442335B (en) Responder
US20150380973A1 (en) RF Energy Harvesting by a Network Node
JP2016519555A5 (en)
CN201323574Y (en) Responder
CN111245093B (en) Medium voltage line-variable relation identification method and system
WO2015032054A1 (en) Sensor, telemeter, remote sensor system, and use method therefor
CN213072674U (en) Testing arrangement of transponder C interface
CN114759975A (en) Electric energy data acquisition method and system based on Beidou satellite communication
CN112350783A (en) Testing arrangement of transponder C interface
CN108540228A (en) Relay transmission system based on FSO/RF links and energy control method
Ndukwe et al. LoRa-based communication system for data transfer in microgrids
CN108629959B (en) Remote control underwater acoustic communication system and unmanned underwater vehicle
CN106230495B (en) A kind of ADS-B earth station having TIS-B function
CN112485808A (en) GNSS positioning system, positioning method and positioning equipment based on LoRa communication
CN103545101A (en) Intelligent electronic current transformer
CN105931447A (en) Downlink communication system of low-voltage power meter reading system and meter reading method
CN207022017U (en) C interface plate circuit for LEU
CN208638324U (en) Coding-control box and solar energy system
CN107332515B (en) DDS-based C6 signal generation device for LEU
CN205178487U (en) Intelligence residual current circuit breaker controlling means
CN204925315U (en) Carry out device of monitoring to joining in marriage power system fault
CN207135070U (en) Based on DDS LEU C6 signal generation devices
CN219305045U (en) Remote debugging equipment and system for vehicle and vehicle
CN217282364U (en) Line becomes detection device and distribution system of relation

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
REG Reference to a national code

Ref country code: HK

Ref legal event code: DE

Ref document number: 1243568

Country of ref document: HK

GR01 Patent grant
GR01 Patent grant