CN102280481A - Laterally double diffused metal oxide semiconductor device and manufacturing method thereof - Google Patents
Laterally double diffused metal oxide semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102280481A CN102280481A CN201110218604XA CN201110218604A CN102280481A CN 102280481 A CN102280481 A CN 102280481A CN 201110218604X A CN201110218604X A CN 201110218604XA CN 201110218604 A CN201110218604 A CN 201110218604A CN 102280481 A CN102280481 A CN 102280481A
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Abstract
The invention provides a laterally double diffused metal oxide semiconductor device and a manufacturing method thereof. According to the invention, the laterally double diffused metal oxide semiconductor device comprises: a first P trap, which is arranged in a substrate; a source area, which is arranged in the first P trap; an N type drift region, which is arranged in the first P trap; an N trap, which is arranged in the N type drift region; and a drain electrode area, which is arranged in the N trap. According to the invention, the drain electrode area is arranged in the N trap in the N type drift region rather than direct arrangement of the drain electrode area in the N type drift region, so that on resistance is reduced and an SOA working range is enlarged on the condition that a breakdown voltage is not influenced.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly, the present invention relates to a kind of lateral double-diffused metal-oxide semiconductor device and manufacture method thereof.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS) device is a kind of semiconductor device well known in the art.The LDMOS device is for quite being similar to a kind of FET device of conventional field effect transistor (FET) device.The same with the conventional field effect transistor device, the LDMOS device is included in and forms a pair of source/drain region of being separated by channel region in the Semiconductor substrate, and forms gate electrode in the channel region top successively.
Yet, the LDMOS device part different with traditional F ET device is, pair of source territory in traditional FET device is made with gate electrode symmetrical, and the drain region in the LDMOS device forms further from gate electrode than the source region, and the drain region is formed at simultaneously in order in the dopant well (having and the drain region identical polar) of separating channel region and drain region.The LDMOS device is a kind of power metal oxide semiconductor field-effect transistor (MOSFET) of asymmetry basically, and it has coplanar drain electrode and source region, utilizes double diffusion technique to make.At present, LDMOS is widely adopted with the CMOS process compatible owing to easier.
Fig. 1 schematically shows the structure according to the lateral double-diffused metal-oxide semiconductor device of prior art.Lateral double-diffused metal-oxide semiconductor device according to prior art comprises: be arranged in a P trap hvpw in the substrate, be arranged in source region S in the described P trap, be arranged in N type drift region ndf among the described P trap hvpw, be arranged in the drain region D among the described N type drift region ndf.In addition, this lateral double-diffused metal-oxide semiconductor device also comprises the grid G between drain region D and source region S, and described grid G is positioned at the silicon chip top.Wherein, shallow trench isolation is in order to improve the puncture voltage of device from the purpose of (STI).Simultaneously, owing to have the drift region ndf of shallow doping to exist between raceway groove and the drain region D, and the drift region of shallow doping is darker than STI, therefore can not have the connection of blocking-up raceway groove and drain electrode.
In the prior art, the relation of utilizing puncture voltage and the size L of shallow channel isolation area STI1 on channel direction to be directly proportional can utilize same technology to make different puncture voltages and the satisfactory device of electrical parameter.Concerning a device of optimizing fully, when size L was short, puncture voltage was lower, conducting resistance is low, needs the doping content of drift region ndf of shallow doping higher simultaneously, and vice versa, and (L is long, the puncture voltage height, the conducting resistance height, drift region ndf concentration is low).Like this, make the variable voltage device if adopt same technology, so just can only optimize a wherein end, such as optimizing high voltage one end, such drift region ndf concentration concerning the voltage devices of an optimization, seemed lower, this i-v curve from device comes as can be seen, as shown in Figure 2.Fig. 2 schematically shows according to the drain voltage of the lateral double-diffused metal-oxide semiconductor device of prior art and leakage current contrast properties figure.
Summary of the invention
An object of the present invention is to provide to increase at drain voltage and still keep drain voltage and drain current lateral double-diffused metal-oxide semiconductor device and manufacture method thereof effectively in the linear relationship of working region.
According to a first aspect of the invention, a kind of lateral double-diffused metal-oxide semiconductor device is provided, and it comprises: be arranged in a P trap in the substrate, be arranged in source region in the described P trap, be arranged in N type drift region in the described P trap, be arranged in the N trap in the described N type drift region and be arranged in drain region in the described N trap.
Preferably, in above-mentioned lateral double-diffused metal-oxide semiconductor device, the doping content of described N trap is greater than the doping content of described N type drift region.
Preferably, in above-mentioned lateral double-diffused metal-oxide semiconductor device, the doping content of described N trap is less than the doping content of described drain region.
Preferably, in above-mentioned lateral double-diffused metal-oxide semiconductor device, described source region is arranged in the 2nd P trap in the described P trap, and the doping content of described the 2nd P trap is greater than the doping content of a described P trap.
Preferably, in above-mentioned lateral double-diffused metal-oxide semiconductor device, the side away from grid of described source region is furnished with P type tagma, and the doping content in described P type tagma is greater than the doping content of a described P trap.
According to a first aspect of the invention, by the drain region being arranged in the N trap in the N type drift region, rather than directly be arranged in the N type drift region, make along with zone the size on channel direction of drain region near grid one side do not change, N type doping content in the N type drift region is still enough (that is, not influencing puncture voltage) for the width of N type drift region thus; Reduced conducting resistance by the N trap that increases in the N type drift region, the relation between drain voltage and the leakage current that makes thus still remains the relation of approximately linear along with the increase of drain voltage, thereby has kept the service behaviour of lateral double-diffused metal-oxide semiconductor device.
According to a second aspect of the invention, provide a kind of lateral double-diffused metal-oxide semiconductor device manufacture method, it comprises: form a P trap in substrate; In a described P trap, form the source region;
In a described P trap, form N type drift region; In described N type drift region, form the N trap; And in described N trap, form the drain region.
Preferably, in above-mentioned lateral double-diffused metal-oxide semiconductor device manufacture method, the doping content of described N trap is greater than the doping content of described N type drift region.
Preferably, in above-mentioned lateral double-diffused metal-oxide semiconductor device manufacture method, the doping content of described N trap is less than the doping content of described drain region.
Preferably, above-mentioned lateral double-diffused metal-oxide semiconductor device manufacture method also is included in the step that forms the 2nd P trap in the described P trap, thereby described source region is arranged in the 2nd P trap in the described P trap, and the doping content of described the 2nd P trap is greater than the doping content of a described P trap.
Preferably, above-mentioned lateral double-diffused metal-oxide semiconductor device manufacture method also is included in the step of arranging P type tagma away from a side of grid of described source region, and the doping content in described P type tagma is greater than the doping content of a described P trap.
According to a second aspect of the invention, similarly, by the drain region being arranged in the N trap in the N type drift region, rather than directly be arranged in the N type drift region, make along with zone the size on channel direction of drain region near grid one side do not change, N type doping content in the N type drift region is still enough (that is, not influencing puncture voltage) for the width of N type drift region thus; Reduced conducting resistance by the N trap that increases in the N type drift region, the relation between drain voltage and the leakage current that makes thus still remains the relation of approximately linear along with the increase of drain voltage, thereby has kept the service behaviour of lateral double-diffused metal-oxide semiconductor device.
Promptly, method has according to a second aspect of the invention increased doping process one, this road doping process (does not influence puncture voltage substantially to the device influence of high voltage one end is little, and conducting resistance can be improved), but concerning the device of low-voltage one end, puncture voltage has reduction slightly, and i-v curve is greatly improved but conducting resistance is greatly improved simultaneously, helps to improve device reliability and enlarges the SOA working range.
Description of drawings
In conjunction with the accompanying drawings, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and feature the present invention by with reference to following detailed, wherein:
Fig. 1 schematically shows the structure according to the lateral double-diffused metal-oxide semiconductor device of prior art.
Fig. 2 schematically shows according to the drain voltage of the lateral double-diffused metal-oxide semiconductor device of prior art and leakage current contrast properties figure.
Fig. 3 schematically shows the structure according to the lateral double-diffused metal-oxide semiconductor device of the embodiment of the invention.
Fig. 4 schematically shows according to the drain voltage of the lateral double-diffused metal-oxide semiconductor device of the embodiment of the invention and leakage current contrast properties figure.
Fig. 5 schematically shows the flow chart according to the lateral double-diffused metal-oxide semiconductor device manufacture method of the embodiment of the invention.
Need to prove that accompanying drawing is used to illustrate the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure may not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear and understandable more, content of the present invention is described in detail below in conjunction with specific embodiments and the drawings.
Fig. 3 schematically shows the structure according to the lateral double-diffused metal-oxide semiconductor device of the embodiment of the invention.As shown in Figure 3, the lateral double-diffused metal-oxide semiconductor device according to the embodiment of the invention comprises: be arranged in a P trap hvpw in the substrate, be arranged in source region S in the described P trap, be arranged in N type drift region ndf among the described P trap hvpw, be arranged in the N trap NW among the described N type drift region ndf and be arranged in drain region D among the described N trap NW.In addition, also comprise grid G between drain region D and source region S according to the lateral double-diffused metal-oxide semiconductor device of the embodiment of the invention, described grid G is positioned at the silicon chip top.
Wherein, a described P trap hvpw for example is the high pressure P trap.
And the doping content of wherein said N trap NW is greater than the doping content of described N type drift region, and the doping content of described N trap is less than the doping content of described drain region.
Preferably, as shown in Figure 3, described source region S is arranged among the 2nd P trap ptub among the described P trap hvpw, and the doping content of described the 2nd P trap ptub is greater than the doping content of a described P trap hvpw.
In addition, preferably, the side away from grid G of described source region S is furnished with P type tagma B, and the doping content of described P type tagma B is greater than the doping content of a described P trap hvpw.And preferably, drain region D is furnished with the first shallow channel isolation area STI1 and the second shallow channel isolation area STI2 respectively, to isolate relevant zone.The purpose of arranging shallow channel isolation area (STI) is in order to improve the puncture voltage of device, and owing to there is the drift region of shallow doping to exist between raceway groove and the drain region D, and the drift region of shallow doping is darker than shallow channel isolation area, therefore can not have the connection of blocking-up raceway groove and drain electrode.
Fig. 4 schematically shows according to the drain voltage VD of the lateral double-diffused metal-oxide semiconductor device of the embodiment of the invention and leakage current ID contrast properties figure.From the contrast of Fig. 4 and Fig. 2 as can be known, compare with the lateral double diffusion metal oxide semiconductor device performance of prior art, by the lateral double-diffused metal-oxide semiconductor device according to the embodiment of the invention being carried out emulation and test is found, still can keep the linear character of drain voltage VD and leakage current ID preferably when increasing (in the working region) gradually at drain voltage according to the lateral double-diffused metal-oxide semiconductor device of the embodiment of the invention.
Promptly, by drain region S being arranged among the N trap NW among the N type drift region ndf, rather than directly be arranged among the N type drift region ndf, make along with zone the size L on channel direction of drain region near grid one side do not change, N type doping content in the N type drift region is still enough (that is, not influencing puncture voltage) for the width of N type drift region thus; Reduced conducting resistance by the N trap NW that increases in the N type drift region, the relation between drain voltage and the leakage current that makes thus still remains the relation of approximately linear along with the increase of drain voltage, thereby has kept the service behaviour of lateral double-diffused metal-oxide semiconductor device.
Fig. 5 schematically shows the flow chart according to the lateral double-diffused metal-oxide semiconductor device manufacture method of the embodiment of the invention.As shown in Figure 5, the lateral double-diffused metal-oxide semiconductor device manufacture method according to the embodiment of the invention can comprise the steps:
At first in substrate, form a P trap (step S1).
Can in a described P trap, form the 2nd P trap (step S2) subsequently; After this in the 2nd P trap, form source region (step S3),
And, after step S1, can in a described P trap, form N type drift region (step S4); And form N trap NW (step S5) then in described N type drift region, the doping content of wherein said N trap NW is greater than the doping content of described N type drift region.
After step S5, can in described N trap NW, form drain region (step S6), the doping content of described N trap NW is less than the doping content of described drain region.
Equally preferably, said method can also be included in the step of arranging P type tagma away from a side of grid of described source region, and the doping content in described P type tagma is greater than the doping content of a described P trap.
Promptly, above-mentioned technology has increased by one doping process to form N trap NW with respect to prior art, this road doping process (does not influence puncture voltage substantially to the device influence of high voltage one end is little, and conducting resistance can be improved), but concerning the device of low-voltage one end, puncture voltage has reduction (2-3V slightly, reduce by 8%), but conducting resistance is greatly improved (reducing by 25%), i-v curve is greatly improved simultaneously, helps to improve device reliability and enlarges the SOA working range.
Any those of ordinary skill in the art are understandable that, though described manufacture method of the present invention with step S1 to the order of step S6, for the manufacturing sequence of source electrode in the substrate and drain electrode, do not need to do concrete qualification; Thereby the sequencing of the manufacturing of source electrode and drain electrode does not cause qualification to manufacture method of the present invention.
Be understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (10)
1. lateral double-diffused metal-oxide semiconductor device is characterized in that comprising: be arranged in a P trap in the substrate, be arranged in source region in the described P trap, be arranged in N type drift region in the described P trap, be arranged in the N trap in the described N type drift region and be arranged in drain region in the described N trap.
2. lateral double-diffused metal-oxide semiconductor device according to claim 1 is characterized in that, the doping content of described N trap is greater than the doping content of described N type drift region.
3. lateral double-diffused metal-oxide semiconductor device according to claim 1 and 2 is characterized in that the doping content of described N trap is less than the doping content of described drain region.
4. lateral double-diffused metal-oxide semiconductor device according to claim 1 and 2, it is characterized in that, described source region is arranged in the 2nd P trap in the described P trap, and the doping content of described the 2nd P trap is greater than the doping content of a described P trap.
5. lateral double-diffused metal-oxide semiconductor device according to claim 1 and 2, it is characterized in that, side away from grid of described source region is furnished with P type tagma, and the doping content in described P type tagma is greater than the doping content of a described P trap.
6. lateral double-diffused metal-oxide semiconductor device manufacture method is characterized in that comprising:
In substrate, form a P trap;
In a described P trap, form the source region;
In a described P trap, form N type drift region;
In described N type drift region, form the N trap; And
In described N trap, form the drain region.
7. lateral double-diffused metal-oxide semiconductor device manufacture method according to claim 6 is characterized in that, the doping content of described N trap is greater than the doping content of described N type drift region.
8. according to claim 6 or 7 described lateral double-diffused metal-oxide semiconductor device manufacture methods, it is characterized in that the doping content of described N trap is less than the doping content of described drain region.
9. lateral double-diffused metal-oxide semiconductor device manufacture method according to claim 6, it is characterized in that also being included in the step that forms the 2nd P trap in the described P trap, thereby described source region is arranged in the 2nd P trap in the described P trap, and the doping content of described the 2nd P trap is greater than the doping content of a described P trap.
10. lateral double-diffused metal-oxide semiconductor device manufacture method according to claim 6, it is characterized in that also being included in the step of arranging P type tagma away from a side of grid of described source region, and the doping content in described P type tagma is greater than the doping content of a described P trap.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077895A (en) * | 2012-12-19 | 2013-05-01 | 上海宏力半导体制造有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof |
| CN106033775A (en) * | 2014-09-01 | 2016-10-19 | 爱思开海力士有限公司 | Power integrated devices, electronic devices and electronic systems including the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088031A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof |
| KR20110078861A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Lateral double diffused metal oxide semiconductor |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102088031A (en) * | 2009-12-03 | 2011-06-08 | 无锡华润上华半导体有限公司 | N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof |
| KR20110078861A (en) * | 2009-12-31 | 2011-07-07 | 주식회사 동부하이텍 | Lateral double diffused metal oxide semiconductor |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103077895A (en) * | 2012-12-19 | 2013-05-01 | 上海宏力半导体制造有限公司 | Laterally diffused metal oxide semiconductor (LDMOS) transistor and formation method thereof |
| CN106033775A (en) * | 2014-09-01 | 2016-10-19 | 爱思开海力士有限公司 | Power integrated devices, electronic devices and electronic systems including the same |
| CN106033775B (en) * | 2014-09-01 | 2020-09-11 | 爱思开海力士系统集成电路有限公司 | Power integrated device, electronic device including the same, and electronic system |
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