CN102280443B - Structure of array substrate and manufacturing method thereof - Google Patents
Structure of array substrate and manufacturing method thereof Download PDFInfo
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- CN102280443B CN102280443B CN201010200177.8A CN201010200177A CN102280443B CN 102280443 B CN102280443 B CN 102280443B CN 201010200177 A CN201010200177 A CN 201010200177A CN 102280443 B CN102280443 B CN 102280443B
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Abstract
The invention discloses a structure of an array substrate and a manufacturing method thereof, and relates to the technical field of display. The invention aims to solve the problem that the distance between a pixel electrode and a common electrode in a storage capacity (CS) is long so abnormal gray scale is caused by change of the voltage at two ends of liquid crystals in a liquid crystal panel due to failure of retention of the constant voltage for controlling liquid crystal diversion under the condition that the CS is charged is solved. The array substrate comprises a substrate, and a grid scanning line, a data scanning line, a pixel electrode and a first thin film transistor which are formed on the substrate, wherein a grid of the first thin film transistor is connected with the grid scanning line, a source of the first thin film transistor is connected with the data scanning line, and a drain of the first thin film transistor is connected with the pixel electrode; the array substrate also comprises the storage capacitor; and a bottom electrode of the storage capacitor and the data scanning line are positioned in the same plane; and a top electrode of the storage capacitor and the pixel electrode are positioned in the same plane. The embodiment of the invention is mainly applied in the display field, and is particularly suitable for liquid crystal display panels.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to a kind of structure and manufacture method of array base palte.
Background technology
Utilize thin-film transistor to produce the display that voltage turns to control liquid crystal, be called Thin Film Transistor-LCD (TFT LCD).Thin Film Transistor-LCD comprises liquid crystal panel, and the plane-parallel capacitor that clipped Formation of liquid crystals between layer glass up and down of liquid crystal panel, is referred to as C
lC(capacitor of liquid crystal), its size is about 0.1pF.Described C
lCfor the voltage of retentive control liquid crystal transition, but in the time of practical application, at thin-film transistor TFT to C
lCafter charged to TFT next time again to C
lCcharge in the time period, C
lCvoltage cannot be maintained, voltage is changed, cause shown GTG incorrect.
General modal storage capacitors Cs (storage capacitor) framework has two kinds, respectively these two kinds of Cs on gate and Cs on common. just can know as its name suggests for these two kinds, its main difference is just that storage capacitors is utilized gate cabling or common cabling completes.Wherein, this C
son commonpass through pixel electrode and common electrode form, between described pixel electrode and public electrode, clip gate insulator and passivation layer.
Realizing in process of the present invention, inventor finds, C
sthe C of this framework of on common
sin electric capacity, between pixel electrode and public electrode, distance is larger, at C
s, there is because liquid crystal both end voltage changes the GTG abnormal problem causing liquid crystal panel in the voltage constant can not retentive control liquid crystal in charged situation turning to.
Summary of the invention
Embodiments of the invention provide a kind of structure and manufacture method of array base palte, have solved C
sin electric capacity, between pixel electrode and public electrode, distance is larger, at C
s, there is because liquid crystal both end voltage changes the GTG abnormal problem causing liquid crystal panel in the voltage constant can not retentive control liquid crystal in charged situation turning to.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprise substrate, and the controlling grid scan line forming on substrate, data scanning line, pixel electrode and the first film transistor, the transistorized grid of this first film is connected with controlling grid scan line, the transistorized source electrode of this first film is connected with data scanning line, the transistorized drain electrode of this first film is connected with pixel electrode; Also comprise storage capacitance, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, and the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect.
Concrete, the top electrode of described storage capacitance is described pixel electrode, and the hearth electrode of described storage capacitance is corresponding to the edge of the latter half of described pixel electrode, and the hearth electrode of described storage capacitance is connected to constant voltage source.
The concrete connected mode that the hearth electrode of described storage capacitance is connected to constant voltage source is: described hearth electrode is connected on peripheral public electrode power supply by the via hole of described hearth electrode top.
Further, in order to optimize C
scapacitance time increase the aperture opening ratio of pixel, the hearth electrode of described storage capacitance is the transistorized drain electrode of the first film, the top electrode of described storage capacitance is corresponding to the transistorized drain electrode of described the first film, and the top electrode of described storage capacitance is independent of described pixel electrode and described top electrode is connected to constant voltage source.
The concrete connected mode that described top electrode is connected to constant voltage source is: the lead-in wire that described top electrode is provided with by this top electrode is connected with external voltage input.
Further, for fear of when the top electrode of described storage capacitance is connected the outside constant voltage of introducing by lead-in wire with external voltage input, the larger problem of voltage noise that described outside constant voltage source provides to described storage capacitance, reaches and is optimizing C
scapacitance, reduce described storage capacitance when increasing the aperture opening ratio of pixel and introduce the noise object of external voltage, on described array base palte, be also formed with the second thin-film transistor, the grid of described the second thin-film transistor is connected with described controlling grid scan line; The source electrode of described the second thin-film transistor is connected with described controlling grid scan line; The concrete connected mode that described top electrode is connected to constant voltage source is: described top electrode is connected with the drain electrode of described the second thin-film transistor.
Optionally, described the second thin-film transistor is positioned at the top of described controlling grid scan line, the part that the grid of described the second thin-film transistor is described controlling grid scan line.
Described top electrode is connected concrete connected mode with the drain electrode of described the second thin-film transistor: described top electrode connects by the via hole of the drain electrode top of described the second thin-film transistor.
The source electrode of described the second thin-film transistor is connected concrete connected mode with described controlling grid scan line: the source electrode top of described the second thin-film transistor is formed with via hole; Described controlling grid scan line top is formed with via hole; Connecting electrode couples together the source electrode of described the second thin-film transistor and described controlling grid scan line by the via hole of the source electrode top of described the second thin-film transistor and the via hole of described controlling grid scan line top.
A kind of manufacture method of array base palte, comprise: on the substrate with gate pattern and insulating barrier, form the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance by composition technique, the hearth electrode of described storage capacitance and described data scanning line are positioned at same layer; On described substrate, deposit one deck passivation layer, form via hole by mask composition technique; On described substrate, deposit layer of transparent conductive film, form pixel electrode and storage capacitance top electrode by mask composition technique, wherein pixel electrode is connected with drain electrode by the via hole of described drain electrode top, and described via hole is positioned at the top of described drain electrode.
Concrete, on the described substrate thering is gate pattern and insulating barrier, form the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance by composition technique, comprising:
On the substrate with gate pattern and insulating barrier, deposit active layer film, form active layer pattern by mask composition technique;
Depositing metal films on the substrate with gate pattern, insulating barrier and active layer pattern, by the hearth electrode of mask composition technique formation data scanning line, source electrode, drain electrode and storage capacitance;
Described one deck passivation layer that deposits on described substrate, forms via hole by mask composition technique, comprising:
On described substrate, deposit one deck passivation layer, above the two ends corresponding to described hearth electrode, forming via hole and form via hole above described drain electrode by mask composition technique;
The described layer of transparent conductive film that deposits on described substrate, forms pixel electrode and storage capacitance top electrode by mask composition technique, comprising:
On described substrate, deposit layer of transparent conductive film, form pixel electrode by mask composition technique, the pixel electrode that is wherein positioned at hearth electrode top forms the top electrode of storage capacitance.
Further, in order to optimize C
scapacitance time increase the aperture opening ratio of pixel, on the described substrate thering is gate pattern and insulating barrier, form the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance by composition technique, comprising:
On the substrate with gate pattern and insulating barrier, deposit active layer film and metallic film, form active layer pattern, data scanning line, source electrode and drain electrode by gray tone or halftoning composition technique, described drain electrode is simultaneously also as the hearth electrode of storage capacitance;
The described layer of transparent conductive film that deposits on described substrate, forms pixel electrode and storage capacitance top electrode by mask composition technique, comprising:
On described substrate, deposit layer of transparent conductive film, form the top electrode of pixel electrode and storage capacitance by mask composition technique, the top electrode of described storage capacitance is independent of described pixel electrode.
And described method, also comprises:
On the top electrode of described storage capacitance, be formed with for the lead-in wire that is connected with described external voltage input.
Further, for fear of when the top electrode of described storage capacitance is connected the outside constant voltage of introducing by lead-in wire with external voltage input, the larger problem of voltage noise that described outside constant voltage source provides to described storage capacitance, reaches and is optimizing C
scapacitance, reduce described storage capacitance when increasing the aperture opening ratio of pixel and introduce the noise object of external voltage, the hearth electrode that forms active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the described substrate having gate pattern and insulating barrier by composition technique, comprising:
On the substrate with gate pattern and insulating barrier, deposit active layer film, above the grid of gate pattern, form the first active layer by mask composition technique, above the controlling grid scan line of described gate pattern, form the second active layer, described the first active layer and described the second active layer form active layer pattern;
Depositing metal films on the substrate with gate pattern, insulating barrier and active layer pattern, form data scanning line, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode by mask composition technique, described the first drain electrode is simultaneously also as storage capacitance hearth electrode;
Described one deck passivation layer that deposits on described substrate, forms via hole by mask composition technique, comprising:
On described substrate, deposit one deck passivation layer, form the via hole of the first drain electrode top, via hole, the via hole of the second source electrode top and the via hole of controlling grid scan line top of the second drain electrode top by mask composition technique;
The described layer of transparent conductive film that deposits on described substrate, forms pixel electrode and storage capacitance top electrode by mask composition technique, and wherein pixel electrode is connected with drain electrode by described via hole, comprising:
On described substrate, deposit layer of transparent conductive film, form top electrode and the connecting electrode of pixel electrode, storage capacitance by mask composition technique, the top electrode of described storage capacitance is connected with described the second drain electrode by the via hole of the second drain electrode top corresponding to the top electrode of described the first drain electrode and described storage capacitance; Described connecting electrode is connected the second source electrode with the via hole of controlling grid scan line top by the via hole of the second source electrode top with controlling grid scan line.
The structure of the array base palte that the embodiment of the present invention provides and manufacture method, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the thickness that distance between hearth electrode and the top electrode of this storage capacitance is passivation layer, the distance of top crown and described bottom crown is reduced, optimize the capacitance of storage capacitance, solved due to the C on array base palte in prior art
spixel electrode and storage capacitance hearth electrode between distance larger, cause C
scapacitance less and have a fluctuation, C
svoltage can not constantly remain to the problem of next time upgrading picture.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The vertical view of the array base palte that Fig. 1 provides for the embodiment of the present invention;
The vertical view one of the array base palte that Fig. 2 provides for further embodiment of this invention;
The vertical view two of the array base palte that Fig. 3 provides for further embodiment of this invention;
The A-A cutaway view of the array base palte that Fig. 4 provides for the embodiment of the present invention shown in Fig. 3;
The manufacture method flow chart of the array base palte that Fig. 5 provides for the embodiment of the present invention;
The manufacture method flow chart of the array base palte that Fig. 6 provides for further embodiment of this invention;
The manufacture method flow chart of the array base palte that Fig. 7 provides for another embodiment of the present invention;
The manufacture method flow chart of the array base palte that Fig. 8 provides for yet another embodiment of the invention.
Mark in figure: 1-substrate; 2-controlling grid scan line; 3-data scanning line; 4-pixel electrode; 5, the first film transistor; 51-grid; 52-source electrode; 53-drain electrode; 6-storage capacitance; 61-hearth electrode; 62-top electrode; 7-lead-in wire; 8-the second thin-film transistor; 82-drain electrode; 83-source electrode; 9-connecting electrode.
Embodiment
The embodiment of the present invention provides a kind of structure and manufacture method of array base palte, has solved C
sin electric capacity, between pixel electrode and public electrode, distance is larger, at C
s, there is because liquid crystal both end voltage changes the GTG abnormal problem causing liquid crystal panel in the voltage constant can not retentive control liquid crystal in charged situation turning to.
As shown in Figure 1, the array base palte that the embodiment of the present invention provides, comprise substrate 1, and the controlling grid scan line 2, data scanning line 3, pixel electrode 4 and the first film transistor 5 that on substrate 1, form, the grid 51 of this first film transistor 5 is connected with controlling grid scan line 2, source electrode 52 and data scanning line 3 are connected, drain 53 is connected with pixel electrode 4; Also comprise storage capacitance 6, hearth electrode 61 and the described data scanning line 3 of described storage capacitance 6 are positioned at same aspect, and the top electrode of described storage capacitance 6 and described pixel electrode 4 are positioned at same aspect.
In the time of concrete utilization, the top electrode of described storage capacitance 6 is pixel electrode 4, the hearth electrode 61 of described storage capacitance is parallel to described controlling grid scan line 2 corresponding with the edge of the latter half of described pixel electrode 4, and the hearth electrode 61 of described storage capacitance is connected to constant voltage source, in Fig. 1, do not provide concrete connected mode, for example, hearth electrode 61 can be connected on peripheral public electrode power supply by the via hole of hearth electrode 61 tops, the top at the two ends of described hearth electrode 61 is provided with via hole, between multiple hearth electrodes 61, can interconnect by connecting line, choosing one of them hearth electrode 61 is connected on peripheral public electrode power supply by the via hole on described hearth electrode 61.
The structure of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the thickness that distance between hearth electrode and the top electrode of this storage capacitance is passivation layer, the distance of top crown and described bottom crown is reduced, optimize the capacitance of storage capacitance, solved the C on array base palte in prior art
spixel electrode and storage capacitance hearth electrode between distance larger, cause C
scapacitance less and have a fluctuation, C
svoltage can not constantly remain to the problem of next time upgrading picture.
As shown in Figure 2, the structure of the array base palte that further embodiment of this invention provides, comprise substrate 1, and the controlling grid scan line 2, data scanning line 3, pixel electrode 4 and the first film transistor 5 that on substrate 1, form, the grid 51 of this first film transistor 5 is connected with controlling grid scan line 2, source electrode 52 and data scanning line 3 are connected, drain 53 is connected with pixel electrode 4; Also comprise storage capacitance 6, the hearth electrode of described storage capacitance 6 and described data scanning line 3 are positioned at same aspect, the hearth electrode of described storage capacitance 6 is the drain electrode 53 of described the first film transistor 5, and top electrode 62 and the described pixel electrode 4 of described storage capacitance 6 are positioned at same aspect.The top electrode 62 of described storage capacitance is corresponding to the drain electrode 53 of described the first film transistor 5, and the top electrode 62 of described storage capacitance is independent of described pixel electrode 4 and described top electrode 62 is connected to constant voltage source.
When concrete application, the concrete connected mode that described top electrode 62 is connected to constant voltage source is:
The lead-in wire 7 that described top electrode 62 is provided with by this top electrode 62 is connected with external voltage input.External voltage described herein can be provided by pcb board.
In the present embodiment, described storage capacitance 6 is by the drain electrode 53 of described the first film transistor 5 with corresponding to the drain electrode 53 of described the first film transistor 5, and the top electrode 62 that is independent of described pixel electrode 4 forms, and optimizing C
scapacitance time increased the aperture opening ratio of pixel.
Further, for fear of when the top electrode 62 of described storage capacitance is connected the outside constant voltage of introducing by lead-in wire 7 with external voltage input, the larger problem of voltage noise that described outside constant voltage source provides to described storage capacitance 6, reaches and is optimizing C
scapacitance, reduce described storage capacitance when increasing the aperture opening ratio of pixel and introduce the noise object of external voltage, as shown in Figure 3, on described array base palte, be also formed with the second thin-film transistor 8, the grid of described the second thin-film transistor 8 is connected with described controlling grid scan line 2; The source electrode 83 of described the second thin-film transistor 8 is connected with described controlling grid scan line 2; The concrete connected mode that described top electrode 62 is connected to constant voltage source is: described top electrode 62 is connected with the drain electrode 82 of described the second thin-film transistor 8.
Optionally, described the second thin-film transistor 8 is positioned at the top of described controlling grid scan line 2, and the grid of described the second thin-film transistor 8 is a part for described controlling grid scan line 2.
Described top electrode 62 is connected concrete connected mode with the drain electrode 82 of described the second thin-film transistor 8: described top electrode 62 connects by the via hole of drain electrode 82 tops of described the second thin-film transistor 8.
As shown in Figure 4, the source electrode 83 of described the second thin-film transistor 8 is connected concrete connected mode with described controlling grid scan line 2 and is:
Source electrode 83 tops of described the second thin-film transistor 8 are formed with via hole; Described controlling grid scan line 2 tops are formed with via hole; Connecting electrode 9 couples together the source electrode of described the second thin-film transistor 8 83 and described controlling grid scan line 2 by the via hole of source electrode 83 tops of described the second thin-film transistor 8 and the via hole of described controlling grid scan line 2 tops.
In the time of concrete use, the signal on described controlling grid scan line 2 passes on the source electrode 83 of the second thin-film transistor 8, and now the grid of the second thin-film transistor 8 is opened, and signal reaches in the drain electrode 82 of the second thin-film transistor 8.The top electrode 62 of described storage capacitance 6 is connected with the drain electrode 82 of described the second thin-film transistor 8, so drain electrode 82 signals of thin-film transistor 8 transfer to the top electrode 62 of storage capacitance 6.Same, the signal on data scanning line 3 is transferred in the drain electrode 53 of the first film transistor 5.
In the present embodiment, drain electrode 82 and the source electrode 83 of the drain electrode 53 of described data scanning line 3, the first film transistor 5 and source electrode 52, the second thin-film transistor 8 form in a photoetching composition technique, have the gradient after identical thickness and identical corrosion; Described top electrode 62, described connecting electrode 9 and pixel electrode 4 form in a composition technique, have the gradient after identical thickness and identical corrosion.On described controlling grid scan line 2, cover insulating barrier and passivation layer, on described data scanning line 3, covered passivation layer.
The structure of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the thickness that distance between hearth electrode and the top electrode of this storage capacitance is passivation layer, the distance of top crown and described bottom crown is reduced, optimize the capacitance of storage capacitance, solved the C on array base palte in prior art
spixel electrode and storage capacitance hearth electrode between distance larger, cause C
scapacitance less and have a fluctuation, C
svoltage can not constantly remain to the problem of next time upgrading picture.
As shown in Figure 5, the manufacture method of the array base palte that the embodiment of the present invention provides, comprising:
Step 101 forms the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technique, the hearth electrode of described storage capacitance and described data scanning line are positioned at same layer.
Step 102 deposits one deck passivation layer on described substrate, forms via hole by mask composition technique.
Step 103 deposits layer of transparent conductive film on described substrate, forms pixel electrode and storage capacitance top electrode by mask composition technique, and wherein pixel electrode is connected with drain electrode by via hole, and described via hole is positioned at the top of described drain electrode.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the thickness that distance between hearth electrode and the top electrode of this storage capacitance is passivation layer, the distance of top crown and described bottom crown is reduced, optimize the capacitance of storage capacitance, solved the C on array base palte in prior art
spixel electrode and storage capacitance hearth electrode between distance larger, thereby affected C
sthe size of capacitance, cause C
scharged voltage can not remain to when upgrading picture next time, makes voltage have variation, and shown GTG will incorrect problem.
As shown in Figure 6, the manufacture method of the array base palte that further embodiment of this invention provides, comprising:
Step 201 deposits active layer film on the substrate with gate pattern and insulating barrier, forms active layer pattern by mask composition technique.
The specific implementation of described step 201 is: utilize chemical vapour deposition technique depositing insulating layer film and active layer film successively on the substrate with gate pattern, the thickness of described insulating layer of thin-film is between 1000 dust-6000 dusts, and the thickness of described active layer film is between 1000 dust-6000 dusts.Normally silicon nitride of the material of described insulating layer of thin-film, also can use silica and silicon oxynitride etc.Described active layer film adopts amorphous silicon membrane conventionally.
After described active layer film being exposed with the mask of active layer in the present embodiment, carry out dry etching, form active layer pattern, and insulating layer of thin-film between described gate pattern and amorphous silicon plays the effect that stops etching.
What deserves to be explained is, in step 201, the substrate with gate pattern can be realized by following execution mode:
On glass substrate, prepare one deck grid metallic film, on the certain area of glass substrate, form gate pattern by mask composition technique, the grid that described gate pattern comprises controlling grid scan line and is connected with controlling grid scan line.
In the present embodiment, adopt magnetically controlled sputter method on glass substrate, to prepare one deck grid metallic film, the thickness of this grid metallic film is between 1000 dust-7000 dusts.Described grid metallic film material adopts the metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper conventionally, also can adopt the combining structure of above-mentioned different materials film.
In step 202, the thickness of metallic film is between 1000 dust-7000 dusts.Described metallic film material adopts the metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper conventionally, also can adopt the combining structure of above-mentioned different materials film.
Step 203 deposits one deck passivation layer on described substrate, is being formed via hole and formed via hole above described drain electrode by mask composition technique above the two ends corresponding to described hearth electrode.
In described step 203, the thickness of described passivation layer is between 1000 dust-6000 dusts, and the material of described passivation layer is silicon nitride or silicon dioxide normally.Deposit one deck passivation layer on described substrate after, above described controlling grid scan line, cover insulating barrier and passivation layer, and form the via hole of top, hearth electrode two ends and the via hole of drain electrode top by mask composition technique.
Step 204 deposits layer of transparent conductive film on described substrate, forms pixel electrode by mask composition technique, and the pixel electrode that is wherein positioned at hearth electrode top forms the top electrode of storage capacitance.
In described step 204, described pixel electrode is connected with drain electrode by the via hole of drain electrode top, the transparency electrode that described transparent conductive film is conventional is indium tin oxide transparent conductive semiconductor film ITO or indium-zinc oxide transparent conductive semiconductor film IZO, the thickness of this transparent conductive film is between 100 dust-1000 dusts, and the passivation layer clipping between the top electrode of described storage capacitance, hearth electrode and described top electrode and hearth electrode forms storage capacitance.
In the present embodiment, the hearth electrode of described storage capacitance is parallel to described grid surface sweeping line the edge corresponding to the latter half of described pixel electrode.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the thickness that distance between hearth electrode and the top electrode of this storage capacitance is passivation layer, the distance of top crown and described bottom crown is reduced, optimize the capacitance of storage capacitance, solved the C on array base palte in prior art
spixel electrode and storage capacitance hearth electrode between distance larger, thereby affected C
sthe size of capacitance, cause C
scharged voltage can not remain to when upgrading picture next time, makes voltage have variation, and shown GTG will incorrect problem.
As shown in Figure 7, the manufacture method of the array base palte that another embodiment of the present invention provides, comprising:
In described step 301, by adopting gray tone or halftoning composition technique to form active layer, data scanning line, source electrode and drain electrode in a composition technique, can reduce processing step, save cost.The specific implementation of the described substrate with gate pattern and insulating layer pattern is same as the previously described embodiments, repeats no more herein.
Step 302 deposits one deck passivation layer on described substrate, forms via hole by mask composition technique.
Step 303 deposits layer of transparent conductive film on described substrate, forms the top electrode of pixel electrode and storage capacitance by mask composition technique, and the top electrode of described storage capacitance is independent of described pixel electrode.
In described step 303, described pixel electrode is connected with described drain electrode by the via hole of described drain electrode top.
In the present embodiment, on the top electrode of storage capacitance described in abovementioned steps or subsequent step, can be formed with for the lead-in wire that is connected with described external voltage input.The passivation layer clipping between top electrode, hearth electrode and described top electrode and the hearth electrode of described storage capacitance forms storage capacitance.
In the present embodiment, adopt drain electrode as electric capacity hearth electrode, and form and the top electrode of the storage capacitance of described pixel electrode identical material by mask composition at the same layer of pixel electrode, remove storage capacitance in above-described embodiment to the taking of elemental area, and then increased pixel aperture ratio.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the thickness that distance between hearth electrode and the top electrode of this storage capacitance is passivation layer, the distance of top crown and described bottom crown is reduced, optimize the capacitance of storage capacitance, solved the C on array base palte in prior art
spixel electrode and storage capacitance hearth electrode between distance larger, thereby affected C
sthe size of capacitance, cause C
scharged voltage can not remain to when upgrading picture next time, makes voltage have variation, and shown GTG will incorrect problem.
As shown in Figure 8, the manufacture method of the array base palte that yet another embodiment of the invention provides, comprising:
The specific implementation of substrate of preparing described gate pattern and insulating barrier in described step 401 is same as the previously described embodiments, repeats no more herein.
Step 403 deposits one deck passivation layer on described substrate, forms the via hole of the first drain electrode top, via hole, the via hole of the second source electrode top and the via hole of controlling grid scan line top of the second drain electrode top by mask composition technique.
In the present embodiment, grid, the first active layer, the first source electrode and the first drain electrode form the first film transistor; Controlling grid scan line, the second active layer, the second source electrode and the second drain electrode form the second thin-film transistor; The passivation layer clipping between top electrode, hearth electrode and described top electrode and the hearth electrode of described storage capacitance forms storage capacitance.
In the present embodiment, in increasing aperture opening ratio, because described storage capacitance is connected with controlling grid scan line by the second thin-film transistor, by described the second thin-film transistor, the external voltage of introducing by described controlling grid scan line is carried out to noise elimination, reduced external voltage due to the impact of noise problem on described storage capacitance.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the thickness that distance between hearth electrode and the top electrode of this storage capacitance is passivation layer, the distance of top crown and described bottom crown is reduced, optimize the capacitance of storage capacitance, solved the C on array base palte in prior art
spixel electrode and storage capacitance hearth electrode between distance larger, thereby affected C
sthe size of capacitance, cause C
scharged voltage can not remain to when upgrading picture next time, makes voltage have variation, and shown GTG will incorrect problem.
The embodiment of the present invention is mainly used in demonstration field, is particularly useful for display panels.
The embodiment of the present invention is mainly with C
son common is described, and Cs on gate and these two kinds of modes of Cson common can be used in conjunction with, in practice as Figure of description.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (8)
1. an array base palte, comprise substrate, and the controlling grid scan line forming on substrate, data scanning line, pixel electrode and the first film transistor, the transistorized grid of this first film is connected with controlling grid scan line, the transistorized source electrode of this first film is connected with data scanning line, the transistorized drain electrode of this first film is connected with pixel electrode; It is characterized in that, also comprise:
Storage capacitance, the hearth electrode of described storage capacitance is the transistorized drain electrode of described the first film, and is positioned at same aspect with described data scanning line, and the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, and described top electrode is connected to constant voltage source;
On described array base palte, be also formed with the second thin-film transistor, the grid of described the second thin-film transistor is connected with described controlling grid scan line; The source electrode of described the second thin-film transistor is connected with described controlling grid scan line; The concrete connected mode that described top electrode is connected to constant voltage source is: described top electrode is connected with the drain electrode of described the second thin-film transistor.
2. array base palte according to claim 1, is characterized in that, the top electrode correspondence of described storage capacitance is positioned at the position of the transistorized drain electrode of described the first film, and the top electrode of described storage capacitance is independent of described pixel electrode.
3. array base palte according to claim 1, it is characterized in that, the transistorized drain electrode of the drain electrode of described the second thin-film transistor and source electrode and the first film and source electrode, data scanning line form in a photoetching composition technique, have the gradient after identical thickness and identical corrosion.
4. array base palte according to claim 1, is characterized in that, described the second thin-film transistor is positioned at the top of described controlling grid scan line, the part that the grid of described the second thin-film transistor is described controlling grid scan line.
5. array base palte according to claim 1, is characterized in that, described top electrode is connected concrete connected mode with the drain electrode of described the second thin-film transistor and is: described top electrode connects by the via hole of the drain electrode top of described the second thin-film transistor.
6. according to the arbitrary described array base palte of claim 1 to 5, it is characterized in that, the source electrode of described the second thin-film transistor is connected concrete connected mode with described controlling grid scan line and is:
The source electrode top of described the second thin-film transistor is formed with via hole; Described controlling grid scan line top is formed with via hole; Connecting electrode couples together the source electrode of described the second thin-film transistor and described controlling grid scan line by the via hole of the source electrode top of described the second thin-film transistor and the via hole of described controlling grid scan line top.
7. array base palte according to claim 6, is characterized in that, the top electrode of described connecting electrode and described storage capacitance and described pixel electrode are to form in a composition technique, has the gradient after identical thickness and identical corrosion.
8. a manufacture method for array base palte, is characterized in that, comprising:
On the substrate with gate pattern and insulating barrier, form the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance by composition technique, the hearth electrode of described storage capacitance is transistorized the first drain electrode of the first film, and be positioned at same layer with described data scanning line, described the first film transistor comprises: the first source electrode, the first drain electrode, comprising:
On the substrate with gate pattern and insulating barrier, deposit active layer film, above the grid of gate pattern, form the first active layer by mask composition technique, above the controlling grid scan line of described gate pattern, form the second active layer, described the first active layer and described the second active layer form active layer pattern
Depositing metal films on the substrate with gate pattern, insulating barrier and active layer pattern, forms data scanning line, the first source electrode, the first drain electrode, the second source electrode and the second drain electrode by mask composition technique;
On described substrate, deposit one deck passivation layer, form via hole by mask composition technique, comprising:
On described substrate, deposit one deck passivation layer, form the via hole of the first drain electrode top, via hole, the via hole of the second source electrode top and the via hole of controlling grid scan line top of the second drain electrode top by mask composition technique;
On described substrate, deposit layer of transparent conductive film, form pixel electrode and storage capacitance top electrode by mask composition technique, wherein pixel electrode is connected with drain electrode by via hole, comprising:
On described substrate, deposit layer of transparent conductive film, form top electrode and the connecting electrode of pixel electrode, storage capacitance by mask composition technique, the top electrode correspondence of described storage capacitance is positioned at the position of the transistorized drain electrode of described the first film, and the top electrode of described storage capacitance is connected with described the second drain electrode by the via hole of the second drain electrode top; Described connecting electrode is connected the second source electrode with the via hole of controlling grid scan line top by the via hole of the second source electrode top with controlling grid scan line.
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| KR102438782B1 (en) * | 2015-11-26 | 2022-09-01 | 엘지디스플레이 주식회사 | Display Device and Method of Manufacturing the same |
| CN109270751B (en) * | 2018-10-23 | 2020-10-30 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal display panel |
| CN114823735A (en) * | 2022-05-07 | 2022-07-29 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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| CN1488083A (en) * | 2001-09-26 | 2004-04-07 | 三星电子株式会社 | Thin film transistor array substrate of liquid crystal display device and producing method thereof |
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