CN102280443A - Structure of array substrate and manufacturing method thereof - Google Patents
Structure of array substrate and manufacturing method thereof Download PDFInfo
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- CN102280443A CN102280443A CN2010102001778A CN201010200177A CN102280443A CN 102280443 A CN102280443 A CN 102280443A CN 2010102001778 A CN2010102001778 A CN 2010102001778A CN 201010200177 A CN201010200177 A CN 201010200177A CN 102280443 A CN102280443 A CN 102280443A
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Abstract
The invention discloses a structure of an array substrate and a manufacturing method thereof, and relates to the technical field of display. The invention aims to solve the problem that the distance between a pixel electrode and a common electrode in a storage capacity (CS) is long so abnormal gray scale is caused by change of the voltage at two ends of liquid crystals in a liquid crystal panel due to failure of retention of the constant voltage for controlling liquid crystal diversion under the condition that the CS is charged is solved. The array substrate comprises a substrate, and a grid scanning line, a data scanning line, a pixel electrode and a first thin film transistor which are formed on the substrate, wherein a grid of the first thin film transistor is connected with the grid scanning line, a source of the first thin film transistor is connected with the data scanning line, and a drain of the first thin film transistor is connected with the pixel electrode; the array substrate also comprises the storage capacitor; and a bottom electrode of the storage capacitor and the data scanning line are positioned in the same plane; and a top electrode of the storage capacitor and the pixel electrode are positioned in the same plane. The embodiment of the invention is mainly applied in the display field, and is particularly suitable for liquid crystal display panels.
Description
Technical field
The present invention relates to the Display Technique field, relate in particular to a kind of structure and manufacture method of array base palte.
Background technology
Utilize thin-film transistor to produce voltage, be called Thin Film Transistor-LCD (TFT LCD) with the display that the control liquid crystal turns to.Thin Film Transistor-LCD comprises liquid crystal panel, and the liquid crystal that clips between layer glass up and down of liquid crystal panel has formed plane-parallel capacitor, is referred to as C
LC(capacitor of liquid crystal), its size is about 0.1pF.Described C
LCThe voltage that is used for retentive control liquid crystal transition, but when practical application, at thin-film transistor TFT to C
LCCharged back to TFT next time again to C
LCCharge in the time period, C
LCVoltage can't be maintained, make voltage change, cause shown GTG incorrect.
General modal storage capacitors Cs (storage capacitor) framework has two kinds, be respectively these two kinds of Cs on gate and Cs on common. these two kinds as the term suggests just can know, its main difference just is that storage capacitors utilizes gate cabling or common cabling to finish.Wherein, this C
Son commonPass through pixel electrode and common electrode form, clip gate insulator and passivation layer between described pixel electrode and the public electrode.
In realizing process of the present invention, the inventor finds, C
SThe C of this framework of on common
SIn the electric capacity between pixel electrode and the public electrode distance bigger, at C
SThe voltage constant that can not the retentive control liquid crystal under the charged situation turns to makes liquid crystal panel occur because the liquid crystal both end voltage changes the GTG abnormal problem that is caused.
Summary of the invention
Embodiments of the invention provide a kind of structure and manufacture method of array base palte, have solved C
SIn the electric capacity between pixel electrode and the public electrode distance bigger, at C
SThe voltage constant that can not the retentive control liquid crystal under the charged situation turns to makes liquid crystal panel occur because the liquid crystal both end voltage changes the GTG abnormal problem that is caused.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of array base palte, comprise substrate, and the controlling grid scan line that on substrate, forms, data scanning line, pixel electrode and the first film transistor, the transistorized grid of this first film links to each other with controlling grid scan line, the transistorized source electrode of this first film links to each other with the data scanning line, this first film transistor drain links to each other with pixel electrode; Also comprise storage capacitance, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, and the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect.
Concrete, the top electrode of described storage capacitance is described pixel electrode, and the hearth electrode of described storage capacitance is corresponding to the edge of the latter half of described pixel electrode, and the hearth electrode of described storage capacitance is connected to constant voltage source.
The concrete connected mode that the hearth electrode of described storage capacitance is connected to constant voltage source is: described hearth electrode is connected on the peripheral public electrode power supply by the via hole of described hearth electrode top.
Further, in order to optimize C
SCapacitance the time increase aperture ratio of pixels, the hearth electrode of described storage capacitance is the first film transistor drain, the top electrode of described storage capacitance is corresponding to described the first film transistor drain, and the top electrode of described storage capacitance is independent of described pixel electrode and described top electrode is connected to constant voltage source.
The concrete connected mode that described top electrode is connected to constant voltage source is: described top electrode is connected with the external voltage input by the lead-in wire that this top electrode is provided with.
Further, when linking to each other the outside constant voltage of introducing for fear of the top electrode when described storage capacitance with the external voltage input by lead-in wire, the bigger problem of voltage noise that described outside constant voltage source provides for described storage capacitance reaches and is optimizing C
SCapacitance, reduce the noise purpose that described storage capacitance is introduced external voltage when increasing aperture ratio of pixels, also be formed with second thin-film transistor on the described array base palte, the grid of described second thin-film transistor is connected with described controlling grid scan line; The source electrode of described second thin-film transistor is connected with described controlling grid scan line; The concrete connected mode that described top electrode is connected to constant voltage source is: described top electrode is connected with the drain electrode of described second thin-film transistor.
Optionally, described second thin-film transistor is positioned at the top of described controlling grid scan line, and the grid of described second thin-film transistor is the part of described controlling grid scan line.
Described top electrode is connected concrete connected mode with the drain electrode of described second thin-film transistor: described top electrode connects by the via hole of the drain electrode top of described second thin-film transistor.
The source electrode of described second thin-film transistor is connected concrete connected mode with described controlling grid scan line: the source electrode top of described second thin-film transistor is formed with via hole; Described controlling grid scan line top is formed with via hole; The via hole of the source electrode top of connection electrode by described second thin-film transistor and the via hole of described controlling grid scan line top couple together the source electrode and the described controlling grid scan line of described second thin-film transistor.
A kind of manufacture method of array base palte, comprise: form the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology, the hearth electrode of described storage capacitance and described data scanning line are positioned at same one deck; Deposition one deck passivation layer forms via hole by mask composition technology on described substrate; Deposition layer of transparent conductive film forms pixel electrode and storage capacitance top electrode by mask composition technology on described substrate, and wherein pixel electrode is connected with drain electrode by the via hole of described drain electrode top, and described via hole is positioned at the top of described drain electrode.
Concrete, the described hearth electrode that forms active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology comprises:
The active layer film of deposition forms active layer pattern by mask composition technology on the substrate with gate pattern and insulating barrier;
Depositing metal films on the substrate with gate pattern, insulating barrier and active layer pattern is by the hearth electrode of mask composition technology formation data scanning line, source electrode, drain electrode and storage capacitance;
Described one deck passivation layer that deposits on described substrate forms via hole by mask composition technology, comprising:
Deposition one deck passivation layer on described substrate forms via hole and form via hole above described drain electrode above corresponding to the two ends of described hearth electrode by mask composition technology;
The described layer of transparent conductive film that deposits on described substrate forms pixel electrode and storage capacitance top electrode by mask composition technology, comprising:
Deposition layer of transparent conductive film forms pixel electrode by mask composition technology on described substrate, and the pixel electrode that wherein is positioned at the hearth electrode top constitutes the top electrode of storage capacitance.
Further, in order to optimize C
SCapacitance the time increase aperture ratio of pixels, the described hearth electrode that forms active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology comprises:
Deposition active layer film and metallic film forms active layer pattern, data scanning line, source electrode and drain electrode by gray tone or halftoning composition technology on the substrate with gate pattern and insulating barrier, and described drain electrode is simultaneously also as the hearth electrode of storage capacitance;
The described layer of transparent conductive film that deposits on described substrate forms pixel electrode and storage capacitance top electrode by mask composition technology, comprising:
Deposition layer of transparent conductive film on described substrate, by the top electrode of mask composition technology formation pixel electrode and storage capacitance, the top electrode of described storage capacitance is independent of described pixel electrode.
And described method also comprises:
On the top electrode of described storage capacitance, be formed with and be used for linking to each other lead-in wire with described external voltage input.
Further, when linking to each other the outside constant voltage of introducing for fear of the top electrode when described storage capacitance with the external voltage input by lead-in wire, the bigger problem of voltage noise that described outside constant voltage source provides for described storage capacitance reaches and is optimizing C
SCapacitance, reduce the noise purpose that described storage capacitance is introduced external voltage when increasing aperture ratio of pixels, the described hearth electrode that forms active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology comprises:
The active layer film of deposition on substrate with gate pattern and insulating barrier, above the grid of gate pattern, form first active layer by mask composition technology, form second active layer above the controlling grid scan line of described gate pattern, described first active layer and described second active layer constitute active layer pattern;
Depositing metal films on substrate with gate pattern, insulating barrier and active layer pattern, form data scanning line, first source electrode, first drain electrode, second source electrode and second drain electrode by mask composition technology, described first drain electrode is simultaneously also as the storage capacitance hearth electrode;
Described one deck passivation layer that deposits on described substrate forms via hole by mask composition technology, comprising:
Deposition one deck passivation layer on described substrate forms the via hole of the first drain electrode top, the via hole of the second drain electrode top, the via hole of second source electrode top and the via hole of controlling grid scan line top by mask composition technology;
The described layer of transparent conductive film that deposits on described substrate forms pixel electrode and storage capacitance top electrode by mask composition technology, and wherein pixel electrode is connected with drain electrode by described via hole, comprising:
Deposition layer of transparent conductive film on described substrate, form the top electrode and the connection electrode of pixel electrode, storage capacitance by mask composition technology, the top electrode of described storage capacitance links to each other corresponding to via hole and described second drain electrode by the second drain electrode top of the top electrode of described first drain electrode and described storage capacitance; Described connection electrode is connected second source electrode by the via hole of second source electrode top and the via hole of controlling grid scan line top with controlling grid scan line.
The structure of the array base palte that the embodiment of the invention provides and manufacture method, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the hearth electrode of this storage capacitance and the distance between the top electrode are the thickness of passivation layer, make the distance of top crown and described bottom crown reduce, optimized the capacitance of storage capacitance, solved owing to the C on the array base palte in the prior art
SPixel electrode and the distance between the storage capacitance hearth electrode bigger, cause C
SCapacitance less and fluctuation, C arranged
SVoltage can not constantly remain to the problem of frame update next time.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
The vertical view of the array base palte that Fig. 1 provides for the embodiment of the invention;
The vertical view one of the array base palte that Fig. 2 provides for further embodiment of this invention;
The vertical view two of the array base palte that Fig. 3 provides for further embodiment of this invention;
The A-A cutaway view of the array base palte that Fig. 4 provides for the embodiment of the invention shown in Figure 3;
The manufacture method flow chart of the array base palte that Fig. 5 provides for the embodiment of the invention;
The manufacture method flow chart of the array base palte that Fig. 6 provides for further embodiment of this invention;
The manufacture method flow chart of the array base palte that Fig. 7 provides for another embodiment of the present invention;
The manufacture method flow chart of the array base palte that Fig. 8 provides for yet another embodiment of the invention.
Mark among the figure: 1-substrate; The 2-controlling grid scan line; 3-data scanning line; The 4-pixel electrode; 5, the first film transistor; The 51-grid; The 52-source electrode; The 53-drain electrode; The 6-storage capacitance; The 61-hearth electrode; The 62-top electrode; The 7-lead-in wire; 8-second thin-film transistor; The 82-drain electrode; The 83-source electrode; The 9-connection electrode.
Embodiment
The embodiment of the invention provides a kind of structure and manufacture method of array base palte, has solved C
SIn the electric capacity between pixel electrode and the public electrode distance bigger, at C
SThe voltage constant that can not the retentive control liquid crystal under the charged situation turns to makes liquid crystal panel occur because the liquid crystal both end voltage changes the GTG abnormal problem that is caused.
As shown in Figure 1, the array base palte that the embodiment of the invention provides, comprise substrate 1, and the controlling grid scan line 2, data scanning line 3, pixel electrode 4 and the first film transistor 5 that on substrate 1, form, the grid 51 of this first film transistor 5 links to each other with controlling grid scan line 2, source electrode 52 and data scanning line 3 link to each other, drain 53 links to each other with pixel electrode 4; Also comprise storage capacitance 6, the hearth electrode 61 and the described data scanning line 3 of described storage capacitance 6 are positioned at same aspect, and the top electrode of described storage capacitance 6 and described pixel electrode 4 are positioned at same aspect.
When concrete utilization, the top electrode of described storage capacitance 6 is a pixel electrode 4, the hearth electrode 61 of described storage capacitance is parallel to described controlling grid scan line 2 and corresponding with the edge of the latter half of described pixel electrode 4, and the hearth electrode 61 of described storage capacitance is connected to constant voltage source, do not provide concrete connected mode among Fig. 1, for example, hearth electrode 61 can be connected to by the via hole of hearth electrode 61 tops on the peripheral public electrode power supply, the top at the two ends of described hearth electrode 61 is provided with via hole, can interconnect by connecting line between a plurality of hearth electrodes 61, choose one of them hearth electrode 61 and be connected on the peripheral public electrode power supply by the via hole on the described hearth electrode 61.
The structure of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the hearth electrode of this storage capacitance and the distance between the top electrode are the thickness of passivation layer, make the distance of top crown and described bottom crown reduce, optimize the capacitance of storage capacitance, solved the C on the array base palte in the prior art
SPixel electrode and the distance between the storage capacitance hearth electrode bigger, cause C
SCapacitance less and fluctuation, C arranged
SVoltage can not constantly remain to the problem of frame update next time.
As shown in Figure 2, the structure of the array base palte that further embodiment of this invention provides, comprise substrate 1, and the controlling grid scan line 2, data scanning line 3, pixel electrode 4 and the first film transistor 5 that on substrate 1, form, the grid 51 of this first film transistor 5 links to each other with controlling grid scan line 2, source electrode 52 and data scanning line 3 link to each other, drain 53 links to each other with pixel electrode 4; Also comprise storage capacitance 6, the hearth electrode of described storage capacitance 6 and described data scanning line 3 are positioned at same aspect, the hearth electrode of described storage capacitance 6 is the drain electrode 53 of described the first film transistor 5, and the top electrode 62 and the described pixel electrode 4 of described storage capacitance 6 are positioned at same aspect.The top electrode 62 of described storage capacitance is corresponding to the drain electrode 53 of described the first film transistor 5, and the top electrode 62 of described storage capacitance is independent of described pixel electrode 4 and described top electrode 62 is connected to constant voltage source.
During concrete the application, the concrete connected mode that described top electrode 62 is connected to constant voltage source is:
Described top electrode 62 is connected with the external voltage input by the lead-in wire 7 that this top electrode 62 is provided with.External voltage described herein can be provided by pcb board.
In the present embodiment, described storage capacitance 6 is by the drain electrode 53 of described the first film transistor 5 with corresponding to the drain electrode 53 of described the first film transistor 5, and the top electrode 62 that is independent of described pixel electrode 4 forms, and optimizing C
SCapacitance the time increased aperture ratio of pixels.
Further, for fear of linking to each other with the external voltage input when introducing outside constant voltage by lead-in wire 7 when the top electrode 62 of described storage capacitance, the bigger problem of voltage noise that described outside constant voltage source provides for described storage capacitance 6 reaches at optimization C
SCapacitance, reduce the noise purpose that described storage capacitance is introduced external voltage when increasing aperture ratio of pixels, as shown in Figure 3, also be formed with second thin-film transistor 8 on the described array base palte, the grid of described second thin-film transistor 8 is connected with described controlling grid scan line 2; The source electrode 83 of described second thin-film transistor 8 is connected with described controlling grid scan line 2; The concrete connected mode that described top electrode 62 is connected to constant voltage source is: described top electrode 62 is connected with the drain electrode 82 of described second thin-film transistor 8.
Optionally, described second thin-film transistor 8 is positioned at the top of described controlling grid scan line 2, and the grid of described second thin-film transistor 8 is the part of described controlling grid scan line 2.
Described top electrode 62 is connected concrete connected mode with the drain electrode 82 of described second thin-film transistor 8: described top electrode 62 connects by the via hole of drain electrode 82 tops of described second thin-film transistor 8.
As shown in Figure 4, the source electrode 83 of described second thin-film transistor 8 is connected concrete connected mode with described controlling grid scan line 2 and is:
When concrete the use, the signal on the described controlling grid scan line 2 passes on the source electrode 83 of second thin-film transistor 8, and this moment, the grid of second thin-film transistor 8 was opened, and signal reaches in the drain electrode 82 of second thin-film transistor 8.The top electrode 62 of described storage capacitance 6 links to each other with the drain electrode 82 of described second thin-film transistor 8, so drain electrode 82 signals of thin-film transistor 8 transfer to the top electrode 62 of storage capacitance 6.Same, the signal on the data scanning line 3 is transferred in the drain electrode 53 of the first film transistor 5.
In the present embodiment, the drain electrode 82 and the source electrode 83 of the drain electrode 53 of described data scanning line 3, the first film transistor 5 and source electrode 52, second thin-film transistor 8 form in a photoetching composition technology, have the gradient after identical thickness and the identical corrosion; Described top electrode 62, described connection electrode 9 and pixel electrode 4 form in a composition technology, have the gradient after identical thickness and the identical corrosion.Cover insulating barrier and passivation layer on the described controlling grid scan line 2, covered passivation layer on the described data scanning line 3.
The structure of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the hearth electrode of this storage capacitance and the distance between the top electrode are the thickness of passivation layer, make the distance of top crown and described bottom crown reduce, optimize the capacitance of storage capacitance, solved the C on the array base palte in the prior art
SPixel electrode and the distance between the storage capacitance hearth electrode bigger, cause C
SCapacitance less and fluctuation, C arranged
SVoltage can not constantly remain to the problem of frame update next time.
As shown in Figure 5, the manufacture method of the array base palte that the embodiment of the invention provides comprises:
Step 101 forms the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance by composition technology on the substrate with gate pattern and insulating barrier, the hearth electrode of described storage capacitance and described data scanning line are positioned at same one deck.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the hearth electrode of this storage capacitance and the distance between the top electrode are the thickness of passivation layer, make the distance of top crown and described bottom crown reduce, optimize the capacitance of storage capacitance, solved the C on the array base palte in the prior art
SPixel electrode and the distance between the storage capacitance hearth electrode bigger, thereby influenced C
SThe size of capacitance, cause C
SWhen charged voltage can not remain to next time frame update, make voltage that variation arranged, shown GTG will incorrect problem.
As shown in Figure 6, the manufacture method of the array base palte that further embodiment of this invention provides comprises:
The specific implementation of described step 201 is: utilize chemical vapour deposition technique having on the substrate of gate pattern depositing insulating layer film and active layer film successively, the thickness of described insulating layer of thin-film is between 1000 dusts-6000 dust, and the thickness of described active layer film is between 1000 dusts-6000 dust.The material of described insulating layer of thin-film is silicon nitride normally, also can use silica and silicon oxynitride etc.Described active layer film adopts amorphous silicon membrane usually.
Carry out dry etching after with the mask of active layer described active layer film being exposed in the present embodiment, form active layer pattern, and the insulating layer of thin-film between described gate pattern and the amorphous silicon plays the effect that stops etching.
What deserves to be explained is that in step 201, the substrate with gate pattern can be realized by following execution mode:
Preparation one deck grid metallic film forms gate pattern by mask composition technology on certain zone of glass substrate on glass substrate, and described gate pattern comprises controlling grid scan line and the grid that links to each other with controlling grid scan line.
In the present embodiment, adopt magnetically controlled sputter method to prepare one deck grid metallic film on glass substrate, the thickness of this grid metallic film is between 1000 dusts-7000 dust.Described grid metallic film material adopts metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually, also can adopt the combining structure of above-mentioned different materials film.
In step 202, the thickness of metallic film is between 1000 dusts-7000 dust.Described metallic film material adopts metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually, also can adopt the combining structure of above-mentioned different materials film.
In described step 203, the thickness of described passivation layer is between 1000 dusts-6000 dust, and the material of described passivation layer is silicon nitride or silicon dioxide normally.On described substrate, after deposition one deck passivation layer, cover insulating barrier and passivation layer above the described controlling grid scan line, and form the via hole of top, hearth electrode two ends and the via hole of drain electrode top by mask composition technology.
In described step 204, described pixel electrode is connected with drain electrode by the via hole of drain electrode top, the transparency electrode that described transparent conductive film is commonly used is indium tin oxide transparent conductive semiconductor film ITO or indium-zinc oxide transparent conductive semiconductor film IZO, the thickness of this transparent conductive film is between 100 dusts-1000 dust, and the passivation layer that clips between the top electrode of described storage capacitance, hearth electrode and described top electrode and the hearth electrode constitutes storage capacitance.
In the present embodiment, the hearth electrode of described storage capacitance is parallel to described grid surface sweeping line and corresponding to the edge of the latter half of described pixel electrode.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the hearth electrode of this storage capacitance and the distance between the top electrode are the thickness of passivation layer, make the distance of top crown and described bottom crown reduce, optimize the capacitance of storage capacitance, solved the C on the array base palte in the prior art
SPixel electrode and the distance between the storage capacitance hearth electrode bigger, thereby influenced C
SThe size of capacitance, cause C
SWhen charged voltage can not remain to next time frame update, make voltage that variation arranged, shown GTG will incorrect problem.
As shown in Figure 7, the manufacture method of the array base palte that another embodiment of the present invention provides comprises:
In the described step 301, in a composition technology, form active layer, data scanning line, source electrode and drain electrode, can reduce processing step, save cost by adopting gray tone or halftoning composition technology.The specific implementation of described substrate with gate pattern and insulating layer pattern is same as the previously described embodiments, repeats no more herein.
In the described step 303, described pixel electrode is connected with described drain electrode by the via hole of described drain electrode top.
In the present embodiment, on the top electrode of storage capacitance described in abovementioned steps or the subsequent step, can be formed with and be used for linking to each other lead-in wire with described external voltage input.The passivation layer that clips between the top electrode of described storage capacitance, hearth electrode and described top electrode and the hearth electrode constitutes storage capacitance.
In the present embodiment, adopt drain electrode as the electric capacity hearth electrode, and form top electrode with the storage capacitance of described pixel electrode identical material by the mask composition at same one deck of pixel electrode, remove storage capacitance in the foregoing description to the taking of elemental area, and then increased pixel aperture ratio.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the hearth electrode of this storage capacitance and the distance between the top electrode are the thickness of passivation layer, make the distance of top crown and described bottom crown reduce, optimize the capacitance of storage capacitance, solved the C on the array base palte in the prior art
SPixel electrode and the distance between the storage capacitance hearth electrode bigger, thereby influenced C
SThe size of capacitance, cause C
SWhen charged voltage can not remain to next time frame update, make voltage that variation arranged, shown GTG will incorrect problem.
As shown in Figure 8, the manufacture method of the array base palte that yet another embodiment of the invention provides comprises:
The specific implementation of the substrate of described gate pattern of preparation and insulating barrier is same as the previously described embodiments in the described step 401, repeats no more herein.
In the present embodiment, grid, first active layer, first source electrode and first drain electrode constitute the first film transistor; Controlling grid scan line, second active layer, second source electrode and second drain electrode constitute second thin-film transistor; The passivation layer that clips between the top electrode of described storage capacitance, hearth electrode and described top electrode and the hearth electrode constitutes storage capacitance.
In the present embodiment, when increasing aperture opening ratio, because described storage capacitance links to each other with controlling grid scan line by second thin-film transistor, by described second thin-film transistor external voltage of introducing by described controlling grid scan line is carried out noise eliminating, reduced external voltage owing to the influence of noise problem to described storage capacitance.
The manufacture method of the array base palte that embodiments of the invention provide, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect, the hearth electrode of this storage capacitance and the distance between the top electrode are the thickness of passivation layer, make the distance of top crown and described bottom crown reduce, optimize the capacitance of storage capacitance, solved the C on the array base palte in the prior art
SPixel electrode and the distance between the storage capacitance hearth electrode bigger, thereby influenced C
SThe size of capacitance, cause C
SWhen charged voltage can not remain to next time frame update, make voltage that variation arranged, shown GTG will incorrect problem.
The embodiment of the invention is mainly used in the demonstration field, is particularly useful for display panels.
The embodiment of the invention is mainly with C
SOn common is described, and Cs on gate and this dual mode of Cson common can be used in the practice, as Figure of description.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (16)
1. array base palte, comprise substrate, and the controlling grid scan line that on substrate, forms, data scanning line, pixel electrode and the first film transistor, the transistorized grid of this first film links to each other with controlling grid scan line, the transistorized source electrode of this first film links to each other with the data scanning line, this first film transistor drain links to each other with pixel electrode; It is characterized in that, also comprise:
Storage capacitance, the hearth electrode of described storage capacitance and described data scanning line are positioned at same aspect, and the top electrode of described storage capacitance and described pixel electrode are positioned at same aspect.
2. array base palte according to claim 1, it is characterized in that, the top electrode of described storage capacitance is described pixel electrode, and the hearth electrode of described storage capacitance is corresponding to the edge of the latter half of described pixel electrode, and the hearth electrode of described storage capacitance is connected to constant voltage source.
3. array base palte according to claim 2 is characterized in that, the concrete connected mode that the hearth electrode of described storage capacitance is connected to constant voltage source is:
Described hearth electrode is connected on the peripheral public electrode power supply by the via hole of described hearth electrode top.
4. array base palte according to claim 1, it is characterized in that, the hearth electrode of described storage capacitance is the first film transistor drain, the top electrode of described storage capacitance is corresponding to described the first film transistor drain, and the top electrode of described storage capacitance is independent of described pixel electrode and described top electrode is connected to constant voltage source.
5. array base palte according to claim 4 is characterized in that, the concrete connected mode that described top electrode is connected to constant voltage source is:
Described top electrode is connected with the external voltage input by the lead-in wire that this top electrode is provided with.
6. array base palte according to claim 4 is characterized in that, also is formed with second thin-film transistor on the described array base palte, and the grid of described second thin-film transistor is connected with described controlling grid scan line; The source electrode of described second thin-film transistor is connected with described controlling grid scan line; The concrete connected mode that described top electrode is connected to constant voltage source is: described top electrode is connected with the drain electrode of described second thin-film transistor.
7. array base palte according to claim 6, it is characterized in that, the drain electrode of described second thin-film transistor and source electrode and the first film transistor drain and source electrode, data scanning line form in a photoetching composition technology, have the gradient after identical thickness and the identical corrosion.
8. array base palte according to claim 6 is characterized in that described second thin-film transistor is positioned at the top of described controlling grid scan line, and the grid of described second thin-film transistor is the part of described controlling grid scan line.
9. array base palte according to claim 6 is characterized in that, described top electrode is connected concrete connected mode with the drain electrode of described second thin-film transistor and is: described top electrode connects by the via hole of the drain electrode top of described second thin-film transistor.
10. according to the arbitrary described array base palte of claim 6 to 9, it is characterized in that the source electrode of described second thin-film transistor is connected concrete connected mode with described controlling grid scan line and is:
The source electrode top of described second thin-film transistor is formed with via hole; Described controlling grid scan line top is formed with via hole; The via hole of the source electrode top of connection electrode by described second thin-film transistor and the via hole of described controlling grid scan line top couple together the source electrode and the described controlling grid scan line of described second thin-film transistor.
11. array base palte according to claim 10 is characterized in that, the top electrode of described connection electrode and described storage capacitance and described pixel electrode are to form in a composition technology, have the gradient after identical thickness and the identical corrosion.
12. the manufacture method of an array base palte is characterized in that, comprising:
Form the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology, the hearth electrode of described storage capacitance and described data scanning line are positioned at same one deck;
Deposition one deck passivation layer forms via hole by mask composition technology on described substrate;
Deposition layer of transparent conductive film forms pixel electrode and storage capacitance top electrode by mask composition technology on described substrate, and wherein pixel electrode is connected with drain electrode by via hole, and described via hole is positioned at the top of described drain electrode.
13. method according to claim 12 is characterized by, the described hearth electrode that forms active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology comprises:
The active layer film of deposition forms active layer pattern by mask composition technology on the substrate with gate pattern and insulating barrier;
Depositing metal films on the substrate with gate pattern, insulating barrier and active layer pattern is by the hearth electrode of mask composition technology formation data scanning line, source electrode, drain electrode and storage capacitance;
Described one deck passivation layer that deposits on described substrate forms via hole by mask composition technology, comprising:
Deposition one deck passivation layer on described substrate forms via hole and form via hole above described drain electrode above corresponding to the two ends of described hearth electrode by mask composition technology;
The described layer of transparent conductive film that deposits on described substrate forms pixel electrode and storage capacitance top electrode by mask composition technology, comprising:
Deposition layer of transparent conductive film forms pixel electrode by mask composition technology on described substrate, and the pixel electrode that wherein is positioned at the hearth electrode top constitutes the top electrode of storage capacitance.
14. method according to claim 12 is characterized in that, the described hearth electrode that forms active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology comprises:
Deposition active layer film and metallic film forms active layer pattern, data scanning line, source electrode and drain electrode by gray tone or halftoning composition technology on the substrate with gate pattern and insulating barrier, and described drain electrode is simultaneously also as the hearth electrode of storage capacitance;
The described layer of transparent conductive film that deposits on described substrate forms pixel electrode and storage capacitance top electrode by mask composition technology, comprising:
Deposition layer of transparent conductive film on described substrate, by the top electrode of mask composition technology formation pixel electrode and storage capacitance, the top electrode of described storage capacitance is independent of described pixel electrode.
15. method according to claim 14 is characterized in that, also comprises:
On the top electrode of described storage capacitance, be formed with and be used for linking to each other lead-in wire with described external voltage input.
16. method according to claim 12 is characterized in that, forms the hearth electrode of active layer pattern, data scanning line, source electrode, drain electrode and storage capacitance on the substrate with gate pattern and insulating barrier by composition technology, comprising:
The active layer film of deposition on substrate with gate pattern and insulating barrier, above the grid of gate pattern, form first active layer by mask composition technology, form second active layer above the controlling grid scan line of described gate pattern, described first active layer and described second active layer constitute active layer pattern;
Depositing metal films on substrate with gate pattern, insulating barrier and active layer pattern, form data scanning line, first source electrode, first drain electrode, second source electrode and second drain electrode by mask composition technology, described first drain electrode is simultaneously also as the storage capacitance hearth electrode;
Described one deck passivation layer that deposits on described substrate forms via hole by mask composition technology, comprising:
Deposition one deck passivation layer on described substrate forms the via hole of the first drain electrode top, the via hole of the second drain electrode top, the via hole of second source electrode top and the via hole of controlling grid scan line top by mask composition technology;
The described layer of transparent conductive film that deposits on described substrate forms pixel electrode and storage capacitance top electrode by mask composition technology, and wherein pixel electrode is connected with drain electrode by via hole, comprising:
Deposition layer of transparent conductive film on described substrate, form the top electrode and the connection electrode of pixel electrode, storage capacitance by mask composition technology, the top electrode of described storage capacitance links to each other corresponding to via hole and described second drain electrode by the second drain electrode top of the top electrode of described first drain electrode and described storage capacitance; Described connection electrode is connected second source electrode by the via hole of second source electrode top and the via hole of controlling grid scan line top with controlling grid scan line.
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| WO2023216305A1 (en) * | 2022-05-07 | 2023-11-16 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
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