CN102270250A - Layout method of circuit board - Google Patents
Layout method of circuit board Download PDFInfo
- Publication number
- CN102270250A CN102270250A CN201010198993XA CN201010198993A CN102270250A CN 102270250 A CN102270250 A CN 102270250A CN 201010198993X A CN201010198993X A CN 201010198993XA CN 201010198993 A CN201010198993 A CN 201010198993A CN 102270250 A CN102270250 A CN 102270250A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- secondary element
- major component
- layout
- layout method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention provides a layout method of a circuit board. The method comprises the following steps of: building a component group, wherein the component group comprises a main component and a plurality of auxiliary components which are functionally related to the main component; arranging the main component to be configured on a first surface of the circuit board; moving one of the auxiliary components to the first surface of the circuit board; judging whether the length of connecting line between the main component and the auxiliary component is less than or equal to a preset length; if the length of connecting line is less than or equal to the preset length, configuring the auxiliary component on the first surface; if the length of connecting line is more than or equal to the preset length, moving the one auxiliary component from the first surface; selecting another unconfigured auxiliary component, and returning to the step of moving one of the auxiliary components to the first surface of the circuit board until the configurations of all the auxiliary components are completed. Accordingly, the working time of a layout engineer is greatly reduced, so that the work efficiency is increased.
Description
Technical field
The present invention relates to a kind of layout method, and relate in particular to a kind of layout method of circuit board.
Background technology
(printed circuit board, layout PCB) (layout) program is usually by the circuit diagram of Electronics Engineer's designing printed circuit board, and transfers a layout after having drawn to for known printed circuit board (PCB).Then, design and draw the mechanism map of this printed circuit board (PCB) by the slip-stick artist of mechanism.Afterwards, layout slip-stick artist carries out configuration (placement) operation, with electronic component according to circuit diagram or mechanism map and be configured to the precalculated position of printed circuit board (PCB).
When carrying out above-mentioned layout process in the prior art, generally see through the layout slip-stick artist and carry out the configuration of electronic component with manual type, so that one by one with the tram of electronic component arrangements in the printed circuit board (PCB), so will make the tediously long and inefficiency of layoutprocedure of electronic component.
In addition, because the function of general printed circuit board (PCB) is various, the quantity of the electronic component of its required configuration is also various relatively, for example be hundreds of or even thousands of dissimilar electronic components, therefore can increase the probability that the layout slip-stick artist makes a mistake in layout process, and cause the mistake of configuration electronic component.And, when follow-up electronic component to institute's layout is checked and need make amendment replacing for wrong electronic component to check, will spend layout slip-stick artist more time and energy.
For overcoming the caused defective of above-mentioned manual configuration electronic component, some layout softwares can provide the function of autoplacement now, but in whole printed circuit board (PCB), there are a lot of drawbacks in the automatic configuration of element, therefore still need be adjusted and revise and check with manual mode by the layout slip-stick artist, and cause the reduction of work efficiency.
Summary of the invention
The invention provides a kind of layout method of circuit board,, thereby increase work efficiency with saving layout slip-stick artist's working time.
The present invention proposes a kind of layout method of circuit board, comprises the following steps: at first, sets up an element group, and wherein said element group comprises a major component and a plurality of secondary element relevant with described major component function; Then, set the first surface that described major component is configured in described circuit board; Afterwards, one of them moves to the described first surface of described circuit board with described a plurality of secondary elements; Then, judge whether one of them wire length of described major component and described a plurality of secondary element is less than or equal to a preset length; Afterwards, if described wire length is less than or equal to described preset length, then dispose described secondary element at described first surface; Then, if described wire length greater than described preset length, is then removed described secondary element at first surface; Afterwards, select as yet the not secondary element of configuration, and get back to that one of them moves to the step of the described first surface of described circuit board with described a plurality of secondary elements, finish up to all secondary arrangements of components.
In one embodiment of this invention, the step that disposes described secondary element at described first surface also comprises: with an adjacent elements predeterminable range at interval, dispose described secondary element at described first surface.
In one embodiment of this invention, the step of removing described secondary element at described first surface comprises: described secondary element is moved to a second surface of described circuit board, and be positioned at the back side of described major component.
In one embodiment of this invention, described secondary element is moved to a second surface of described circuit board, and the step that is positioned at the back side of described major component also comprises the following steps: at first afterwards, judges whether the wire length of described secondary element and described major component is less than or equal to described preset length; Then, if described wire length is less than or equal to described preset length, then dispose described secondary element at second surface; Afterwards, if described wire length is greater than described preset length, then remove described secondary element at second surface, the secondary element of going forward side by side and not disposing as yet into selection, and get back to that one of them moves to the step of the described first surface of described circuit board with described a plurality of secondary elements, the step of finishing up to all secondary arrangements of components.
In one embodiment of this invention, the step that disposes described secondary element at described second surface also comprises: with an adjacent elements predeterminable range at interval, dispose described secondary element at described second surface.
In one embodiment of this invention, described circuit board is a printed circuit board (PCB).
The present invention is created as element group by major component and the secondary element that function is relevant, and utilize the wire length of major component and secondary element and preset length to compare, determining first surface or the second surface of secondary arrangements of components, and then accelerate the layout speed of circuit board at circuit board.Thus, present embodiment can reduce layout slip-stick artist's working time effectively, to promote its work efficiency.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and cooperate appended graphic being described in detail below.
Description of drawings
Fig. 1 is the layout method process flow diagram of the circuit board of one embodiment of the invention.
Fig. 2 is the configuration schematic diagram of the elements on circuit board of one embodiment of the invention.
Fig. 3 is the synoptic diagram of the element group of one embodiment of the invention.
Fig. 4 is the layout method process flow diagram of the circuit board of another embodiment of the present invention.Reference numeral:
S102～S116: each step of the layout method of the circuit board of one embodiment of the invention;
200: circuit board; 201: the first surface of circuit board 200;
301: major component; 310～315: secondary element;
S402～S422: each step of the layout method of the circuit board of another embodiment of the present invention.
Embodiment
Fig. 1 is the layout method process flow diagram of the circuit board of one embodiment of the invention.Fig. 2 is the configuration schematic diagram of the elements on circuit board of one embodiment of the invention.Fig. 3 is the synoptic diagram of the element group of one embodiment of the invention.In the present embodiment, for example (printed circuit board PCB) implements circuit board 200 with printed circuit board (PCB).Please merge with reference to Fig. 1～Fig. 3, in step S102, set up an element group, wherein element group comprises a plurality of secondary element 310,311,312,313,314,315 that major component 301 is relevant with described major component function, as shown in Figure 3.
The relation of above-mentioned major component 301 and secondary element 310～315 can at the designed layout of Electronics Engineer and the slip-stick artist of mechanism or mechanism map is pre-defined be finished.Therefore, the layout software can be set up out element group according to above-mentioned relation, so that carry out layout.Thus, present embodiment can avoid the layout slip-stick artist with manual type when the layout moving meter, omitted a certain element.In addition, in the present embodiment, describe with 6 secondary elements, but the invention is not restricted to this.
Then, in step S104, set the first surface 201 that major component 301 is configured in circuit board 200.Afterwards, in step S106, one of them moves to the first surface 201 of circuit board 200 with described a plurality of secondary elements (being secondary element 310～315).For instance, secondary element 310 is moved to the first surface 201 of circuit board 200.
Then, in step S108, judge whether the major component 301 and the wire length (netlength) of secondary element 310 are less than or equal to preset length.For instance, the wire length of major component 301 and secondary element 310 for example is the length between two pins (pin pair) of the line that is connected major component 301 and secondary element 310, and preset length for example is 1000 Mills (mil), but the invention is not restricted to this, the visual demand of user is adjusted voluntarily.
If the length of described line is less than or equal to preset length (1000 Mill), then enter step S110, secondary element 310 is configured on the first surface 201 of circuit board 200.The situation that can not overlap for the secondary element that present embodiment is disposed, therefore, in this step S110, can with secondary element 310 adjacent elements predeterminable range at interval, at the secondary element 310 of first surface 201 configurations.In the present embodiment, above-mentioned predeterminable range is 5 Mills for example, but the invention is not restricted to this, and the visual demand of user is adjusted voluntarily.
On the other hand, if the length of described line is greater than preset length (1000 Mill), then enter step S112, remove secondary element 310 at the first surface 201 of circuit board 200, that is to say, secondary element 310 can not be configured in the first surface 201 of circuit board 200, but is configured in other parts of circuit board 200.
After step S110 or step S112 are finished, can enter into step S114, judge promptly whether all secondary arrangements of components are finished.If judged result is for being then to finish the layout method of present embodiment.On the other hand, if judged result is for denying, represent that then still having secondary element not dispose finishes, so then enter among the step S116, the secondary element (being secondary element 311～315) that selection is not disposed as yet, and get back among the step S 106, so that one of them moves to the first surface 201 of circuit board 200 with secondary element 311～315.Then, continue to carry out steps such as step S108, S110, S112, S114, S116, all dispose up to all secondary elements and finish, promptly finish the layout method of present embodiment.Thus, present embodiment can reduce layout slip-stick artist's working time effectively, to increase work efficiency.
In order more clearly to describe each step of above-mentioned layout method, below the detailed process of layout method of the present invention is described for an embodiment again.Fig. 4 is the layout method process flow diagram of the circuit board of another embodiment of the present invention.In the present embodiment, the embodiment of step S402, S404, S406, S408, S410, S420, S422 can be with reference to the embodiment of step S102, the S104 of Fig. 1, S406, S108, S110, S114, S116, so do not repeat them here.
After execution in step S408, if judge that described wire length is greater than preset length (for example 1000 Mills), then enter step S412, secondary element (for example among Fig. 2 with the secondary element 313 shown in the dotted line) is moved to the second surface (not shown) of circuit board 200, and be positioned at the back side of major component 301.
Then, in step S414, judge whether the secondary element 313 and the wire length of major component are less than or equal to preset length.If judge that described wire length is less than or equal to preset length, then execution in step S416 promptly disposes secondary element 313 at the second surface of circuit board 200.The situation that can not overlap for the secondary element that present embodiment is disposed, therefore, in this step S110, can with secondary element 313 adjacent elements predeterminable range at interval, and dispose secondary element 313 at the second surface of circuit board 200.
On the other hand, if judge described wire length greater than described preset length, then execution in step S418 promptly removes described secondary element 313 at the second surface of circuit board 200.After execution in step S416 or step S418, can enter into step S420, judge whether all secondary arrangements of components are finished.If judged result is for being then to finish the layout flow process of present embodiment.In addition, if judged result is not, then execution in step S422 selects as yet the not secondary element of configuration.Afterwards, execution in step S406, S408, S410, S412, S414, S416, S418, S420, S422 dispose up to all secondary elements and to finish.Thus, present embodiment can reduce layout slip-stick artist's working time effectively, to increase work efficiency.
As seen from Figure 2, behind the layout method of carrying out present embodiment, the first surface 201 of circuit board 200 can dispose major component 301, secondary element 310,311,314,315, and the second surface (not shown) of circuit board 200 can dispose secondary element 313 (being represented by dotted lines).Secondary element 312 is not configured on the first surface 201 and second surface of circuit board 200, also just expression, secondary element 312 does not meet the condition of present embodiment layout method, therefore, the layout software of present embodiment can be put back to secondary element 312 in the component library, and mode that can high brightness (highlight) shows, to inform that the layout slip-stick artist needs be configured secondary element 312 in addition.Thus, can reduce the time of layout engineer inspection arrangements of components effectively, to increase work efficiency.
In sum, the present invention is created as element group by major component and the secondary element that function is relevant, and utilize the wire length of major component and secondary element and preset length to compare, determining first surface or the second surface of secondary arrangements of components, and then accelerate the layout speed of circuit board at circuit board.Thus, present embodiment can reduce layout slip-stick artist's working time effectively, promoting its work efficiency, and can avoid the layout slip-stick artist with manual type when the layout moving meter, the configuration of having omitted a certain element.
Though the present invention discloses as above with embodiment; but it is not in order to limit the present invention; any person of ordinary skill in the field; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that accompanying Claim defines.
Claims (6)
1. the layout method of a circuit board is characterized in that, the layout method of described circuit board comprises:
Set up an element group, wherein said element group comprises a major component and a plurality of secondary element relevant with described major component function;
Set the first surface that described major component is configured in described circuit board;
One of them moves to the described first surface of described circuit board with described a plurality of secondary elements; Judge whether one of them wire length of described major component and described a plurality of secondary element is less than or equal to a preset length;
If described wire length is less than or equal to described preset length, then dispose described secondary element at described first surface;
If described wire length greater than described preset length, is then removed described secondary element at described first surface; And
Select as yet the not secondary element of configuration, and get back to that one of them moves to the step of the described first surface of described circuit board with described a plurality of secondary elements, finish up to all secondary arrangements of components.
2. the layout method of circuit board according to claim 1 is characterized in that, the step that disposes described secondary element at described first surface also comprises:
With with an adjacent elements predeterminable range at interval, dispose described secondary element at described first surface.
3. the layout method of circuit board according to claim 1 is characterized in that, the step of removing described secondary element at described first surface comprises:
Described secondary element is moved to a second surface of described circuit board, and be positioned at the back side of described major component.
4. the layout method of circuit board according to claim 3 is characterized in that, described secondary element is moved to a second surface of described circuit board, and also comprises after being positioned at the step at the back side of described major component:
Whether the wire length of judging described secondary element and described major component is less than or equal to described preset length;
If described wire length is less than or equal to described preset length, then dispose described secondary element at second surface; And
If described wire length is greater than described preset length, then remove described secondary element at second surface, the secondary element of going forward side by side and not disposing as yet into selection, and get back to that one of them moves to the step of the described first surface of described circuit board with described a plurality of secondary elements, the step of finishing up to all secondary arrangements of components.
5. the layout method of circuit board according to claim 4 is characterized in that, the step that disposes described secondary element at described second surface also comprises:
With with an adjacent elements predeterminable range at interval, dispose described secondary element at described second surface.
6. the layout method of circuit board according to claim 1 is characterized in that, described circuit board is a printed circuit board (PCB).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010198993XA CN102270250A (en) | 2010-06-04 | 2010-06-04 | Layout method of circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010198993XA CN102270250A (en) | 2010-06-04 | 2010-06-04 | Layout method of circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102270250A true CN102270250A (en) | 2011-12-07 |
Family
ID=45052555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010198993XA Pending CN102270250A (en) | 2010-06-04 | 2010-06-04 | Layout method of circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102270250A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979503A (en) * | 2005-12-09 | 2007-06-13 | 英业达股份有限公司 | Circuit-board laying-out method |
| JP2008004796A (en) * | 2006-06-23 | 2008-01-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and circuit element layout method |
| TW200825818A (en) * | 2006-12-07 | 2008-06-16 | Inventec Corp | Component designing system and method |
| CN101539955A (en) * | 2008-03-20 | 2009-09-23 | 英业达股份有限公司 | Layout method for circuit design |
-
2010
- 2010-06-04 CN CN201010198993XA patent/CN102270250A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1979503A (en) * | 2005-12-09 | 2007-06-13 | 英业达股份有限公司 | Circuit-board laying-out method |
| JP2008004796A (en) * | 2006-06-23 | 2008-01-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and circuit element layout method |
| TW200825818A (en) * | 2006-12-07 | 2008-06-16 | Inventec Corp | Component designing system and method |
| CN101539955A (en) * | 2008-03-20 | 2009-09-23 | 英业达股份有限公司 | Layout method for circuit design |
Non-Patent Citations (1)
| Title |
|---|
| 张琳: "印刷电路板设计中的布局与布线", 《赤峰学院学报》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7562326B2 (en) | Method of generating a standard cell layout and transferring the standard cell layout to a substrate | |
| CN103812502A (en) | Programmable integrated circuits with redundant circuitry | |
| CN102592000B (en) | Circuit board wiring detection system | |
| JP5586325B2 (en) | Wire harness continuity inspection method and wire harness continuity inspection program | |
| CN103970959A (en) | Circuit board wiring method and system | |
| CN103870617B (en) | Low frequency chip automatic placement and routing method | |
| CN101201864A (en) | System and method for laying element | |
| CN105278938A (en) | Chip integration method and apparatus | |
| CN108897933A (en) | A kind of method of quick elimination antenna effect | |
| JP2011034291A (en) | Design method, design program and design support device for semiconductor integrated circuit, and semiconductor integrated circuit | |
| CN102270250A (en) | Layout method of circuit board | |
| CN109492273B (en) | Automatic punching method based on through hole | |
| CN101866373A (en) | Execution monitor for electronic design automation | |
| US10540463B1 (en) | Placement of delay circuits for avoiding hold violations | |
| CN102314530B (en) | Interactive type hierarchical short circuit tracing and dynamic debugging method | |
| JP2008053606A (en) | Layout method and layout program of semiconductor device | |
| CN102789509B (en) | A kind of mark does not weld the method and system of device | |
| CN101271481B (en) | Through-hole component auxiliary arranging system and method | |
| US20130061194A1 (en) | Layout method, layout apparatus, and program for semiconductor integrated circuit | |
| JP2011109025A (en) | Method and apparatus for automatically disposing cells for semiconductor integrated circuit, and program therefor | |
| KR102062277B1 (en) | Method for simulating product time in smt process | |
| JP3125759B2 (en) | Automatic design system, method and recording medium | |
| CN114492256B (en) | Integrated circuit digital back-end ECO method, system and computer storage medium | |
| CN103164565A (en) | Method for automatically forming antenna regular test vectors | |
| CN117291140B (en) | Method and device for reducing winding violations of automatic wiring tool, storage medium and electronic terminal |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20111207 |