CN1979503A - Circuit-board laying-out method - Google Patents
Circuit-board laying-out method Download PDFInfo
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- CN1979503A CN1979503A CN 200510127486 CN200510127486A CN1979503A CN 1979503 A CN1979503 A CN 1979503A CN 200510127486 CN200510127486 CN 200510127486 CN 200510127486 A CN200510127486 A CN 200510127486A CN 1979503 A CN1979503 A CN 1979503A
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Abstract
The invention is a circuit board layout method, comprising the steps of: providing a circuit diagram; establishing and storing electronic components and their attribute parameters in a database; drawing the attribute parameters the circuit diagram indicates from the database and inserting the attribute parameters of electronic components in the circuit diagram in the indication positions of the circuit diagram; when converting a circuit diagram into a circuit layout diagram, a designer obtains sizes, pin positions and connection relations of electronic components and other graphic data at the time of circuit layout design according to the attribute parameters of electronic components in the circuit diagram. And the invention benefits circuit layout design, raising layout efficiency and reducing artificial mistakes.
Description
Technical field
The invention relates to a kind of circuit-board laying-out method,, provide the needs of configuration particularly about a kind of method in wiring diagram electronic component one embedded graphic attribute parameter.
Background technology
The electronic installation of function admirable, except selecting high-quality electronic component and rational circuit, the impedance that the layout of printed circuit board component and circuit connect etc. also are the factors that influences this electronic installation quality; For the circuit that has with a kind of element and parameter, because component placement (layout) design and circuit connect difference, have different resistance values, and impedance magnitude influences signal transmission and control stiffness.Therefore, how to reduce the impedance that configuration produces, eliminate the noise of the improper generation of wiring, the installation in helping producing, debugging and maintenance etc. have become an important ring in electronic industry.
Lay electronic component and configuration on circuit board, layout design engineers in the past is arranged in electronic component on the circuit board earlier according to wiring diagram, and then carries out the circuit connection according to the annexation of electronic component.Simple and the bigger circuit design of board area of prior function can directly convert wiring diagram to the layout circuit of circuit board according to said method, but along with development in science and technology is rapid, present electronic apparatus functions is quite complete and powerful, circuit board develops into now multilayer circuit board by in the past individual layer wiring board, make the configuration design become increasingly complex and difficulty, the number of electronic components that connects develops thousands of by previous dozens of, may derive in the future to up to ten thousand.Therefore the time of circuit layout designs consume more and more longer, and the factor amount is huge and be difficult to discharging and wiring; How the huge electronic component of quantity is emitted on the circuit board, rely on the experience accumulation of layout designer,, therefore must constantly revise electronic component discharging position and reach layout again in case the discharging mistake can influence follow-up configuration, to expend the quite long working time like this, efficient is reduced.
Fig. 1 is the flow process of available circuit layout, at first, as step S11, provides a wiring diagram earlier; Then as step S12, layout designer is placed in electronic component in the area of circuit board setting according to wiring diagram, and the putting position of this electronic component is put each electronic component according to deviser's experience with manual mode; Then as step S13,, finish configuration figure according to the line design layout that goes between; As step S14, figure is made into printed circuit board (PCB) according to configuration afterwards; Last as step S15, carry out debug (debug) operation, if layout is correctly then finish the layout operation, otherwise, get back to step S12, put electronic component again.
More than each step all used special purpose computer software as auxiliary, as design circuit software (ConceptHDL) and wiring software (Allegro) etc., if but from the process of circuit board integral layout operation, because the electronic component layout all relies on electronic design engineering teacher's layout experience, disposes with manual mode; If on circuit board, dispose the huge electronic component of quantity with manual mode, can quite waste time and energy, do not meet economic benefit, and following shortcoming is arranged: (1) electronic component disposes with manual mode, necessary extreme care is careful, in the process of the huge electronic component of configuration quantity, this electronic design engineering teacher can neglect the situation of omission unavoidably; If with passive device or related elements mismatch position or disposed far, can cause debug time lengthening, more serious will causing can't the debug reparation, makes the design cycle elongate.(2) after the electronic design engineering teacher finishes the partial circuit layout, if just run into the electronic component specification change of using in this circuit board, in the time of must changing the allocation position of element, for the electronic design engineering teacher, therefore necessary redesign will expend the longer time and energy is made amendment.
Therefore, design one cover can be simplified the also method of accelerated electron design engineer layout work flow process, existing its necessity.
Summary of the invention
For overcoming the shortcoming of above-mentioned prior art, fundamental purpose of the present invention is to provide a kind of circuit-board laying-out method, reaches the effect that improves positioning efficiency.
A further object of the present invention is to provide a kind of circuit-board laying-out method, reaches the effect that reduces the human error rate.
For achieving the above object, the invention provides a kind of circuit-board laying-out method, this circuit-board laying-out method comprises the following steps: that (1) provides a wiring diagram; (2) database is set up and be stored in to electronic component and property parameters thereof; (3) take out the property parameters of electronic component that this wiring diagram indicates from database; And (4) embed the property parameters of electronic component in the wiring diagram marker location of this wiring diagram electronic component.
This property parameters is the figure of electronic component shape, pin spacing and position dimension, can comprise signal language and guiding term etc., is the favourable instrument of layout designer.
Foregoing circuit plate layout method also comprises: according to the property parameters of electronic component that this wiring diagram indicates, electronic component is emitted on a preliminary configuration (layout) figure; After then this electronic component arranges into preliminary configuration figure according to wiring diagram, go between at this preliminary configuration, finish this configuration figure according to wiring diagram; Be made into circuit board according to this configuration figure then; At last this circuit board is carried out debug (debug).
This circuit board is printed circuit board (PCB), base plate for packaging or multilayer circuit board; This electronic component is chipset, CPU (central processing unit), chip for driving, control chip, special applications chip or passive device, and wherein this passive device is resistor, capacitor, inductor or switch.
The module formed by a center part and a subsidiary component at least of this electronic component in the present invention, this center part is the element that is associated with subsidiary component, property parameters under this electronic component comprises: the size of the shape of center part and subsidiary component, pin spacing and position and annexation figure also can comprise signal language and guiding term etc.Provide the deviser directly the property parameters under this center part and the subsidiary component module to be taken out wiring in the lump, avoided choosing respectively the inconvenience that center part and subsidiary component bring to the deviser.
The deviser directly chooses the figure or the word attribute parameter of this electronic component according to the configuration of wiring diagram, as the foundation of configuration, has avoided existing method shortcoming of layout again after debug, has improved positioning efficiency and has reduced the human error rate.
Description of drawings
Fig. 1 is the layout process flow diagram of available circuit panel element;
Fig. 2 is a circuit-board laying-out method process flow diagram of the present invention;
Fig. 3 is the synoptic diagram of the property parameters wiring diagram of circuit-board laying-out method of the present invention; And
Fig. 4 is the center part of circuit-board laying-out method of the present invention and the synoptic diagram of subsidiary component property parameters.
Embodiment
Embodiment
Please consult Fig. 2 and Fig. 3 simultaneously, circuit-board laying-out method of the present invention comprises the following steps, shown in step S21, at first provides a circuit Figure 20; Then as step S22, set up its property parameters according to the electronic component 20a among this circuit Figure 20, and this electronic component 20a and affiliated property parameters 21 thereof be stored into a database, this electronic component 20a is chipset, CPU (central processing unit), chip for driving, control chip, special applications chip or passive device, and this passive device is resistor, capacitor, inductor or switch; As step S23, from database, take out the property parameters 21 that this circuit Figure 20 indicates electronic component 20a then; Afterwards shown in step S24, the property parameters 21 of electronic component 20a among this circuit Figure 20 is embedded into the position that electronic component 20a indicates among this circuit Figure 20, the figure of the shape that this property parameters 21 is electronic components, pin spacing and position dimension, or comprise the signal language of this electronic component and the literal of guiding term.
Then see also Fig. 2, shown in step S25, electronic component that this wiring diagram indicates is emitted on a preliminary configuration (layout) figure according to its property parameters; Then shown in step 26, this electronic component goes between at this preliminary configuration by wiring diagram after arranging into preliminary configuration figure according to wiring diagram, finishes this configuration figure; Shown in step 26, figure is made into circuit board according to this configuration then; At last, shown in step 27, this circuit board is carried out debug (debug), if do not have any mistake after the debug then finish configuration, wherein this circuit board is printed circuit board (PCB), base plate for packaging or multilayer circuit board.
When the deviser converts configuration figure to by circuit Figure 20, can directly obtain shape, pin position and the position equidimension figure of this electronic component 20a from the electronic component 20a circuit Figure 20, be applied on the configuration figure, all related datas and prompting can obtain simultaneously, avoid occurring design mistake, improved positioning efficiency.
In configuration, this property parameters 21 provides various parameters to use for configuration, thereby reduces the mistake that human error causes, and shortens the time of topological design, reduces again the time of the waste of layout.
See also Fig. 4, in circuit design, the electronic component electronic component that must arrange in pairs or groups simultaneously and be associated partly, therefore will main center part 41 and relevant on every side subsidiary component 42 layouts after be created as same module, this module has the property parameters of this center part 41 and subsidiary component 42 simultaneously; Property parameters under this electronic component comprises: the figure of the shape of center part and subsidiary component, pin spacing and position dimension and annexation, or signal language and guiding term literal etc.; This center part 41 is chipset, CPU (central processing unit), chip for driving, control chip or special applications chip, and this subsidiary component 42 is resistor, capacitor, inductor or switch.
The deviser if use identical electronic component, can directly choose the module with center part 41 and subsidiary component 42 when next configuration, need not be once more layout again; Can save the configuration time.If the electronic design engineering teacher is after carrying out circuit-board laying-out at every turn, all emerging electronic component and relevant subsidiary component thereof are created as same module on every side, and deposit database in, in the future or other slip-stick artist's use, have very great help.
In addition, the property parameters of same module will be created as after electronic component and the relevant on every side subsidiary component layout thereof, the functional attributes of electronic component and subsidiary component can be established in the lump in the property parameters of module, when electronic design engineering Shi Jinhang component placement, can clear recognize the functional attributes and the corresponding relation thereof of element, make the function of its detail knowledge integral module.
In sum, circuit-board laying-out method of the present invention is by setting up the mode of module, and the circuit that layout is once crossed stores, help use in the future, the electronic design engineering teacher does not need the identical circuit of repetition layout, can save time, and reduces the probability that error takes place.
Claims (15)
1. a circuit-board laying-out method is characterized in that, this circuit-board laying-out method comprises the following steps:
(1) provides a wiring diagram;
(2) database is set up and be stored in to electronic component and property parameters thereof;
(3) take out the property parameters of electronic component that this wiring diagram indicates from database; And
(4) property parameters of electronic component in the wiring diagram is embedded the marker location of this wiring diagram electronic component.
2. circuit-board laying-out method as claimed in claim 1 is characterized in that, this circuit-board laying-out method also comprises: the property parameters according to electronic component that this wiring diagram indicates is emitted on a preliminary configuration figure with electronic component.
3. circuit-board laying-out method as claimed in claim 2, it is characterized in that, this circuit-board laying-out method also comprises: this electronic component goes between in this preliminary configuration according to wiring diagram after arranging into preliminary configuration figure according to wiring diagram, finishes this configuration figure.
4. circuit-board laying-out method as claimed in claim 3 is characterized in that, this circuit-board laying-out method also comprises: be made into circuit board according to this configuration figure.
5. circuit-board laying-out method as claimed in claim 4 is characterized in that, this circuit-board laying-out method also comprises: this circuit board is carried out debug.
6. circuit-board laying-out method as claimed in claim 1 is characterized in that, this property parameters is the figure of shape, pin spacing and the position dimension of electronic component.
7. circuit-board laying-out method as claimed in claim 1 is characterized in that, this property parameters also comprises the literal of this electronic component signal language and guiding term.
8. circuit-board laying-out method as claimed in claim 4 is characterized in that, this circuit board is printed circuit board (PCB), base plate for packaging or multilayer circuit board.
9. circuit-board laying-out method as claimed in claim 1 is characterized in that, this electronic component is made up of a center part and a subsidiary component at least.
10. circuit-board laying-out method as claimed in claim 9 is characterized in that, the property parameters under this electronic component comprises: the figure of the shape of center part and subsidiary component, pin spacing and position dimension and annexation.
11. circuit-board laying-out method as claimed in claim 10 is characterized in that, this property parameters also comprises the literal of this electronic component signal language and guiding term.
12. circuit-board laying-out method as claimed in claim 9 is characterized in that, this center part is chipset, CPU (central processing unit), chip for driving, control chip or special applications chip.
13. circuit-board laying-out method as claimed in claim 9 is characterized in that, this subsidiary component is resistor, capacitor, inductor or switch.
14. circuit-board laying-out method as claimed in claim 1 is characterized in that, this electronic component is chipset, CPU (central processing unit), chip for driving, control chip, special applications chip or passive device.
15. circuit-board laying-out method as claimed in claim 14 is characterized in that, this passive device is resistor, capacitor, inductor or switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510127486 CN1979503A (en) | 2005-12-09 | 2005-12-09 | Circuit-board laying-out method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510127486 CN1979503A (en) | 2005-12-09 | 2005-12-09 | Circuit-board laying-out method |
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| Publication Number | Publication Date |
|---|---|
| CN1979503A true CN1979503A (en) | 2007-06-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200510127486 Pending CN1979503A (en) | 2005-12-09 | 2005-12-09 | Circuit-board laying-out method |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373489B (en) * | 2007-08-23 | 2010-06-16 | 英业达股份有限公司 | System for switching laying bedding plane of signal line |
| CN101996268A (en) * | 2009-08-20 | 2011-03-30 | 鸿富锦精密工业（深圳）有限公司 | Circuit wiring system and method |
| CN101426360B (en) * | 2007-10-31 | 2011-07-27 | 松下电器产业株式会社 | Method for mounting elements on printed circuit board by surface mounting machine |
| CN102270250A (en) * | 2010-06-04 | 2011-12-07 | 英业达股份有限公司 | Layout method of circuit board |
| CN102346786A (en) * | 2010-07-29 | 2012-02-08 | 鸿富锦精密工业（深圳）有限公司 | Signal line inspection system and method |
| CN102567553A (en) * | 2010-12-23 | 2012-07-11 | 研华股份有限公司 | Design guiding system and method for circuit board layout rule |
| CN102652316A (en) * | 2009-12-11 | 2012-08-29 | 新思科技有限公司 | Optical proximity correction aware integrated circuit design optimization |
| CN103678812A (en) * | 2013-12-18 | 2014-03-26 | 上海森松制药设备工程有限公司 | Accurate plotting method of engineering drawing |
| CN104918412A (en) * | 2015-06-09 | 2015-09-16 | 广西大学 | Circuit board layout method and device |
| CN108430154A (en) * | 2018-03-21 | 2018-08-21 | 珠海格力电器股份有限公司 | A kind of layout method and device of circuit board |
| CN109388821A (en) * | 2017-08-08 | 2019-02-26 | 富比库股份有限公司 | System and method is configured with the electronic component pattern that circuit layout system cooperates |
-
2005
- 2005-12-09 CN CN 200510127486 patent/CN1979503A/en active Pending
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101373489B (en) * | 2007-08-23 | 2010-06-16 | 英业达股份有限公司 | System for switching laying bedding plane of signal line |
| CN101426360B (en) * | 2007-10-31 | 2011-07-27 | 松下电器产业株式会社 | Method for mounting elements on printed circuit board by surface mounting machine |
| CN101996268A (en) * | 2009-08-20 | 2011-03-30 | 鸿富锦精密工业（深圳）有限公司 | Circuit wiring system and method |
| CN102652316A (en) * | 2009-12-11 | 2012-08-29 | 新思科技有限公司 | Optical proximity correction aware integrated circuit design optimization |
| CN102270250A (en) * | 2010-06-04 | 2011-12-07 | 英业达股份有限公司 | Layout method of circuit board |
| CN102346786A (en) * | 2010-07-29 | 2012-02-08 | 鸿富锦精密工业（深圳）有限公司 | Signal line inspection system and method |
| CN102567553A (en) * | 2010-12-23 | 2012-07-11 | 研华股份有限公司 | Design guiding system and method for circuit board layout rule |
| CN103678812A (en) * | 2013-12-18 | 2014-03-26 | 上海森松制药设备工程有限公司 | Accurate plotting method of engineering drawing |
| CN104918412A (en) * | 2015-06-09 | 2015-09-16 | 广西大学 | Circuit board layout method and device |
| CN104918412B (en) * | 2015-06-09 | 2017-10-10 | 广西大学 | The layout method and device of a kind of circuit board |
| CN109388821A (en) * | 2017-08-08 | 2019-02-26 | 富比库股份有限公司 | System and method is configured with the electronic component pattern that circuit layout system cooperates |
| CN109388821B (en) * | 2017-08-08 | 2022-12-09 | 富比库股份有限公司 | Electronic part pattern configuration system and method working in cooperation with circuit layout system |
| CN108430154A (en) * | 2018-03-21 | 2018-08-21 | 珠海格力电器股份有限公司 | A kind of layout method and device of circuit board |
| CN108430154B (en) * | 2018-03-21 | 2019-10-22 | 珠海格力电器股份有限公司 | A kind of layout method and device of circuit board |
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