CN115392159A - Integrated circuit layout design teaching auxiliary system - Google Patents
Integrated circuit layout design teaching auxiliary system Download PDFInfo
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- CN115392159A CN115392159A CN202211028641.9A CN202211028641A CN115392159A CN 115392159 A CN115392159 A CN 115392159A CN 202211028641 A CN202211028641 A CN 202211028641A CN 115392159 A CN115392159 A CN 115392159A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3323—Design verification, e.g. functional simulation or model checking using formal methods, e.g. equivalence checking or property checking
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q50/00—Systems or methods specially adapted for specific business sectors, e.g. utilities or tourism
- G06Q50/10—Services
- G06Q50/20—Education
Abstract
The invention discloses an integrated circuit layout design teaching auxiliary system, which comprises: the circuit diagram design unit is configured to create a circuit schematic diagram according to a circuit diagram creation instruction and send the generated circuit schematic diagram to the layout design unit; the layout design unit is configured to generate an initial layout at a layout design interface according to the received circuit schematic diagram, and perform layout design on the initial layout according to a layout design instruction to generate an integrated circuit layout; the error checking unit is configured to perform real-time error checking on the layout object in the layout design process and feed back the checked error information to the user. According to the invention, by carrying out real-time error check and feedback on the layout object in the layout design process, a user can conveniently check and modify errors, the error rate is reduced, the learning efficiency of the user is improved, and the learning period is shortened.
Description
Technical Field
The invention relates to the technical field of software systems, in particular to an integrated circuit layout design teaching auxiliary system.
Background
In the whole production flow of the integrated circuit, the layout design is also a key step as the back end design, and the reasonability of the layout design also determines whether the finally manufactured chip can realize the correct function. Wafer manufacturers formulate Rule Check files of symbol requirements according to different processes, and designers need to perform Rule Check (DRC) on layouts according to the Rule Check files.
An Electronic Design Automation (EDA) tool is a key tool for designing an integrated circuit, and EDA teaching is developed in major universities and universities in China for the micro-electronics major, the computer major, electronic information engineering, communication engineering and the like. The learning period of an EDA tool for designing an integrated circuit layout is long, the course progress is slow, the student cannot know DRC errors generated by the layout, the student cannot timely acquire the errors generated in the layout design learning, a plurality of errors must exist in the layout design, the student modifies the layout again according to the checked error information after the whole layout is designed, more time is wasted, and the learning efficiency is greatly reduced. .
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an auxiliary system for teaching integrated circuit layout design, which can transmit the error generated in the layout design process to the student in time through the function of real-time DRC error detection, so as to achieve the effects of reducing the error rate and improving the learning efficiency and quality of the student.
To achieve the above and other related objects, the present invention provides an integrated circuit layout teaching assistance system, comprising:
a circuit diagram design unit;
the layout design unit is connected with the circuit design unit;
the error checking unit is connected with the layout design unit;
the circuit diagram design unit is configured to create a circuit schematic diagram according to a circuit diagram creation instruction and send the generated circuit schematic diagram to the layout design unit;
the layout design unit is configured to generate an initial layout at a layout design interface according to the received circuit schematic diagram, and perform layout design on the initial layout according to a layout design instruction so as to generate an integrated circuit layout;
the error checking unit is configured to perform real-time error checking on the layout object in the layout design process and feed back the checked error information to the user in real time.
In an alternative embodiment of the present invention, the circuit diagram design unit includes:
a circuit diagram module configured to generate a circuit diagram drawing interface according to the circuit diagram creation instruction;
the device symbol creating module is configured to draw the circuit devices and the connection relations among the circuit devices on the circuit diagram drawing interface according to a circuit diagram drawing instruction of a user so as to generate the circuit schematic diagram;
and the circuit diagram output module is configured to send the generated circuit schematic diagram to the layout design unit.
In an optional embodiment of the present invention, the layout design unit includes:
the layout generating module is configured to generate the initial layout on the layout design interface according to the received circuit schematic diagram;
the layout design module is configured to carry out layout design on the initial layout according to a layout design instruction so as to generate an integrated circuit layout;
and the layout output module is configured to send layout data in the layout design process to the error checking unit in real time.
In an optional embodiment of the present invention, the layout design module is further configured to perform layout design on the initial layout according to a layout instruction, a routing instruction, or a punching instruction, so as to generate the integrated circuit layout.
In an optional embodiment of the present invention, the layout design module is further configured to correct the integrated circuit layout in the layout design process according to the layout correction instruction in the layout design process.
In an optional embodiment of the present invention, the error checking unit comprises an error checking module and an error information storage module;
the error checking module is configured to perform real-time error checking on the layout objects in the layout design process, feed the checked error information back to the user in real time, and associate and store the checked error information with the corresponding layout objects in the error information storage module.
In an optional embodiment of the present invention, the error checking unit further includes an error checking module, which is connected to the layout design unit and the error information storage module; the error checking module is configured to respond to a target layout object in an error checking instruction, and retrieve and display error information and a corresponding modification scheme of the target layout object from the error information storage module.
In an optional embodiment of the present invention, the error checking unit is further configured to perform error checking on the layout object selected by the user through the cursor during the layout design process, and feed back the checked error information to the user in real time
In an optional embodiment of the present invention, the error checking unit is configured to automatically load a corresponding layout design check rule file according to the selected process library to perform real-time error checking on the layout object in the layout design process, and feed back the checked error information to the user.
In an optional embodiment of the present invention, the layout design check rule file includes a via overlap check rule file and/or a parallel trace pitch check rule file.
The integrated circuit layout design teaching auxiliary system can timely transmit errors generated in the layout design process to students through the real-time DRC error detection function, so that the effects of reducing the error rate and improving the learning efficiency and the learning quality of the students can be achieved.
The integrated circuit layout design teaching auxiliary system has the advantages of less computer occupied resources, clear and smooth graphical interface and is more suitable for entrance-level students to learn.
Drawings
Fig. 1 is an integrated circuit layout design teaching assistance system according to an embodiment of the present invention.
Fig. 2 is a schematic view of checking the overlapping width of the through-hole.
Fig. 3 is a schematic diagram of the inspection of the wiring.
Fig. 4 is a flowchart of integrated circuit layout design using the integrated circuit layout design teaching assistance system of the embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
In the description herein, numerous specific details are provided, such as examples of components and/or methods, to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Referring to fig. 1, an embodiment of the present invention discloses an integrated circuit layout design teaching assistance system, which includes a circuit diagram design unit 1, a layout design unit 2, and an error check unit 3, where the circuit diagram design unit 1 is connected to the layout design unit 2, and the layout design unit 2 is connected to the error check unit 3. The integrated circuit layout Design teaching assistance system of this embodiment is an Electronic Design Automation (EDA) tool for short.
The circuit diagram design unit 1 is configured to create a circuit schematic diagram according to a circuit diagram creation instruction, and send the generated circuit schematic diagram to the layout design unit 2; the layout design unit 2 is configured to generate an initial layout at a layout design interface according to the received circuit schematic, and perform layout design on the initial layout according to a layout design instruction to generate an integrated circuit layout; the error checking unit 3 is configured to perform real-time error checking on the layout object in the layout design process, and feed back the checked error information to the user in real time.
As shown in fig. 1, in the present embodiment, the circuit diagram design unit 1 includes a circuit diagram module 11, a device symbol creation module 12, and a circuit diagram output module 13. The circuit diagram module 11 is configured to generate a circuit diagram drawing interface according to the circuit diagram creation instruction; the device symbol creating module 12 is configured to draw circuit devices and connection relationships between the circuit devices on the circuit diagram drawing interface according to a circuit diagram drawing instruction of a user to generate the circuit schematic diagram; the circuit diagram output module 13 is configured to send the generated circuit schematic diagram to the layout design unit 2.
When the integrated circuit layout design teaching assistance system of this embodiment is used to create a circuit schematic diagram, a user may click a circuit diagram creation button on a system working interface to generate a circuit diagram creation instruction, the circuit diagram module 11 receives the circuit diagram creation instruction to generate a circuit diagram drawing interface (also referred to as a circuit diagram drawing window), and the user may enter a corresponding input instruction on the circuit diagram drawing interface to call the device symbol creation module 12; a user can select a required device through the device symbol creation module 12, specify a placement position and a connection mode, draw the circuit schematic diagram on a circuit diagram drawing interface, automatically name the device and the connection when the circuit schematic diagram is manufactured, and automatically match the information when the circuit schematic diagram is led out to the layout design unit 2, so that the layout and the wiring of a layout are convenient for the user; after the circuit schematic diagram is drawn, the generated circuit schematic diagram can be sent to the layout generating module 21 in the layout design unit 2 through the circuit diagram output module 13.
As shown in fig. 1, in this embodiment, the layout design unit 2 includes a layout generation module 21, a layout design module 22 and a layout output module 23. The layout generating module 21 is configured to generate the initial layout at the layout design interface according to the received circuit schematic diagram; the layout design module 22 is configured to perform layout design on the initial layout according to layout design instructions to generate an integrated circuit layout; the layout output module 23 is configured to send layout data in the layout design process to the error check unit 3 in real time. The layout design instruction may include, for example, a layout instruction, a wiring instruction, or a punching instruction, that is, the layout design module 22 may perform layout design on the initial layout according to the layout instruction, the wiring instruction, or the punching instruction, so as to generate the integrated circuit layout.
In this embodiment, the layout design module 22 is further configured to, during the layout design process, perform real-time correction on the integrated circuit layout during the layout design process according to the layout correction instruction.
When the integrated circuit layout design teaching assistance system of this embodiment is used to design an integrated circuit layout, the layout generation module 21 may generate the initial layout at the layout design interface according to the received circuit schematic; a user can utilize the layout design module 22 to configure layout design such as layout, wiring and punching on the initial layout to generate an integrated circuit layout, and in the integrated circuit layout design process, the layout output module 23 can send layout data in the layout design process to the error check unit 3 in real time to perform DRC error check; when the checking unit detects the layout DRC error, the layout DRC error information is fed back to a user, and the user can correct the integrated circuit layout in the layout design process in real time according to the layout DRC error information, so that the learning period of the user can be shortened, and the learning efficiency of the user is improved.
In this embodiment, when performing error check, the error check unit 3 may automatically load the corresponding layout design check rule file according to the selected process library to perform real-time error check on the layout object in the layout design process, and feed back the checked error information to the user, and when performing error check, the error check unit 3 may, for example, determine whether the layout object violates the check rule in the corresponding rule check file, where the layout design check rule file includes the through hole overlap check rule file and/or the parallel trace pitch check rule file. It is understood that, in other embodiments, the layout design check rule file may also include other check rule files.
The through-hole overlap check rule file may be, for example, a rule check that determines whether all through-hole overlap widths are greater than or equal to a first preset value. As shown in fig. 2, if the overlap width of the via penetrating through the metal layer 1 and the metal layer 2 is defined as d2, and if d2 is smaller than d1 (a first preset value), it is determined that the check rule violates the via overlap check rule file, that is, there is a DRC error in which the via overlap width is too small in the layout design.
The parallel trace pitch check rule file may be, for example, a check rule that determines whether the pitch between the parallel traces is greater than or equal to a second preset value. As shown in fig. 3, an actual distance d4 between the trace 1 and the trace 2 is defined, and if it is determined that d4 is smaller than d3 (a second preset value), it represents that the check rule of the parallel trace pitch check rule file is violated, that is, there is a DRC error in which the trace pitch is too small in the layout design.
By way of example, the system provides the user with the SMIC 55nm and SMIC180nm process libraries and corresponding rule check files, which is convenient for the user to learn, although the user may add other process libraries and corresponding rule check files.
As shown in fig. 4, in the present embodiment, the error checking unit 3 includes an error checking module 31 and an error information storage module 32; the error checking module 31 is configured to perform real-time error checking on the layout objects in the layout design process, feed back the checked error information to the user in real time, and associate and store the checked error information with the corresponding layout objects in the error information storage module 32.
As shown in fig. 1, in this embodiment, the error checking unit 3 further includes an error checking module 33, and the error checking module 33 is connected to the layout design unit 2 and the error information storage module 32; the error checking module 33 is configured to, in response to a target layout object in an error checking instruction, retrieve and display error information of the target layout object and a corresponding preset modification scheme from the error information storage module 32. The error checking module 33 can realize real-time error information checking and modify the error information according to a corresponding preset modification scheme, so that the learning efficiency is improved.
It should be noted that, in the integrated circuit layout design teaching assistance system of this embodiment, the error checking unit 3 can provide three error checking modes: one is that in the layout design process mentioned above, the layout object is checked for errors in real time, and the checked error information is fed back to the user in real time; secondly, in the layout design process, the layout object selected by the user through a cursor or other modes is subjected to error check, and the checked error information is fed back to the user in real time, namely, the user can select wiring, through holes and the like through the cursor or other modes to carry out error check in the layout wiring process; the third is DRC error checking after the entire integrated circuit layout design is completed.
The integrated circuit layout design teaching auxiliary system can meet the basic requirements of student layout learning, greatly reduces error rate and learning period, and greatly improves learning efficiency of users.
Fig. 2 is a flowchart showing integrated circuit layout design using the integrated circuit layout design teaching assistance system according to the embodiment of the present invention. As shown in fig. 2, when a user (e.g., a student) designs an integrated circuit layout by using the integrated circuit layout design teaching assistance system according to the embodiment of the present invention, the user may first build a circuit schematic diagram by using the circuit diagram design unit 1, and then generate an initial layout by using the circuit diagram design unit 1 according to the built circuit schematic diagram; and then, drawing the layout by performing operations of layout movement, wiring, punching and the like on the initial layout, performing DRC error correction in real time in the process of drawing the layout, modifying and correcting the layout when the layout is judged to have errors, and otherwise, finishing the DRC error correction process.
In summary, the integrated circuit layout design teaching assistance system of the embodiment of the invention can timely transmit the error generated in the layout design process to students through the real-time DRC error detection function, thereby achieving the effects of reducing the error rate and improving the learning efficiency and the learning quality of the students. The integrated circuit layout design teaching auxiliary system provided by the embodiment of the invention has the advantages of less computer occupied resources, clear and smooth graphical interface, chinese interface and suitability for entrance-level students to study.
Additionally, any reference arrows in the drawings/figures should be considered only as exemplary, and not limiting, unless otherwise expressly specified. Further, as used herein, the term "or" is generally intended to mean "and/or" unless otherwise indicated. Combinations of components or steps will also be considered as being noted where terminology is foreseen as rendering the ability to separate or combine is unclear.
The above description of illustrated embodiments of the invention, including what is described in the abstract of the specification, is not intended to be exhaustive or to limit the invention to the precise forms disclosed herein. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the present invention, as those skilled in the relevant art will recognize and appreciate. As indicated, these modifications may be made to the present invention in light of the foregoing description of illustrated embodiments of the present invention and are to be included within the spirit and scope of the present invention.
The systems and methods have been described herein in general terms as the details aid in understanding the invention. Furthermore, various specific details have been given to provide a general understanding of the embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
Thus, although the present invention has been described herein with reference to particular embodiments thereof, a latitude of modification, various changes and substitutions are intended in the foregoing disclosures, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope and spirit of the invention as set forth. Thus, many modifications may be made to adapt a particular situation or material to the essential scope and spirit of the present invention. It is intended that the invention not be limited to the particular terms used in following claims and/or to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include any and all embodiments and equivalents falling within the scope of the appended claims. Accordingly, the scope of the invention is to be determined solely by the appended claims.
Claims (10)
1. An integrated circuit layout design teaching assistance system, comprising:
a circuit diagram design unit;
the layout design unit is connected with the circuit design unit;
the error checking unit is connected with the layout design unit;
the circuit diagram design unit is configured to create a circuit schematic diagram according to a circuit diagram creation instruction and send the generated circuit schematic diagram to the layout design unit;
the layout design unit is configured to generate an initial layout at a layout design interface according to the received circuit schematic diagram, and perform layout design on the initial layout according to a layout design instruction to generate an integrated circuit layout;
the error checking unit is configured to perform real-time error checking on the layout object in the layout design process and feed back the checked error information to the user in real time.
2. The integrated circuit layout design teaching assistance system of claim 1 wherein the circuit diagram design unit comprises:
a circuit diagram module configured to generate a circuit diagram drawing interface according to the circuit diagram creation instruction;
the device symbol creating module is configured to draw the circuit devices and the connection relation among the circuit devices on the circuit diagram drawing interface according to a circuit diagram drawing instruction of a user so as to generate the circuit schematic diagram;
and the circuit diagram output module is configured to send the generated circuit schematic diagram to the layout design unit.
3. The integrated circuit layout design teaching assistance system of claim 1 wherein the layout design unit comprises:
the layout generating module is configured to generate the initial layout on the layout design interface according to the received circuit schematic diagram;
the layout design module is configured to carry out layout design on the initial layout according to a layout design instruction so as to generate an integrated circuit layout;
and the layout output module is configured to send layout data in the layout design process to the error checking unit in real time.
4. The integrated circuit layout design teaching assistance system of claim 3 wherein the layout design module is further configured to perform layout design on the initial layout according to a placement instruction, a routing instruction, or a punching instruction to generate an integrated circuit layout.
5. The integrated circuit layout design teaching assistance system of claim 3 wherein the layout design module is further configured to modify the integrated circuit layout during the layout design process according to the layout modification instruction during the layout design process.
6. The integrated circuit layout design teaching assistance system of claim 1 wherein the error checking unit comprises an error checking module and an error information storage module;
the error checking module is configured to perform real-time error checking on the layout objects in the layout design process, feed the checked error information back to the user in real time, and associate and store the checked error information with the corresponding layout objects in the error information storage module.
7. The integrated circuit layout design teaching assistance system of claim 6 wherein the error checking unit further comprises an error checking module connected to the layout design unit and the error information storage module; the error checking module is configured to respond to a target layout object in an error checking instruction, and retrieve and display error information and a corresponding modification scheme of the target layout object from the error information storage module.
8. The integrated circuit layout design teaching assistance system of claim 1 wherein the error checking unit is further configured to perform error checking on the layout object selected by the user via the cursor during the layout design process and to feed back the checked error information to the user in real time.
9. The integrated circuit layout design teaching assistance system of claim 1 wherein the error checking unit is configured to automatically load a corresponding layout design check rule file to perform real-time error checking on layout objects in the layout design process according to the selected process library, and to feed back the checked error information to the user.
10. The integrated circuit layout design teaching assistance system of claim 9 wherein the layout design check rule file comprises a via overlap check rule file and/or a parallel trace pitch check rule file.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116029258A (en) * | 2023-03-24 | 2023-04-28 | 深圳前海深蕾半导体有限公司 | Chip layout verification method, device, equipment and storage medium |
| CN116736061A (en) * | 2023-05-09 | 2023-09-12 | 珠海妙存科技有限公司 | Triode matching precision detection method, controller and storage medium |
| CN116757145A (en) * | 2023-08-16 | 2023-09-15 | 合肥奎芯集成电路设计有限公司 | Integrated circuit design layout processing method and device, electronic equipment and storage medium |
-
2022
- 2022-08-25 CN CN202211028641.9A patent/CN115392159A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116029258A (en) * | 2023-03-24 | 2023-04-28 | 深圳前海深蕾半导体有限公司 | Chip layout verification method, device, equipment and storage medium |
| CN116029258B (en) * | 2023-03-24 | 2023-06-06 | 深圳前海深蕾半导体有限公司 | Chip layout verification method, device, equipment and storage medium |
| CN116736061A (en) * | 2023-05-09 | 2023-09-12 | 珠海妙存科技有限公司 | Triode matching precision detection method, controller and storage medium |
| CN116757145A (en) * | 2023-08-16 | 2023-09-15 | 合肥奎芯集成电路设计有限公司 | Integrated circuit design layout processing method and device, electronic equipment and storage medium |
| CN116757145B (en) * | 2023-08-16 | 2024-04-30 | 合肥奎芯集成电路设计有限公司 | Integrated circuit design layout processing method and device, electronic equipment and storage medium |
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