CN108897933A - A kind of method of quick elimination antenna effect - Google Patents
A kind of method of quick elimination antenna effect Download PDFInfo
- Publication number
- CN108897933A CN108897933A CN201810616995.2A CN201810616995A CN108897933A CN 108897933 A CN108897933 A CN 108897933A CN 201810616995 A CN201810616995 A CN 201810616995A CN 108897933 A CN108897933 A CN 108897933A
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- antenna effect
- effect
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- wire jumper
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
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- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a kind of methods for quickly eliminating antenna effect, it is characterized in that, after carrying out the inspection of antenna component effect, a node of selection violation antenna effect first, according to the node actual antennas ratio, setting meets the metal layer length maximum value of antenna effect rule, carries out wire jumper, make it is modified after domain to meet antenna effect regular.Antenna effect rule can be met using the domain of method of the invention after modified, single can complete the antenna effect inspection and modification of the node, the significantly time spent when the antenna effect of compression check integrated circuit, so that entire circuit design flow is more efficiently, with visual inspection, facilitate edit operation.
Description
Technical field
The present invention relates to the inspection methods of integrated circuit diagram, more particularly to a kind of method for quickly eliminating antenna effect.
Background technique
In IC Chip Production manufacturing process, the metal wire or polysilicon conductor of floating technical process (such as
Plasma etching) in can image antenna equally collect charge.When metal wire or polysilicon conductor total length are larger and directly connect
When being connected to polysilicon gate, with the accumulation of its charge collected, voltage is also with raising, it is possible to puncture thin gate oxide,
This phenomenon is known as antenna effect, will affect chip yield, causes integrity problem.Antenna effect rule and antenna ratio by
Foundry manufacturer provides, the general area with the conductor (usually metal or polysilicon line) for constituting so-called " antenna " with
The ratio for the gate oxide area being connected defines, and " antenna ratio " (" antenna ratio ") measures a chips energy
The probability of antenna effect occurs.The method for preventing antenna effect on common domain has " jumper wiring " and " addition antenna device "
Method, since " addition antenna device " method increases device and chip area, the place for needing to change is more, therefore is less applicable in,
And there are the metal layers of antenna effect for " jumper wiring " i.e. disconnection, are connected to other layers by through-hole, finally return current layer, only
Change the attribute of current metal level, it is other all not change, it is used widely due to modification facilitates.
After the completion of chip makes physical domain, Antenna (antenna) DRC is carried out to chip using verifying software tool
(Design Rule Check) is checked, carries out manual modification to place is violated according to inspection result（See Fig. 1）, due to antenna ratio
The amount that rate calculates is area ratio, since the width of the width of polysilicon, length and metal is inconvenient or cannot modify, technique
Parameter constant, only metal length can be convenient modification, therefore convert the amount with length direct proportionality for antenna ratio,
In view of the convenience of modification, modified using " jumper wiring ", the general length and attribute for only modifying metal level, but not
It knows for sure and how much length is violated, need to change that how much length could not violate, so, it is necessarily required to multiple inspection, determines
Position, modification, the time needed for largely expending the inspection method, reduce working efficiency；It is multiple accurate similar when having simultaneously
With node（Such as data/address bus）When having violation antenna effect, check that modification is unable to accurately control the length of wiring layer variability manually
With the quantity of through-hole, the problems such as will have a direct impact on the precision of chip.Chinese patent CN102054083B " the antenna of integrated circuit
The inspection method and its device of effect " is related to counting each node to the maximum of accumulation antenna effect value caused by the element
Value achievees the purpose that reducing element is examined number, is equivalent to the improvement that antenna effect mentioned in the present invention checks file,
It is different with the method for violating antenna effect in heretofore described elimination domain；Chinese patent CN102800667A is " a kind of
The method of antenna effect is solved in chip design ", antenna effect is solved the problems, such as using the circuit of addition passgate structures, with this hair
Bright middle change metal level is different, and therefore, design field is checked in antenna effect, often to the rule of antenna effect, inspection
Checking method research it is more, but to occurring how antenna effect violation is quickly selected later, eliminates, these methods are not
Generate preferably effect.
Summary of the invention
In view of the above-mentioned problems, the invention proposes a kind of methods for quickly eliminating antenna effect.
In order to solve the above technical problems, the technical solution adopted by the present invention is：
A kind of method of quick elimination antenna effect, characterized in that after carrying out the inspection of antenna component effect, selection is violated first
One node of antenna effect, according to the node actual antennas ratio, setting meets the metal layer length of antenna effect rule most
Big value no more than wire jumper is carried out at maximum value, makes to meet antenna effect rule by the modified domain of single.
Wire jumper upward or downward is selected when wire jumper.
Suitable jumper location is selected to carry out wire jumper when wire jumper on domain.
When wire jumper, the dotted line display modification effect on domain, and through visual inspection qualification, finally confirmation modification.
When having multiple nodes to violate antenna effect, the several nodes of simultaneous selection carry out operation modification simultaneously according to the above method.
When there are multiple accurate matched nodes to violate antenna effect, the wire jumper effect of designed node is selected
Modification is answered to copy to the node that other need to modify.
The beneficial effects obtained by the present invention are as follows：
Domain after method of the invention is modified can meet antenna effect rule, and single can complete the antenna effect of the node
It should check and modify, significantly the time spent when the antenna effect of compression check integrated circuit, so that entire circuit is set
It counts process more efficiently, there is visual inspection, facilitate edit operation.In addition when there is multiple similar accurate matched nodes（In full
According to bus）When having violation antenna effect, operation modification, Huo Zhexuan can be carried out simultaneously according to the above method with the several nodes of simultaneous selection
The wire jumper effect modification for selecting designed node copies to the node for needing to modify, and accurately controls several
The length of the wiring layer variability of node and the quantity of through-hole, ensure that the matching by the modified interdependent node of antenna effect
The problems such as precision.
Detailed description of the invention
Fig. 1 is the flow chart that conventional aerial effect checks amending method；
Fig. 2 is the flow chart that antenna effect of the invention checks amending method;
Fig. 3 A- Fig. 3 D is the process schematic that antenna effect of the invention checks amending method.
Specific embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following embodiment is only used for clearly illustrating the present invention
Technical solution, and not intended to limit the protection scope of the present invention.
The invention proposes a kind of methods for quickly eliminating antenna effect, as shown in Fig. 2, carrying out the inspection of antenna component effect
After looking into, the node that selection violates antenna effect first sets by showing node actual antennas ratio and meets antenna effect
The length maximum value of rule, selects wire jumper upward or downward, and select suitable jumper location later, last dotted line display modification
Effect, and visual inspection is qualified, modifies automatically after confirmation.Domain after modified meets antenna effect rule, and single is just
The antenna effect inspection and modification of the node can be completed, when significantly spent when the antenna effect of compression check integrated circuit
Between, so that entire circuit design flow is more efficiently, there is visual inspection, facilitate edit operation.In addition when there is multiple classes
Like accurate matched node（Such as data/address bus）Have when violating antenna effect, it can be with the several nodes of simultaneous selection according to the above method simultaneously
Carry out operation modification, or the wire jumper effect modification of the designed node of selection one copies to the section for needing to modify
Point accurately controls the length of the wiring layer variability of several nodes and the quantity of through-hole, ensure that and repair by antenna effect
The problems such as matching precision of interdependent node after changing.
In the environment of Virtuoso software, examined using one domain of SMIC0.18 μm of technological design, and with Calibre
It looks into for software and is illustrated.When carrying out the inspection of antenna component effect to the domain of chip, selection violates one of antenna effect
Node, such as the polysilicon gate 100 of Fig. 3 A and the first metal layer 101 and through-hole 102 that it is connected click right button and show that node is real
Border antenna ratio, SMIC0.18 μm of process rule regulation in the case where not using protection diode, the perimeter of the first 101 layers of metal with
The ratio of 100 perimeter of polysilicon gate is less than or equal to 400, and since technique other parameters are constant, general antenna ratio and length are at just
Proportionate relationship, reducing length can reduce ratio, clicks display actual antennas ratio by right key and is assumed to 500, is greater than design rule,
Ratio must be reduced, that is, reduce length, Fig. 3 B dotted line 103 shows the length maximum value for meeting antenna effect rule, selects
Wire jumper upward or downward is selected, since this node is the first metal layer, so selecting upward wire jumper, selects second metal layer, selection
Suitable jumper location, dotted line display modification effect, such as Fig. 3 C dotted line 103, the second metal layer at wire jumper without other nodes connects
Otherwise line will lead to short circuit, visual inspection is qualified, and confirmation modification, as shown in Figure 3D, the first metal layer 101 disconnects, and increase
Wire jumper second metal layer 2105 and through-hole 104.
It, can be several with simultaneous selection simultaneously when there is multiple similar accurate matched node such as data/address bus to have violation antenna effect
A node carries out operation modification simultaneously according to the above method, or the antenna effect modification side of the designed node of selection one
Case, that is, Fig. 3 C dotted line 103 copies to the node for needing to modify, and visual inspection is qualified, confirmation modification, if accurately controlling
The length of the wiring layer variability of dry node and the quantity of through-hole, ensure that by the modified interdependent node of antenna effect
The problems such as matching precision.
Domain after modified meets antenna effect rule, and single can complete antenna effect inspection, significantly compress
It checks the time spent when the antenna effect of integrated circuit, so that entire circuit design flow is more efficiently, has visual
Change and check, facilitates edit operation, the method is all suitable for all technology libraries, versatile.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of method for quickly eliminating antenna effect, characterized in that after carrying out the inspection of antenna component effect, selection is disobeyed first
One node of anti-antenna effect, according to the node actual antennas ratio, setting meets the metal layer length of antenna effect rule
Maximum value no more than wire jumper is carried out at maximum value, makes to meet antenna effect rule by the modified domain of single.
2. a kind of method for quickly eliminating antenna effect according to claim 1, characterized in that selected when wire jumper upwards or
Downward wire jumper.
3. a kind of method for quickly eliminating antenna effect according to claim 1, characterized in that selected on domain when wire jumper
It selects suitable jumper location and carries out wire jumper.
4. a kind of method for quickly eliminating antenna effect according to claim 1, characterized in that when wire jumper, on domain
Dotted line display modification effect, and through visual inspection qualification, finally confirmation modification.
5. a kind of method for quickly eliminating antenna effect according to claim 1, characterized in that there is multiple nodes to violate day
When line effect, the several nodes of simultaneous selection carry out operation modification simultaneously according to the above method.
6. a kind of method for quickly eliminating antenna effect according to claim 1, characterized in that there is multiple accurate matching sections
When point violates antenna effect, select one the wire jumper effect modification of designed node copy to other and need to modify
Node.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810616995.2A CN108897933A (en) | 2018-06-15 | 2018-06-15 | A kind of method of quick elimination antenna effect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810616995.2A CN108897933A (en) | 2018-06-15 | 2018-06-15 | A kind of method of quick elimination antenna effect |
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| Publication Number | Publication Date |
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| CN108897933A true CN108897933A (en) | 2018-11-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810616995.2A Pending CN108897933A (en) | 2018-06-15 | 2018-06-15 | A kind of method of quick elimination antenna effect |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112329379A (en) * | 2019-07-31 | 2021-02-05 | 天津大学 | Integrated circuit reliability evaluation method aiming at antenna effect |
| CN115879408A (en) * | 2023-02-03 | 2023-03-31 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for repairing antenna effect violation of integrated circuit |
| CN117391043A (en) * | 2023-12-12 | 2024-01-12 | 北京象帝先计算技术有限公司 | Antenna effect detection method, device, electronic equipment and storage medium |
| US11941340B2 (en) | 2021-08-16 | 2024-03-26 | International Business Machines Corporation | Cross-hierarchy antenna condition verification |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060225007A1 (en) * | 2005-04-05 | 2006-10-05 | Taiwan Semiconductor Manufacturing Co. | Antenna effect prevention by model extraction in a circuit design for advanced processes |
| CN101986315A (en) * | 2010-11-19 | 2011-03-16 | 杭州开鼎科技有限公司 | Method for physically implementing special integrated circuit chip under deep sub-micron |
| CN102955123A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN103164565A (en) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | Method for automatically forming antenna regular test vectors |
-
2018
- 2018-06-15 CN CN201810616995.2A patent/CN108897933A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060225007A1 (en) * | 2005-04-05 | 2006-10-05 | Taiwan Semiconductor Manufacturing Co. | Antenna effect prevention by model extraction in a circuit design for advanced processes |
| CN101986315A (en) * | 2010-11-19 | 2011-03-16 | 杭州开鼎科技有限公司 | Method for physically implementing special integrated circuit chip under deep sub-micron |
| CN102955123A (en) * | 2011-08-19 | 2013-03-06 | 上海华虹Nec电子有限公司 | Examination method for different-party IP (internet protocol) containing client party chip antenna effect |
| CN103164565A (en) * | 2012-12-04 | 2013-06-19 | 天津蓝海微科技有限公司 | Method for automatically forming antenna regular test vectors |
Non-Patent Citations (3)
| Title |
|---|
| 张智胜: "超深亚微米物理设计中天线效应的消除", 《半导体技术》 * |
| 李蜀霞等: "超深亚微米IC设计中的天线效应", 《中国集成电路》 * |
| 赵兵等: "基于SKILL语言的自动天线效应修复器设计", 《微电子学》 * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112329379A (en) * | 2019-07-31 | 2021-02-05 | 天津大学 | Integrated circuit reliability evaluation method aiming at antenna effect |
| US11941340B2 (en) | 2021-08-16 | 2024-03-26 | International Business Machines Corporation | Cross-hierarchy antenna condition verification |
| CN115879408A (en) * | 2023-02-03 | 2023-03-31 | 摩尔线程智能科技(北京)有限责任公司 | Method and device for repairing antenna effect violation of integrated circuit |
| CN117391043A (en) * | 2023-12-12 | 2024-01-12 | 北京象帝先计算技术有限公司 | Antenna effect detection method, device, electronic equipment and storage medium |
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Application publication date: 20181127 |