CN102263041B - Method for manufacturing multilayer stacked resistance conversion memorizer - Google Patents
Method for manufacturing multilayer stacked resistance conversion memorizer Download PDFInfo
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- H—ELECTRICITY
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Abstract
The invention relates to a method for manufacturing a multilayer stacked resistance conversion memorizer, which is realized by using a bonding method. The method comprises the following steps: manufacturing a first wafer which contains a peripheral circuit and a resistance conversion memorizer; manufacturing a second wafer, the surface of which has a low-resistivity heavily-doped semiconductor layer; bonding the first wafer with the second wafer, and then removing a redundant semiconductor from the second wafer by performing a subsequent process, such as back corrosion, polishing, annealing peeling, and the like; and manufacturing a gating unit and a resistance conversion memorizing unit on the bonded wafers, thereby acquiring a character/bit line, namely the heavily-doped semiconductor in the multilayer stacked resistance conversion memorizer. According to the method provided by the invention, a metal character/bit line is replaced by a heavily-doped semiconductor character/bit line, so that the process is compatible with the method for manufacturing the resistance conversion memorizer and excellent reliability is achieved.
Description
Technical field
The invention belongs to technical field of semiconductors, relate to a kind of manufacture method of electric resistance transition memory of multiple-level stack, be used for the manufacturing of semiconductor device.
Background technology
The day by day lifting that semiconductor device is required along with the development of semiconductor technology and people, the density of semiconductor device and performance are all at high speed development, the semiconductor device multiple-level stack has been the inexorable trend of integrated circuit development, what the semiconductor device of multiple-level stack was realized is not only the at double rising of integrated level, and obtained the significantly lifting of device speed, meanwhile, in suitable stacking number of plies scope, the unit cost of device also can be reduced significantly, thereby makes semiconductor device more competitive.
Aspect memory, for the demand of high-performance memory, so that phase transition storage, resistance random access memory constant resistance transit storage become the nonvolatile semiconductor memory candidate of future generation of current the supreme arrogance of a person with great power, they have wide market prospects.The storage density of electric resistance transition memory is high, manufacturing process is simple, speed is fast and have good data holding ability, will be widely used in every field in the near future, is expected to become a kind of general memory.Also as the development trend of other semiconductor device, the multiple-level stack of semiconductor memory also is the important directions of memory development, also is like this for electric resistance transition memory.
In semiconductor device 3-dimensional multi-layered stacking, wafer bonding is a kind of important process means, yet, adopt bonding method to carry out being stacked on of electric resistance transition memory and face certain problem in the application, on the surface of two bonding wafers, may have large-area metal, remainder is the dielectric materials such as silica, silicon, therefore, bonded interface greatly being arranged is the interface of dielectric material and metal.Yet, well-known, the binding ability of dielectric material and metal a little less than, not only be difficult to bonding, and reliability is very poor behind the bonding.This also is one of bonding techniques bottleneck in electric resistance transition memory is used, and has greatly limited the application of bonding techniques in electric resistance transition memory.In addition, the multilayer wafer that follow-up chemico-mechanical polishing possibility para-linkage obtains brings very large impact, and the mechanical force that applies in the polishing may cause peeling off of the relatively poor bonded interface of intensity, so that bonding and multilayer device lost efficacy.How to promote the also Science and engineering problem that solves of actual needs of wafer adhesion strength in the stacking process of electric resistance transition memory of multiple-level stack.In existing bonding techniques, also contain inevitably high-temperature technology, the technique of these high temperature and electric resistance transition memory technology also are incompatible.
As mentioned above, in wafer bonding, the bonding of metal and medium (conductor oxidate or semiconductor) is difficult, and bonding force a little less than, and semiconductor and semiconductor, perhaps the bonding between semiconductor and the conductor oxidate is comparatively easy, and bonding force is stronger.By the improvement of bonding technology, the bonding area of amplified medium and medium just can reduce the difficulty of electric resistance transition memory bonding, promotes bond strength.The present invention adopts semiconductor word/bit line substituted metal word/bit line, greatly reduces the difficulty of bonding, has strengthened the intensity of bonding.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of manufacture method that realizes the electric resistance transition memory of multiple-level stack by bonding method, adopt semiconductor word/bit line substituted metal word/bit line, can make technique and electric resistance transition memory process compatible, and have good reliability.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of manufacture method of multilayer stacked resistance transit storage comprises the steps:
(A) make semiconductor the first wafer, and adopt chemico-mechanical polishing to carry out planarization, contain peripheral circuit and at least one deck electric resistance transition memory of being attached thereto on the first wafer, described electric resistance transition memory comprises the first word or bit line, the first gate tube array and the first resistor conversion memory unit array that link to each other corresponding to the first gate tube array that link to each other with the first word or bit line successively;
(B) make semiconductor the second wafer, form heavily doped semiconductor layer on a wherein surface of described the second wafer, then carry out planarization with chemico-mechanical polishing;
(C) the first wafer and the second wafer are carried out bonding, the first wafer manufacturing has the surface of the first resistor conversion memory unit array and the Surface Contact that the second wafer is formed with heavily doped semiconductor layer;
(D) another surperficial part semiconductor of removal the second wafer after bonding is finished, and with its surface of chemico-mechanical polishing planarization, the flat base after having obtained the second wafer stacking;
(E) continue to make the second gate tube array and the second resistor conversion memory unit array of linking to each other of correspondence with it in described substrate, the heavily doped semiconductor layer of the second wafer links to each other with the second gate tube array as the second word or bit line;
(G) make top electrode and encapsulating.
Before as needing continuation stacking, can also comprise step (F): repeating step (A) obtains more multi-layered stacked resistance transit storage to (E) to described method as required in step (G).
Wherein, described chemico-mechanical polishing comprises rough polishing and two steps of finishing polish.
Described the first and second resistor conversion memory unit arrays are phase-changing memory cell array, resistor random memory unit array or Sb base resistor conversion memory unit array.Described the first and second gate tube arrays comprise one or more in PN diode, Schottky diode, bipolar transistor, the field-effect transistor.
Further, in the step (B), adopt a kind of or two kinds of methods in atom diffusion and the Implantation to form described heavily doped semiconductor layer.
Further, in the step (D), remove another surperficial part semiconductor of the second wafer and adopt in following four kinds of techniques one or more:
A. chemico-mechanical polishing;
B. wet etching;
C. annealing to strip technique is injected the special doped layer of formation by the semiconductor intermediate ion of the second wafer, adopts annealing to make this special doped layer form defective, and semiconductor is split at special doped layer place, removes unnecessary part semiconductor thereby peel off;
D. dry etching.
As one of preferred version of the present invention, in the step (D), when adopting annealing to strip technique, the special doped layer that forms by Implantation H and B not being higher than under 400 ℃ the annealing, is realized peeling off.
As one of preferred version of the present invention, described the first and second gate tube arrays and the first and second resistor conversion memory unit arrays adopt the dual shallow groove isolation structure.
As one of preferred version of the present invention, can or in step (E), be formed for making the doped structure of the second gate tube array in step (B).
Beneficial effect of the present invention is: the second wafer and the first wafer that the present invention adopts the surface to have the low-resistivity heavily doped semiconductor layer carry out bonding, make in the sandwich construction memory that obtains behind the bonding, and heavily doped semiconductor layer is as word/bit line.By application and the selection of heavy doping the second wafer, make to have that bond strength promotes between the first wafer that most of area is medium and the second wafer, difficulty reduces, and reliability strengthens, technique and electric resistance transition memory manufacturing process compatibility.So manufacture method of the electric resistance transition memory of the multiple-level stack of the present invention's proposition, not only can make technique and electric resistance transition memory process compatible, and the enhancing by the reliable bond area, make the device architecture behind the bonding have good reliability and less defective, be expected in multiple-level stack, obtain large-scale the application.
Description of drawings
Figure 1A-Fig. 1 M is a kind of manufacturing multilayer stacked resistance transit storage process flow diagram.
Fig. 2 A-Fig. 2 M is the another kind of multilayer stacked resistance transit storage process flow diagram of making.
Embodiment
Below in conjunction with accompanying drawing, further specify the specific embodiment of the present invention.Below be several preferred embodiment of the present invention:
Embodiment one
See also Fig. 1, the present invention has disclosed a kind of manufacture method of electric resistance transition memory of multiple-level stack, comprises the steps:
(A) at first make the first wafer, the first wafer comprises peripheral circuit and one deck electric resistance transition memory at least, adopts chemico-mechanical polishing to carry out planarization, and the chemico-mechanical polishing that the present invention uses can comprise rough polishing and two steps of finishing polish.Electric resistance transition memory comprises gate tube array, word/bit line and resistor conversion memory unit array, and the first wafer can also comprise the electric resistance transition memory of multilayer.On substrate 1, do not draw the peripheral circuit part among Figure 1A, and the non-equal proportion drafting of illustrated size, with one deck electric resistance transition memory.In this example, the gate tube of employing is the PN diode, can certainly adopt the other types gate tube, such as Schottky diode, field-effect transistor and bipolar transistor etc. is at this, take the PN diode as example, but be noted that the gate tube that the present embodiment is selected is not restricted to the PN diode.The resistor conversion memory unit array that adopts memory also can be a kind of in phase-changing memory cell array, resistor random memory unit array or the Sb base resistor conversion memory unit array, if the first wafer comprises the electric resistance transition memory of multilayer, also can comprise simultaneously one or more of said memory cells array.At this, in order to express easily, take phase transition storage as example, obviously in the present invention, other memories of two types also are applicable.Among Figure 1A, 2 are conduction heavily-doped semiconductor word line (or metal word lines), 3 is insulating material (such as polysilicon and silica etc.), 4 is doped semiconductor, forms the PN diode between 4 and 2, and 5 and 7 is electrode, 6 is SiSbTe phase-change storage material unit, it obviously also can be other memory cell, such as metal oxide and Sb etc., and wherein electrode 5, SiSbTe phase-change storage material unit 6 and electrode 7 form the resistor conversion memory unit array.Among Figure 1A along the projection of A-A direction as shown in Figure 1B, vertical view is shown in Fig. 1 C, from Fig. 1 C, can see, area above 75% is the part of insulating material, remainder then is electrode, the electrode 7 of selecting can comprise multilayer, and the material of top layer can select to have with silicon the material of better binding ability.
(B) make the second wafer, superficial layer forms heavily doped semiconductor layer 10 by atom diffusion method or Implantation, heavily doped semiconductor layer 10 has lower resistivity, carry out again subsequently Implantation H and B, form special doped layer 9, shown in Fig. 1 D, special doped layer 9 will be used to removing unnecessary semiconductor 8 in follow-up step.If adopt the additive methods such as chemico-mechanical polishing, wet etching, dry etching to remove redundance semiconductor 8, then need not carry out the Implantation in this step.
(C) the first wafer and the second wafer are carried out bonding, such as Fig. 1 E signal, the surface that the second wafer contains heavily doped semiconductor layer 10 contacts with the surface that the first wafer is formed with the resistor conversion memory unit array, realizes stacking; Structure behind the bonding is shown in Fig. 1 F, and wherein 11 and 12 is respectively the first wafer and the second wafer, and 13 is exactly the structure after the bonding.
(D) protection by high pure nitrogen is annealed under 300 ℃; owing in semiconductor, forming defective behind the ion implanted impurity; semiconductor will split from special doped layer 9; the remainder semiconductor layer is stayed on the first wafer 11; and with its surface of chemico-mechanical polishing planarization; flat base after having obtained the second wafer stacking, and the semiconductor 8 that strips down can also recycle, and is beneficial to reduce cost.
(E) form new doped layer 14 by Implantation, be formed for making the doped structure of PN diode with former heavily doped semiconductor layer 10, shown in Fig. 1 G.Among Fig. 1 G along the projection of B-B direction shown in Fig. 1 H.
Make the first darker shallow channel 17 of the degree of depth, the degree of depth is until can effectively separate heavily doped semiconductor layer 10, and the heavily-doped semiconductor lines 15 that form are bit line, cover the top of the ground floor resistor conversion memory unit array of making in the first wafer, simultaneously new doped layer 14 is separated into doping lines 16.
Make the second more shallow shallow channel 19 of the degree of depth, the degree of depth is to the top of heavily-doped semiconductor lines 15, and the second shallow channel 19 is separated into discrete unit 18 with doping lines 16, and has formed a plurality of PN diodes between the heavily-doped semiconductor lines 15 (bit line).
Filled media material 23 (can be polysilicon etc.), by deposition and relevant semiconductor technologies such as electrode material, SiSbTe materials, formed corresponding phase-change memory cell 20+21+22 in the top of PN diode (gate tube), shown in Fig. 1 K, among the figure, along the projection of C-C direction shown in Fig. 1 L.As seen this gate tube array and resistor conversion memory unit array adopt the dual shallow groove isolation structure, namely by the first shallow channel 17 that intersects and the second shallow channel 19 and fill wherein dielectric material 23 with the unit isolation of array, the first shallow channel 17 and the second shallow channel 19 angles are preferably quadrature, can certainly be 45 the degree to 90 the degree between arbitrarily angled, gate tube array and resistor conversion memory unit array in the first wafer also can adopt this isolation structure, shown in Figure 1A-1C, this is the known technology of this area, does not repeat them here.
(F) continue stacking repeating step (A) to the step of (E) such as needs, the multiple-level stack structure of formation shown in Fig. 1 M, comprise second layer electric resistance transition memory 24, the 3rd layer of electric resistance transition memory 25 and the 4th layer of electric resistance transition memory 26, the number of plies of sandwich construction obviously is not limited to four layers shown in the figure, can be for more; In the sandwich construction, share heavily-doped semiconductor word/bit line between the adjacent layer, although adopt the same storage medium among the figure shown in the present embodiment, but it may be noted that at this, different storage mediums can be adopted between the different layers, even resistor random-access storage medium (such as metal oxide) and Sb sill etc. can be adopted.
(G) make top electrode, the through hole that also can make between each layer is finished interconnection line, and encapsulates.
Embodiment two
The difference of the present embodiment and embodiment one is, the present embodiment is for making the method for the three-dimensionally stacked electric resistance transition memory of bipolar transistor selection.
Also illustrated in above-described embodiment, in the structure of Figure 1A and Figure 1B, can adopt bipolar transistor to substitute PN diode 4 as gate tube.If adopt bipolar transistor as gate tube, the doped layer 10 that forms among Fig. 1 G and 14 will correspondingly change NPN layer or PNP layer into, and corresponding technique subsequently is similar to embodiment one, does not repeat them here.In the Memister structure of the multiple-level stack shown in Fig. 1 M that obtains at last, the difference of comparing is that the gating unit of each layer of 24-26 employing is bipolar transistor.
Embodiment three
(A) Fig. 2 A is depicted as and makes the first wafer that peripheral circuit and one deck electric resistance transition memory are arranged, and does not equally also illustrate peripheral circuit, but does not represent do not possess peripheral circuit on the substrate 31 of the first wafer.The gate tube that adopts in this case is Schottky diode, can certainly adopt other gating units, and such as PN diode and bipolar transistor etc. at this, take Schottky diode as example, but is noted that and is not restricted to Schottky diode.A plurality of Schottky diodes are shared a heavily-doped semiconductor word line 32, and the interface of the Schottky barrier that Schottky diode forms is the interface of light dope semiconductor 34 and electrode 35.The heating electrode of electrode 35 or memory cell 37, it can comprise sandwich construction, being a kind of metal that can form with this light dope semiconductor 34 Schottky contacts in the side near light dope semiconductor 34 for example, then is the electrode material with good adhesion and efficiency of heating surface in the side near memory cell 37.The 36th, in order to limit the insulation side wall of phase-change material volume, can effectively reduce the power consumption of phase transition storage.The memory cell that adopts also can be a kind of in resistance random access memory, the Sb base electric resistance transition memory, at this, in order to express easily, take Si-Sb base phase transition storage as example.Among Fig. 2 A along the projection of D-D direction shown in Fig. 2 B.
(B) make the second required wafer of bonding: adopt lightly doped semiconductor 40, forming heavily doped semiconductor layer 41 by diffusion method at crystal column surface on smooth semiconductor base, still is light dope semiconductor 40 below heavily doped semiconductor layer 41 obviously; Inject the B and the special doped layer 42 of H that form, also can replace with injecting other ions, special doped layer 42 degree of depth are deeper than heavily doped semiconductor layer 41.Shown in Fig. 2 D.
(C) the first wafer 44 and the second wafer 45 are carried out bonding, mainly rely on the bonding realization between semiconductor and the insulating material stacking, shown in Fig. 2 D and E, the second wafer heavily doped semiconductor layer is realized contacting with the first wafer, and the 46th, the structure behind the bonding.
(D) under 250 ℃, anneal by vacuum protection; because the defective that in semiconductor, forms behind the Implantation of H and B; semiconductor will split from special doped layer 42; surperficial heavily doped semiconductor layer 41 and light dope semiconductor 47 are stayed on the first wafer; then adopt chemico-mechanical polishing etc. to obtain smooth light dope semiconductor layer 48; shown in Fig. 2 F; among the figure along the projection of E-E direction shown in Fig. 2 G; and the semiconductor base that strips down can also recycle, and is conducive to save cost.
(E) depositing metal layers 49, metal level 49 can comprise sandwich construction, the part that contacts with light dope semiconductor layer 48 in metal level 49 sandwich constructions need to form Schottky barrier with light dope semiconductor layer 48, to form follow-up Schottky diode, shown in Fig. 2 H.
Make darker shallow channel 50, the degree of depth is until the top of insulating barrier shown in Fig. 2 I, is separated into discrete word line 51 with heavily doped semiconductor layer.
Make the shallow channel 52 that intersects with shallow channel 50, the degree of depth is shallow than shallow channel 50, the degree of depth is until the top of heavily-doped semiconductor word line 51, light dope semiconductor 48 and the metal level 49 of word line 51 tops is separated into discrete unit 53,54, so that formed the Schottky diode unit between them.Shallow channel 50 and 52 angle are preferably quadrature, and what can certainly be 45 degree between 90 degree be arbitrarily angled.
(F) continue stacking repeating step (A) to the step of (E) such as needs, can form the multiple-level stack structure shown in Fig. 2 M;
(G) make through hole and top electrode between each layer, and encapsulate.
Embodiment four
The difference of the present embodiment and embodiment three is, the present embodiment discloses a kind of method of making three-dimensionally stacked electric resistance transition memory, adopts the multiple memory cell of multiple gate tube.
Among the embodiment three, Schottky diode shown in Fig. 2 A and the 2B can replace with PN diode or bipolar diode, and upper strata gate tube subsequently can be Schottky diode, namely in the device of a multiple-level stack, can comprise multiple gate tube, also can comprise the multiple memorizers structure, again repeat no more.As substituting of step (D), removing unnecessary method for semiconductor can also be chemical mechanical polishing method, namely remove unnecessary semiconductor with polishing, if adopt this way, then do not need the Implantation of step (B) and the annealing process of step (D).
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change is possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that in the situation that do not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other forms, structure, layout, ratio, and realize with other substrates, material and parts.In the situation that do not break away from the scope of the invention and spirit, can carry out other distortion and change to disclosed embodiment here.
For example, the selection of storage medium is not restricted to specific phase-change material or resistor random-access storage medium, it can be any material that can under the effect of the signal of telecommunication, realize the resistance counter-rotating, in the device of a multiple-level stack, the multiple memorizers structure can be comprised, also multiple gate tube can be comprised.
Claims (9)
1. the manufacture method of a multilayer stacked resistance transit storage is characterized in that, may further comprise the steps:
(A) make semiconductor the first wafer, and adopt chemico-mechanical polishing to carry out planarization, contain peripheral circuit and at least one deck electric resistance transition memory of being attached thereto on the first wafer, described electric resistance transition memory comprises the first word or bit line, the first gate tube array and the first resistor conversion memory unit array that link to each other corresponding to the first gate tube array that link to each other with the first word or bit line successively; Described the first gate tube array comprises one or more in PN diode, Schottky diode, bipolar transistor, the field-effect transistor;
(B) make semiconductor the second wafer, form heavily doped semiconductor layer on a wherein surface of described the second wafer, then carry out planarization with chemico-mechanical polishing;
(C) the first wafer and the second wafer are carried out bonding, the first wafer manufacturing has the surface of the first resistor conversion memory unit array and the Surface Contact that the second wafer is formed with heavily doped semiconductor layer;
(D) another surperficial part semiconductor of removal the second wafer after bonding is finished, and with its surface of chemico-mechanical polishing planarization, the flat base after having obtained the second wafer stacking;
(E) continue to make the second gate tube array and the second resistor conversion memory unit array of linking to each other of correspondence with it in described substrate, the heavily doped semiconductor layer of the second wafer links to each other with the second gate tube array as the second word or bit line; Described the second gate tube array comprises one or more in PN diode, Schottky diode, bipolar transistor, the field-effect transistor;
(G) make top electrode and encapsulating.
2. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 1, it is characterized in that: in step (G) before, also comprise step (F): repeating step (A) is to (E).
3. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 1, it is characterized in that: described chemico-mechanical polishing comprises rough polishing and two steps of finishing polish.
4. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 1, it is characterized in that: described the first and second resistor conversion memory unit arrays are phase-changing memory cell array, resistor random memory unit array or Sb base resistor conversion memory unit array.
5. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 1 is characterized in that: in the step (B), adopt a kind of or two kinds of methods in atom diffusion and the Implantation to form described heavily doped semiconductor layer.
6. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 1 is characterized in that: in the step (D), remove another surperficial part semiconductor of the second wafer and adopt in following four kinds of techniques one or more:
A. chemico-mechanical polishing;
B. wet etching;
C. annealing to strip technique is injected the special doped layer of formation by the semiconductor intermediate ion of the second wafer, adopts annealing to make this special doped layer form defective, and semiconductor is split at special doped layer place, removes unnecessary part semiconductor thereby peel off;
D. dry etching.
7. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 6, it is characterized in that: in the step (D), when adopting annealing to strip technique, by the special doped layer of Implantation H and B formation, not being higher than under 400 ℃ the annealing, realize peeling off.
8. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 1, it is characterized in that: described the first and second gate tube arrays and the first and second resistor conversion memory unit arrays adopt the dual shallow groove isolation structure.
9. the manufacture method of described a kind of multilayer stacked resistance transit storage according to claim 1 is characterized in that: in step (B) or be formed for making the doped structure of the second gate tube array in step (E).
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| EP3844810A4 (en) | 2018-11-30 | 2022-06-01 | Yangtze Memory Technologies Co., Ltd. | Bonded memory device and fabrication methods thereof |
| KR20210105718A (en) * | 2020-02-19 | 2021-08-27 | 에스케이하이닉스 주식회사 | Memory device and memory system having the same |
| CN114864753B (en) * | 2022-07-05 | 2022-11-04 | 杭州视光半导体科技有限公司 | Preparation method and application of wafer with three-layer stacking structure |
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| CN1632911A (en) * | 2003-12-24 | 2005-06-29 | 联合晶圆公司 | Method for making thin film by transferring on base plate |
| CN1983618A (en) * | 2005-12-12 | 2007-06-20 | 日立环球储存科技荷兰有限公司 | Unipolar resistance random access memory device and vertically stacked architecture |
| CN101477987A (en) * | 2009-01-08 | 2009-07-08 | 中国科学院上海微系统与信息技术研究所 | Tri-dimension stacked resistance conversion memory and manufacturing process thereof |
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| US6888750B2 (en) * | 2000-04-28 | 2005-05-03 | Matrix Semiconductor, Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
| US6737316B2 (en) * | 2001-10-30 | 2004-05-18 | Promos Technologies Inc. | Method of forming a deep trench DRAM cell |
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| CN1632911A (en) * | 2003-12-24 | 2005-06-29 | 联合晶圆公司 | Method for making thin film by transferring on base plate |
| CN1983618A (en) * | 2005-12-12 | 2007-06-20 | 日立环球储存科技荷兰有限公司 | Unipolar resistance random access memory device and vertically stacked architecture |
| CN101477987A (en) * | 2009-01-08 | 2009-07-08 | 中国科学院上海微系统与信息技术研究所 | Tri-dimension stacked resistance conversion memory and manufacturing process thereof |
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