CN102185104A - Multilayer stacked resistance transit storage structure - Google Patents
Multilayer stacked resistance transit storage structure Download PDFInfo
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- CN102185104A CN102185104A CN2011100914767A CN201110091476A CN102185104A CN 102185104 A CN102185104 A CN 102185104A CN 2011100914767 A CN2011100914767 A CN 2011100914767A CN 201110091476 A CN201110091476 A CN 201110091476A CN 102185104 A CN102185104 A CN 102185104A
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Abstract
The invention relates to a multilayer stacked resistance transit storage structure which is characterized by comprising at least two layers of resistance transit storage layers, wherein each resistance transit storage layer contains a gate tube and a corresponding resistance transit storage unit; single gate tube gates at least two resistance transit storage units; the gate tube adopts a bipolar transistor, a Schottky diode, a PN diode or an oxide diode; the multilayer stacked resistance transit storage structure also comprises a peripheral circuit; and all the resistance transit storage layers shear the peripheral circuit. With the structure, the density of the storage can be greatly improved, the area of the peripheral circuit is saved through sharing the peripheral circuit, and the area of the gating diode is effectively increased and further the drive current of the gate tube is increased since a plurality of storage units share the gate tube, so that more space is reserved for the programming operation of the resistance transit storage.
Description
Technical field
The invention belongs to technical field of semiconductors, relate to a kind of structure of electric resistance transition memory of multiple-level stack, be used for the manufacturing of semiconductor device.
Background technology
The density and the performance of semiconductor device are maked rapid progress along with development of semiconductor, and the semiconductor device multiple-level stack has been an important part among the international semiconductor technology path figure, are the inexorable trends of the integrated circuit development of generally acknowledging.The meaning of semiconductor device multiple-level stack not only is the significantly lifting of integrated level, also be the considerable improvement of aspect performances such as device speed and power consumption, meanwhile, the cost of the unit intensity of device also will significantly reduce, thereby makes semiconductor device more competitive.
Aspect memory, demand for high-performance memory, make novel electric resistance transition memories such as phase transition storage, resistance random access memory become the nonvolatile semiconductor memory candidate of future generation of current the supreme arrogance of a person with great power, they have vast market prospect, begun the commercial applications of small lot as phase transition storage, will in increasing electronic product, be applied from now on the first quarter in 2010.
The storage density height of electric resistance transition memory, manufacturing process is simple, cost is low, speed is fast and have the good data hold facility, will be widely used in every field in the near future, is expected to become a kind of general memory.They will at first be applied in the Embedded product, begin to substitute gradually application such as NOR subsequently, be expected to occupy part markets such as DRAM and hard disk at last.
As mentioned above, for novel electric resistance transition memory, multiple-level stack also is the important directions of this kind memory development.Thus, people such as Zhang Ting have also proposed the electric resistance transition memory structure and the manufacturing process (Chinese patent: three-dimensional stacked resistance transit storage and manufacture method thereof of multiple-level stack, the patent No.: ZL 200910045084.X, authorization date: 2010-10-13; The memory of multiple-level stack and manufacture method thereof, application number: 201010512040.6, the date of application: 2010-10-19).
The invention provides a kind of electric resistance transition memory structure of multiple-level stack, be that with the difference of prior art the memory of this kind structure not only has the structure of multiple-level stack, an and gate tube gating a plurality of (at least two) resistive memory cell in the structure, not only further significantly improved the density of memory, and saved the area of peripheral circuit by sharing peripheral circuit, and the shared gate tube of a plurality of memory cell has just increased the area of gating diode effectively, also just increase the drive current of gate tube, reserved more space for the programming operation of electric resistance transition memory.
Summary of the invention
The technical problem that the present invention mainly solves is to provide a kind of device integrated morphology of electric resistance transition memory of multiple-level stack.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of multilayer stacked resistance transit storage structure, it is characterized in that: this kind electric resistance transition memory structure comprises two-layer at least resistance conversion accumulation layer, contain gate tube and the resistor conversion memory unit corresponding in every layer of resistance conversion accumulation layer with it, two resistor conversion memory units of the corresponding at least gating of each gate tube, the electric resistance transition memory structure of this multiple-level stack also comprise the peripheral circuit that is connected with each resistance conversion accumulation layer.
As preferred version of the present invention, the gate tube in the described multilayer stacked resistance transit storage structure is a Schottky diode or for the PN diode or for the oxide diode or for bipolar transistor.
As preferred version of the present invention, the resistance of described resistor conversion memory unit can be realized the reversible variation between the high resistance and low resistance under action of electric signals; The type of this kind electric resistance transition memory is a phase transition storage, or resistance random access memory, or magnetoresistive memory; The storage of resistor conversion memory unit is two-stage storage or multi-stage data storage.
As preferred version of the present invention, contain field-effect transistor in the peripheral circuit of described multilayer stacked resistance transit storage structure, the shared peripheral circuit of each layer resistance conversion accumulation layer.
Beneficial effect of the present invention is: the electric resistance transition memory structure that a kind of multiple-level stack is provided, be that with the difference of prior art the memory of this kind structure not only has the structure of multiple-level stack, an and gate tube gating a plurality of (at least two) resistive memory cell in the structure, not only further significantly improved the density of memory, and saved the area of peripheral circuit by sharing peripheral circuit, and the shared gate tube of a plurality of memory cell has just increased the area of gating diode effectively, also just increase the drive current of gate tube, reserved more space for the programming operation of electric resistance transition memory.
Description of drawings
Fig. 1 is a multilayer stacked resistance transit storage schematic diagram among the embodiment one.
Fig. 2 A-D is an individual layer resistance conversion accumulation layer schematic diagram among the embodiment one.
Fig. 3 A-B is a resistor conversion memory unit schematic diagram among the embodiment two.
Embodiment
Below in conjunction with accompanying drawing, further specify the specific embodiment of the present invention.Below be several preferred embodiments of the present invention:
Embodiment one
See also Fig. 1, the present invention has disclosed a kind of electric resistance transition memory structure of multiple-level stack, from scheming as seen, the electric resistance transition memory of multiple-level stack not only has peripheral circuit and resistor conversion memory unit in substrate, also should comprise two-layer at least resistance conversion accumulation layer, as shown be the n layer, the shared peripheral circuit that is positioned at bottom of the electric resistance transition memory of this n layer, certainly, peripheral circuit also can be set in any one deck according to actual needs.Obviously, after the electric resistance transition memory multiple-level stack, the density of memory will significantly promote.Each layer resistance conversion accumulation layer realizes interconnection by metal throuth hole.
The important feature of the electric resistance transition memory structure of the multiple-level stack that the present invention discloses is: not only contain gate tube and resistor conversion memory unit in the resistance conversion accumulation layer of individual layer, and single gate tube is two or more resistor conversion memory unit of gating at least, the profile of the resistance conversion accumulation layer of individual layer is shown in Fig. 2 A, gate tube 2 is insulated material 1 and separates among the figure, above gate tube 2 electrode 3 and 4, the top of electrode is the storage medium 5 that is embedded in the insulating barrier, what cover storage medium 5 tops is electrode 6 and 7, and electrode 6 and 7 can be to exist with word or bit line form in storage chip.Gate tube 2 shown in Fig. 2 A is preferably diode, can certainly be bipolar transistor and field-effect transistor etc., all is suitable at this as PN diode, Schottky diode and oxide diode, does not need to give unnecessary details.
In order to further specify the structure of at least two memory cell of single gate tube gating, in Fig. 2 A, along the projection of A-A, B-B, C-C direction respectively shown in Fig. 2 B, from two figure as can be seen, electrode 3 covers the top of gate tube 2 fully, and the bottom of electrode 4 covers the top of electrode 3, and electrode 4 is the structures in similar " ditch ", the bottom in " ditch " is connected with gate tube 2 or electrode 3, and the sidewall in " ditch " contacts with storage medium 5 formation, as bottom electrode., it may be noted that the storage medium 5 that memory adopts can be a phase-change material here, also can be metal oxide, can also be giant magnetic resistance, or the material that can realize the resistance reversible transition under signal of telecommunication effect of other any kinds.The storage medium 5 that adopts can be uniformly, also can be sandwich construction, and for example in the application of magnetoresistive memory, storage medium can have two-layer structure.
Certainly, above-mentioned device architecture can also be other structure, such as in Fig. 2 A, and can also be respectively shown in Fig. 2 C along the projection of A-A, B-B, C-C direction.With reference to this figure as seen, electrode 4 is one and is similar to the structure of " square water tumbler " in this example, the bottom of " square water tumbler " is connected with gate tube 2 or electrode 3, and the sidewall of " square water tumbler " contacts with storage medium 5 formation, sidewall is as bottom electrode, and the storage medium 5 of its top also is the structure of annular, is embedded in the insulation and thermal insulation material.
What last figure showed is the structure of 1S2R (two resistive memory cells of 1 gate tube gating), point out that the present invention obviously also protects the structure of two above resistive memory cells of 1 gate tube gating, at this, is example with 1S4R, and other situations just no longer illustrate.Under the situation of 1S4R, among Fig. 2 A, can also be respectively shown in Fig. 2 D, along the projection of A-A, B-B, C-C direction so four resistor conversion memory units of 1 gate tube gating.Obviously, structure can also be the 1SnR structure, and n is more than or equal to 2 here.
Embodiment two
The way of contact for storage medium and electrode in the above-mentioned memory cell obviously can be done corresponding adjustment, the profile of memory cell can be shown in Fig. 3 A and 3B, in the above embodiments one, storage medium is embedded in the insulating material, such structure is very favourable for the lifting of the electric resistance transition memory performance of some type, for example when memory device is phase transition storage, phase-change material is embedded in the insulating material, the power consumption of device after the volume-diminished of material, speed, the performance of aspects such as consistency is significantly improved, and is insulated heat-insulating material based on the storage medium of thermal induced phase transition principle and coats the back heat utilization ratio and significantly promote.And for other storage classes such as resistance random access memories, whether storage medium is slipped in the insulation and thermal insulation material there is no too much influence, therefore can adopt the structure shown in Fig. 3 A, the advantage of this structure is that manufacturing process is comparatively simple, and wherein, 011 is insulating material, 012 is gate tube, electrode 013 and 014 consists of bottom electrode, and 015 is storage medium, and 016 is top electrode.And the structure shown in Fig. 3 B shows, has the storage medium of part to be slipped in the insulating material, and wherein, 021 is insulating material, and 022 is gate tube, and electrode 023 and 024 consists of bottom electrode, and 025 is storage medium, and 026 is top electrode.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change are possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other forms, structure, layout, ratio, and realize with other substrates, material and parts.Under the situation that does not break away from the scope of the invention and spirit, can carry out other distortion and change here to disclosed embodiment.
Claims (7)
1. the electric resistance transition memory structure of a multiple-level stack, it is characterized in that: this kind electric resistance transition memory structure comprises two-layer at least resistance conversion accumulation layer, contain gate tube and the resistor conversion memory unit corresponding in every layer of resistance conversion accumulation layer with it, two resistor conversion memory units of the corresponding at least gating of each gate tube, the electric resistance transition memory structure of this multiple-level stack also comprise the peripheral circuit that is connected with each resistance conversion accumulation layer.
2. multilayer stacked resistance transit storage structure as claimed in claim 1 is characterized in that: described gate tube is a Schottky diode or for the PN diode or for the oxide diode or for bipolar transistor.
3. multilayer stacked resistance transit storage as claimed in claim 1 is characterized in that: the resistance of memory cell is realized the reversible variation between the high resistance and low resistance under action of electric signals.
4. as claim 1 or 3 described multilayer stacked resistance transit storages, it is characterized in that: the type of this kind electric resistance transition memory is a phase transition storage, or resistance random access memory, or magnetoresistive memory.
5. as claim 1 or 3 described multilayer stacked resistance transit storages, it is characterized in that: the storage of resistor conversion memory unit is two-stage storage or multi-stage data storage.
6. multilayer stacked resistance transit storage structure as claimed in claim 1 is characterized in that: the shared peripheral circuit of each resistance conversion accumulation layer.
7. multilayer stacked resistance transit storage structure as claimed in claim 1 is characterized in that: contain field-effect transistor in the described peripheral circuit.
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| CN2011100914767A CN102185104A (en) | 2011-04-12 | 2011-04-12 | Multilayer stacked resistance transit storage structure |
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| CN103579281A (en) * | 2012-08-09 | 2014-02-12 | 旺宏电子股份有限公司 | Memory device and method making same |
| CN110943102A (en) * | 2019-11-12 | 2020-03-31 | 华中科技大学 | High-density phase change memory three-dimensional integrated circuit structure |
| CN111029362A (en) * | 2019-11-12 | 2020-04-17 | 华中科技大学 | Preparation method of high-density phase change memory three-dimensional integrated circuit structure |
| CN111146339A (en) * | 2019-12-19 | 2020-05-12 | 上海集成电路研发中心有限公司 | Phase change memory unit and preparation method thereof |
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| CN101552282A (en) * | 2008-04-04 | 2009-10-07 | 海力士半导体有限公司 | Phase-change memory device and method of fabricating the same |
| CN101834152A (en) * | 2010-04-20 | 2010-09-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing three-dimensionally stacked resistance conversion memory |
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| US20080014733A1 (en) * | 2006-07-14 | 2008-01-17 | Micron Technology, Inc. | Bottom electrode contacts for semiconductor devices and methods of forming same |
| CN101552282A (en) * | 2008-04-04 | 2009-10-07 | 海力士半导体有限公司 | Phase-change memory device and method of fabricating the same |
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| CN103579281A (en) * | 2012-08-09 | 2014-02-12 | 旺宏电子股份有限公司 | Memory device and method making same |
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| CN110943102A (en) * | 2019-11-12 | 2020-03-31 | 华中科技大学 | High-density phase change memory three-dimensional integrated circuit structure |
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| CN111146339A (en) * | 2019-12-19 | 2020-05-12 | 上海集成电路研发中心有限公司 | Phase change memory unit and preparation method thereof |
| CN111146339B (en) * | 2019-12-19 | 2023-01-31 | 上海集成电路研发中心有限公司 | Phase change memory unit and preparation method thereof |
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Application publication date: 20110914 |