CN101488514A - Resistor conversion memory - Google Patents
Resistor conversion memory Download PDFInfo
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- CN101488514A CN101488514A CN 200910046487 CN200910046487A CN101488514A CN 101488514 A CN101488514 A CN 101488514A CN 200910046487 CN200910046487 CN 200910046487 CN 200910046487 A CN200910046487 A CN 200910046487A CN 101488514 A CN101488514 A CN 101488514A
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Abstract
The invention discloses a resistance transit storage, comprising a gating unit and a data storage unit. The gating unit refers to a PN diode, or a Schottky diode or a bipolar transistor; the gating unit adopted by the resistance transit storage is isolated by at least two shallow channels in different depth. The invention provides a plurality of structures of the resistance transit storage, comprising structures of the PN diode, Schottky diode and bipolar transistor. The structures are characterized by simpleness, therefore, the structures feature simple and convenient manufacture methods and are completely compatible with the semiconductor technology, thus contributing to cost reduction and causing the high density resistance transit storage to be more competitive.
Description
Technical field
The invention belongs to microelectronics technology, relate to a kind of memory, relate in particular to a kind of electric resistance transition memory.
Background technology
Electric resistance transition memory is the focus of present nonvolatile memory research of new generation, it integrates high speed, high density, irradiation simple in structure, with low cost, anti-, advantage such as non-volatile, be at present by extensively good memory of future generation, has vast market prospect, it will have an opportunity to substitute present widely used flash memories, thereby occupy an important seat in the electronic memory field.Present electric resistance transition memory mainly contains: phase transition storage and resistance random access memory, two types electric resistance transition memory all are widely good in the world at present memories of future generation.The former is based upon the resistance conversion that the reversible transition of the phase-change material in the device causes, and the latter is based upon on the basis of non-phase transformation.
The rapid expansion of information age amount of information makes the high density resistor transit storage become the important directions of electric resistance transition memory development, in order to promote the density of electric resistance transition memory, can adopt diode (comprising PN pipe and Schottky tube) to replace MOSFET (field-effect transistor) and come the gating memory cell, play the unit are of diode to manage on year-on-year basis much smaller than MOSFET.The application of diode in electric resistance transition memory will improve the integrated level of electric resistance transition memory greatly, thereby make electric resistance transition memory more competitive.
Summary of the invention
Technical problem to be solved by this invention is: a kind of simply constructed electric resistance transition memory is provided, and its manufacture method is easy, and compatible fully with semiconductor technology, helps to reduce cost.
For solving the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of execution mode is a kind of electric resistance transition memory of PN diode selection, and it adopts PN diode selection resistor conversion memory cell, and the gating PN diode that adopts is separated mutually by the isolation of two shallow channels in different depth.Shallow channel darker in the structure is in order to isolate each conductive word lines, and more shallow shallow channel is in order to isolate the discrete diode of same word line top, and the material that shallow trench isolation adopts is an insulating material.Conductive word lines is the first conduction type heavily-doped semiconductor, and same conductive word lines top has several discrete diodes.Form the PN diode between the semiconductor of second conduction type of one deck at least of the first conduction type heavily-doped semiconductor word line and word line top.Second conductive type semiconductor of one deck at least of conductive word lines top is and the first conduction type heavily-doped semiconductor word line one, or be prepared on the first conduction type heavily-doped semiconductor word line, or be bonded on the first conduction type heavily-doped semiconductor word line by the circle crystalline substance by thin film deposition.Further, the method for described electric resistance transition memory device data storage is the programming of storage medium to be realized the change of device resistance by the signal of telecommunication.
The electric resistance transition memory structure that second kind of execution mode of the present invention is a kind of Schottky diode gating, adopt Schottky diode gating resistor conversion memory cell, and the gating Schottky diode that adopts by two shallow channels in different depth every leaving mutually.Shallow channel darker in the structure is in order to isolate each word line, and more shallow shallow channel is in order to isolate the discrete Schottky diode of same word line top, and the material that shallow trench isolation adopts is an insulating material.Conductive word lines is the first conduction type heavily-doped semiconductor, and same conductive word lines top has several discrete Schottky diodes.On the first conduction type heavily-doped semiconductor word line the lightly doped semiconductor of first conduction type is arranged in the structure, above the light dope semiconductor, metal level is arranged, and form Schottky contacts between the metal level and the first conduction type lightly-doped layer.The light dope semiconductor of conductive word lines top is and the word line one, or is prepared on the word line by thin film deposition, or is bonded on the word line by the circle crystalline substance.The method of electric resistance transition memory device data storage is the programming of storage medium to be realized the change of device resistance by the signal of telecommunication.
The electric resistance transition memory structure that the third execution mode of the present invention is a kind of bipolar transistor selection, adopt the bipolar transistor selection resistor conversion memory cell, and the gating bipolar transistor that adopts by two shallow channels in different depth every leaving mutually.Shallow channel darker in the structure is in order to isolate each word line, and the material of shallow trench isolation is an insulating material, and more shallow shallow channel is in order to isolate the discrete diode of same word line top.In the structure, above the heavily doped conductive word lines of first conduction type is the semiconductor that second conduction type mixes, the semi-conductive top that second conduction type mixes then is again the semiconductor that first conduction type mixes, and has formed bipolar transistor structure between the three-layer semiconductor.And the necessary two-layer at least semiconductor of formation bipolar transistor of conductive word lines top be with the first conduction type heavily-doped semiconductor word line be one, or be prepared on the first conduction type heavily-doped semiconductor word line, or be bonded on the first conduction type heavily-doped semiconductor word line by the circle crystalline substance by thin film deposition.The method of electric resistance transition memory device data storage is the programming of storage medium to be realized the change of device resistance by the signal of telecommunication.
Beneficial effect of the present invention is: the device architecture that the invention provides several electric resistance transition memories, the device architecture that has comprised PN diode, Schottky diode and bipolar transistor selection, the characteristics of these structures are simple structure, therefore its manufacture method is easy, and it is compatible fully with semiconductor technology, help to reduce cost, make the high density resistor transit storage of this technology of employing more competitive.In addition, the gating components and parts that electric resistance transition memory adopts are to have the dual shallow groove structure, the degree of depth difference of two shallow channel, and the object that plays electric isolation is also different.
Description of drawings
Figure 1A-1B is the structural representation of the electric resistance transition memory device of PN diode selection of the present invention.
Fig. 2 A-2B is the structural representation of the electric resistance transition memory device of Schottky diode gating of the present invention.
Fig. 3 A-3B is the structural representation of the electric resistance transition memory device of bipolar transistor selection of the present invention.
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Embodiment one
See also Figure 1A-1B, the present invention discloses a kind of electric resistance transition memory of PN diode selection; Figure 1A-1B is for adopting the structural section figure of PN diode as the electric resistance transition memory device cell of gating unit.
Shown in Figure 1A, the heavily doped word line 2 of first conduction type (n type or p type) is arranged in substrate 1, conductive word lines is a semi-conducting material, there are the second conduction type light dope and heavily doped semi-conducting material 5 and 6 in word line 2 tops, form the PN diode structure between semiconductor material layer 5,6 and the heavily doped word line 2 of first conduction type.Keep apart by the more shallow shallow channel 4 of the degree of depth between the PN diode of same word line top, the material that shallow channel adopts is an insulating material, as oxide, nitride or polysilicon etc.And between each word line by separating than shallow channel 4 darker shallow channel 14, purpose is to make electrical insulation between each word line, shown in Figure 1B.
Figure 1B is along the projection of A-A direction among Figure 1A.There are disilicide layer 7, lower electrode layer 8, resistance transition material layer 10 and top electrode 8 etc. in top at PN diode (being formed by word line 2, semiconductor material layer 5,6).Disilicide layer 7 and each electrode number of plies 8 can increase and decrease according to actual needs, dielectric material 3 is arranged, and the purpose of metal throuth hole 9 are to draw word line 2 on every side.In order to form better electricity contact, it is carried out silicidation, form disilicide layer 13, top electrode goes between 12 by drawing and forming of through hole 11.
From above-mentioned structure as seen, adopted two step shallow trench isolation in the present embodiment, the purpose in a step is in order will be respectively effectively to isolate with conductive word lines, and the purpose in another step then is diode and the memory cell electric isolation with same word line top.Between word line 2, the semiconductor material layer 5,6 can be integrally formed, also can be to make step by step by methods such as follow-up thin film deposition and the brilliant bondings of circle to form.
In the present embodiment, the method for device data storage is the programming of storage medium to be realized the change of device resistance by the signal of telecommunication.
Embodiment two
See also Fig. 2 A-2B, among Fig. 2 A-2B, the electric resistance transition memory device adopts Schottky diode as gating unit.
The formation of schottky diode array is to be realized by two shallow trench isolation, the purpose of darker shallow trench isolation is effectively to separate the heavily-doped semiconductor word line of conduction, and the Schottky diode of the purpose of the more shallow shallow trench isolation single word line top that is electric isolation.
In the structure shown in Fig. 2 A, the heavily doped word line 22 of first conduction type was arranged on the semiconductor-based end 21, the mutual separation between the word line 22 relies on the separation than depth channel isolation 30 shown in Fig. 2 B.
Fig. 2 B is along the projection of B-B direction among Fig. 2 A.There is lightly doped semiconductor 23 top of the heavily doped word line 22 of first conduction type, and the top of lightly doped semiconductor 23 then is metal or the metal alloy 24 that forms Schottky contacts with 23.So, form Schottky diode between metal 24 and semiconductor 23 and 22, separate by the more shallow shallow trench isolation 25 of the degree of depth between the diode.The top of Schottky diode then is electrode 27, storage medium 28 and top electrode 29.Semiconductor 23, and semiconductor 22 between can be integrally formed, also can be to make step by step by follow-up thin film deposition and method such as circle brilliant bonding etc. to form.
Embodiment three
See also Fig. 3 A-3B, among Fig. 3 A-3B, the electric resistance transition memory device adopts bipolar transistor as gating unit.
The formation of bipolar transistor array is to be realized by two shallow trench isolation, the purpose of darker shallow trench isolation is effectively to separate the heavily-doped semiconductor word line of conduction, and the bipolar transistor of the purpose of the more shallow shallow trench isolation single word line top that is electric isolation.
In the memory construction as shown in Figure 3A, the heavily doped word line 32 of first conduction type was arranged on the semiconductor-based end 31, the mutual separation of word line 32 relies on the separation than depth channel isolation 40 shown in Fig. 3 B.
Fig. 3 B is along the projection of C-C direction among Fig. 3 A.The semiconductor 33 that the top of the heavily doped word line 32 of first conduction type has second conduction type to mix, the top of semiconductor 33 then are semiconductor 34 (material of semiconductor 34 are the semi-conducting material that first conduction type mixes).So form bipolar transistor between semiconductor 34 and semiconductor 33 and the semiconductor 32, separate by the more shallow shallow trench isolation 35 of the degree of depth between the bipolar transistor.The top of bipolar transistor then is electrode 37, storage medium 38 and top electrode 39.Can be integrally formed between semiconductor 34, semiconductor 33 and the semiconductor 32, also can be to make step by step by methods such as follow-up thin film deposition and the brilliant bondings of circle to form.
In sum, the invention provides the device architecture of several electric resistance transition memories, the device architecture that has comprised PN diode, Schottky diode and triode gating, the characteristics of these structures are simple structure, therefore its manufacture method is easy, and compatible fully with semiconductor technology, help to reduce cost, make the high density resistor transit storage of this technology of employing more competitive.In addition, the gating components and parts that electric resistance transition memory adopts are to have the dual shallow groove structure, the degree of depth difference of two shallow channel, and the object that plays electric isolation is also different.
Here description of the invention and application is illustrative, is not to want with scope restriction of the present invention in the above-described embodiments.Here the distortion of disclosed embodiment and change are possible, and the various parts of the replacement of embodiment and equivalence are known for those those of ordinary skill in the art.Those skilled in the art are noted that under the situation that does not break away from spirit of the present invention or substantive characteristics, and the present invention can be with other forms, structure, layout, ratio, and realize with other elements, material and parts.Under the situation that does not break away from the scope of the invention and spirit, can carry out other distortion and change here to disclosed embodiment.
As, gating unit can also be other structures except PN diode, Schottky diode and bipolar transistor; In addition, the quantity of shallow channels in different depth also can be for more than two.
Among the embodiment of two shallow channels in different depth, darker shallow channel is in order to isolate each word line, and more shallow shallow channel is in order to isolate the discrete gating unit of same word line top.
Claims (22)
1, a kind of electric resistance transition memory comprises gating unit, data storage cell; It is characterized in that:
The gating unit that described memory adopts is kept apart mutually by at least two shallow channels in different depth.
2, electric resistance transition memory according to claim 1 is characterized in that:
In the described raceway groove, darker shallow channel is in order to isolate each word line, and more shallow shallow channel is in order to isolate the discrete gating unit of same word line top.
3, electric resistance transition memory according to claim 1 is characterized in that:
The gating unit that described gating unit adopts is kept apart mutually by two shallow channels in different depth.
4, electric resistance transition memory according to claim 1 is characterized in that:
Described electric resistance transition memory comprises conductive word lines, and described conductive word lines is the first conduction type heavily-doped semiconductor.
5, electric resistance transition memory according to claim 1 is characterized in that:
The method of device data storage is the programming of storage medium to be realized the change of device resistance by the signal of telecommunication.
6, electric resistance transition memory according to claim 1 is characterized in that:
The material that described shallow trench isolation adopts is an insulating material.
7, according to any described electric resistance transition memory of claim 1 to 6, it is characterized in that:
Described gating unit is the PN diode.
8, electric resistance transition memory according to claim 7 is characterized in that:
In two shallow channels in different depth, darker shallow channel is in order to isolate each word line, and more shallow shallow channel is in order to isolate the discrete diode of same word line top.
9, electric resistance transition memory according to claim 7 is characterized in that:
Same conductive word lines top has several discrete diodes.
10, electric resistance transition memory according to claim 9 is characterized in that:
Form the PN diode between the semiconductor of second conduction type of one deck at least of the first conduction type heavily-doped semiconductor word line and word line top.
11, electric resistance transition memory according to claim 10 is characterized in that:
Second conductive type semiconductor of one deck at least of conductive word lines top is and the first conduction type heavily-doped semiconductor word line one, or be prepared on the first conduction type heavily-doped semiconductor word line, or be bonded on the first conduction type heavily-doped semiconductor word line by the circle crystalline substance by thin film deposition.
12, according to any described electric resistance transition memory of claim 1 to 6, it is characterized in that:
Described gating unit is a Schottky diode.
13, electric resistance transition memory according to claim 12 is characterized in that:
In two shallow channels in different depth, darker shallow channel is in order to isolate each word line, and more shallow shallow channel is in order to isolate the discrete Schottky diode of same word line top.
14, electric resistance transition memory according to claim 12 is characterized in that:
Same conductive word lines top has several discrete Schottky diodes.
15, electric resistance transition memory according to claim 12 is characterized in that:
Described electric resistance transition memory comprises conductive word lines, and described conductive word lines is the first conduction type heavily-doped semiconductor;
The lightly doped semiconductor of first conduction type is arranged on the word line of the described first conduction type heavily-doped semiconductor, above the light dope semiconductor, metal level is arranged.
16, electric resistance transition memory according to claim 15 is characterized in that:
Form Schottky contacts between the described metal level and the first conduction type light dope semiconductor layer.
17, electric resistance transition memory according to claim 15 is characterized in that:
The light dope semiconductor of conductive word lines top is and the word line one, or is prepared on the word line by thin film deposition, or is bonded on the word line by the circle crystalline substance.
18, according to any described electric resistance transition memory of claim 1 to 6, it is characterized in that:
Described gating unit is a bipolar transistor.
19, electric resistance transition memory according to claim 18 is characterized in that:
In two shallow channels in different depth, darker shallow channel is in order to isolate each word line, and more shallow shallow channel is in order to isolate the discrete bipolar transistor of same word line top.
20, electric resistance transition memory according to claim 18 is characterized in that:
Same conductive word lines top has several discrete bipolar transistors.
21, electric resistance transition memory according to claim 18 is characterized in that:
Described electric resistance transition memory comprises conductive word lines, and described conductive word lines is the first conduction type heavily-doped semiconductor;
Above the heavily doped conductive word lines of first conduction type is the semiconductor that second conduction type mixes;
The semi-conductive top that second conduction type mixes then is again the semiconductor that first conduction type mixes;
Formed bipolar transistor structure between the above-mentioned three-layer semiconductor.
22, electric resistance transition memory according to claim 18 is characterized in that:
At least the two-layer semiconductor of conductive word lines top be with the first conduction type heavily-doped semiconductor word line be one, or be prepared on the first conduction type heavily-doped semiconductor word line, or be bonded on the first conduction type heavily-doped semiconductor word line by the circle crystalline substance by thin film deposition.
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| CN 200910046487 CN101488514B (en) | 2009-02-23 | 2009-02-23 | Resistor conversion memory |
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| CN 200910046487 CN101488514B (en) | 2009-02-23 | 2009-02-23 | Resistor conversion memory |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102185104A (en) * | 2011-04-12 | 2011-09-14 | 中国科学院上海微系统与信息技术研究所 | Multilayer stacked resistance transit storage structure |
| CN102254927A (en) * | 2010-05-18 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Resistive random access memory (RRAM) and manufacturing method thereof |
| CN102117822B (en) * | 2009-12-31 | 2013-09-11 | 北京大学 | RRAM memory cell and preparation method thereof |
| CN104576924A (en) * | 2013-10-11 | 2015-04-29 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN107123734A (en) * | 2016-02-25 | 2017-09-01 | 三星电子株式会社 | Variable resistance memory device |
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| GB1347688A (en) * | 1970-05-22 | 1974-02-27 | Marconi Co Ltd | Semiconductor memory arrays |
| US4818717A (en) * | 1986-06-27 | 1989-04-04 | Energy Conversion Devices, Inc. | Method for making electronic matrix arrays |
| US5874760A (en) * | 1997-01-22 | 1999-02-23 | International Business Machines Corporation | 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation |
| US6339544B1 (en) * | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
| AU2002248493A1 (en) * | 2002-02-22 | 2003-09-09 | Intel Corporation | Dual trench isolation for a phase-change memory cell and method of making same |
| CN101262005A (en) * | 2008-04-11 | 2008-09-10 | 中国科学院上海微系统与信息技术研究所 | Phase change storage unit using Schottky base diode as selection tube and its making method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102117822B (en) * | 2009-12-31 | 2013-09-11 | 北京大学 | RRAM memory cell and preparation method thereof |
| CN102254927A (en) * | 2010-05-18 | 2011-11-23 | 中国科学院上海微系统与信息技术研究所 | Resistive random access memory (RRAM) and manufacturing method thereof |
| CN102185104A (en) * | 2011-04-12 | 2011-09-14 | 中国科学院上海微系统与信息技术研究所 | Multilayer stacked resistance transit storage structure |
| CN104576924A (en) * | 2013-10-11 | 2015-04-29 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN104576924B (en) * | 2013-10-11 | 2017-06-13 | 中芯国际集成电路制造(北京)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
| CN107123734A (en) * | 2016-02-25 | 2017-09-01 | 三星电子株式会社 | Variable resistance memory device |
| CN107123734B (en) * | 2016-02-25 | 2022-05-10 | 三星电子株式会社 | Variable resistance memory device |
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| CN101488514B (en) | 2013-02-06 |
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