KR20040030723A - Dual trench isolation for a phase-change memory cell and method of making same - Google Patents

Abstract

The present invention relates to a phase change memory device. The device includes a double trench isolation structure around the diode stack that is through to the bottom electrode. The invention also relates to a method of manufacturing a phase change memory device. The method includes forming two orthogonal and cross isolation trenches around the memory cell structure diode stack.

Description

DUAL TRENCH ISOLATION FOR A PHASE-CHANGE MEMORY CELL AND METHOD OF MAKING SAME}

As microelectronic technology has developed, there is a need for new data preservation schemes. One such preservation is chalcogenide phase-change technology. Typically, phase shift memory devices include a bottom electrode, also known as a "matchstick". The lower electrode may be a metal compound such as polysilicon, metal, or metal nitride.

One challenge in forming the lower electrode in the phase change memory cell is to reduce the cell size without losing the cross-talking increase between a given memory cell and a neighboring memory cell.

After formation of a recess in the substrate exposing the active region, a conformal introduction of the lower electrode is required. The bottom electrode material is typically any conductive or semiconductive material, such as polycrystalline silicon, metal, or metal compound. The conformal introduction of the bottom electrode material, which is polycrystalline silicon, can follow conventional introduction techniques, including chemical vapor deposition (CVD) techniques, which are known to those skilled in the art. Dopants are then introduced into the polycrystalline silicon to control the resistance and in one aspect to lower the resistance of the material. Suitable dopants include P type dopants such as boron introduced. From the combination of polysilicon and dopant, a silicidation process is required to form silicide of the lower electrode. Typically this process is doping, first annealing, wet strip and second annealing.

After proper doping and filling of the trench, a planarization step is required to remove any horizontal components of the lower electrode. Thereafter, a modifier material must be introduced into a portion of the bottom electrode material to combine and / or react with the bottom electrode material near the top. Formation of the different materials also prepares the top of the matchstick to form an appropriate ohmic contact with the phase change material. A modifier is introduced to raise the local resistance of the lower electrode material. By modifying a portion of the lower electrode material, the resistance at that modification portion can be changed. Since the modification material can be high resistance, the lower electrode is sufficiently suitable between the volume of the lower electrode and the memory material for the desired application. May not provide ohmic contact. In such a case, the modifying material may be introduced into the lower electrode at a depth below the exposed surface of the lower electrode. For example, the bottom electrode of polycrystalline silicon may have polycrystalline silicon at the exposed surface and have a quartz material at a depth below the exposed surface. In addition, a barrier material should be added to prevent cross contamination between the chalcogenide material and the lower electrode.

The present invention relates to a phase-change memory device. More specifically, the present invention relates to isolation of memory devices. In particular, the present invention relates to a phase change memory device having a minimum feature size.

For the way in which the above and other advantages of the present invention can be achieved, the present invention briefly described above will be described in more detail with reference to specific embodiments of the invention illustrated in the accompanying drawings. These drawings are merely representative of exemplary embodiments of the invention, and do not need to be drawn to scale, and therefore are not intended to limit the scope of the invention, hereinafter, further specificities and details of the invention will be described using the accompanying drawings. Will be explained.

1 is a schematic diagram of a memory device array in accordance with an embodiment of the present invention.

FIG. 2 schematically illustrates a cross-sectional side plan view of a portion of a semiconductor substrate having a first shallow trench isolation (STI) formed in a trench that defines the z-direction thickness of a memory cell in accordance with an embodiment of the present invention. .

3 is a front view of one embodiment of the present invention.

4 (a) is an elevational sectional view of the structure shown in FIG. 3.

4B is an elevational sectional view after further processing the structure shown in FIG. 4A.

FIG. 4C is an elevational sectional view after further processing the structure shown in FIG. 4B. FIG.

FIG. 5 is an elevational slope after further processing the structure shown in FIG. 4C and showing the selected structure. FIG.

FIG. 6 illustrates a cross-sectional view of the structure of FIG. 5, after the dopant is introduced to form a diode stack portion of a memory cell structure in accordance with one embodiment of the present invention.

FIG. 7 illustrates the structure of FIG. 6, which illustrates a process of introducing a masking material onto a memory cell structure according to an embodiment of the present invention.

FIG. 8 shows a schematic front view of the structure of FIG. 2, in accordance with another embodiment of the present invention, wherein the second trench etch removes a substantial portion of the first shallow trench isolation structure.

FIG. 9 is a cross-sectional view of the structure of FIG. 8, illustrating after the x-direction thickness of the semiconductor substrate structure and after formation of a second STI trench orthogonal to the first STI structure. FIG.

FIG. 10 is the same cross-sectional view of the structure of FIG. 9, illustrating after filling of the second STI trench in accordance with one embodiment of the present invention. FIG.

FIG. 11 is a front view after planarization of the structure shown in FIG. 10, illustrating a double trench aspect of the present invention. FIG.

12 is an elevational slope of a selected structure of the memory device of the present invention, showing after planarization.

FIG. 13 is another elevational slope of the selected structure of the memory device of the present invention, showing after planarization.

FIG. 14 is a diagram illustrating the structure of FIG. 5 or 12, after further processing to form a dielectric material having a reducer material and a recess through the reducer material. FIG.

FIG. 15 is the same cross-sectional view of the structure of FIG. 14, illustrating the introduction of electrode material onto a structure in accordance with one embodiment of the present invention. FIG.

FIG. 16 is the same cross sectional view of the structure of FIG. 15, showing after recess filling and planarization. FIG.

FIG. 17 is the same cross-sectional view of the structure of FIG. 16, illustrating the volume of memory material and after the second conductor has been introduced onto the structure, in accordance with an embodiment of the present invention.

FIG. 18 is the same cross-sectional view of the structure of FIG. 17, illustrating the dielectric material after it is introduced on the second conductor and the third conductor connected to the first conductor, in accordance with an embodiment of the invention.

19 is a graphical representation of volume setting and reset of phase change memory materials in terms of temperature and time.

The present invention relates to a memory device used with a phase change material for data storage. The device utilizes a bottom electrode material referred to as a "matchstick." Below the matchstick, a diode stack is provided to activate the bottom electrode. After the first isolation trench is formed, a second isolation trench is formed. The second isolation trench is orthogonal to the first isolation trench. The lower electrode is formed on the diode stack portion of the memory cell structure, and the volume of the phase change memory is disposed above the match stack. A high resistance metal compound can be used as the lower electrode, or a polysilicon compound can be used.

The following description includes terms such as upper, lower, first, second, etc., which are for illustrative purposes only and are not intended to be limiting. Embodiments of the device or article of the invention described herein may be manufactured, used, or shipped in a variety of positions and orientations. Reference will be made to the drawings, wherein like reference numerals will be given to similar structures in the drawings. To more clearly show the structure of the present invention, the drawings herein schematically depict an integrated circuit structure. Thus, for example, the actual appearance of the fabrication structure in a photomicrograph may look different, but still includes the essential structure of the invention. Moreover, the drawings only show the structures necessary to understand the invention. In order to maintain the clarity of the drawings, additional structures known in the art are not included.

Figure 1 shows a schematic diagram of an embodiment of a memory array consisting of a plurality of memory elements provided and formed in connection with the present invention. In this example, the circuit of the memory array 5 comprises an array having a memory element 30 electrically connected in series with the isolation device 25 on a portion of the chip. In one embodiment, address lines 10 (e.g., columns) and 20 (e.g., rows) are connected to the external addressing circuit in a manner known to those skilled in the art. The purpose of a memory element array in combination with a separation device is to allow each discrete memory element to be read and written without compromising the information stored in adjacent or remote memory elements of the array.

A memory array, such as memory array 5, may be formed in a portion of the substrate, including the entire portion. Typical substrates include semiconductor substrates such as silicon substrates. Other substrates are also suitable, including, but not limited to, substrates comprising ceramic materials, organic materials, or glass materials as part of the underlying structure. In the case of a silicon semiconductor substrate, the memory array 5 can be fabricated on the area of the substrate at the wafer level, after which the wafer can be reduced through singulation to discrete dies or chips, Some or all of the die or chip has a memory array formed thereon. Additional addressing circuitry such as sense amplifiers, decoders, etc. may be formed in a form similar to that known to those skilled in the art.

2-18 illustrate the fabrication of the representative memory device 15 of FIG. 1, in accordance with various embodiments. 2 shows a portion of the substrate 100, ie a semiconductor substrate. In one embodiment, a P type dopant, such as boron, is introduced into deep portion 110. In one example, a suitable concentration of P-type dopant of about 5x10 ¹⁹ to create a typically P ⁺⁺ deep part 110 of the substrate 100 - is 1x10 ²⁰ atoms / cm ³ or so. In this example, an epitaxial portion 120 of P type epitaxial silicon is located above the deep portion 110 of the substrate 100. In one example, the dopant concentration in epitaxial portion 120 is about 10 ¹⁶ - is approximately 10 ¹⁷ atoms / cm ^3. Introduction and formation of epitaxial portion 120 as P type and deep portion 110 as P ⁺⁺ type portion may be by techniques known to those skilled in the art. 2 also illustrates the formation of signal line material 140 by implanting ions to a desired depth. As is known in the art, other embodiments may be used that do not utilize constructs such as P ⁺⁺ portions and P epitaxial portions. One example is a non-epitaxial wafer.

2 also shows a first shallow trench isolation (STI) structure 130 formed in the epitaxial portion 120 of the structure 100. The first STI structure 130 may be formed with the help of a hard mask 122, such as a silicon nitride material. 3 is a front view of the substrate 100 after patterning the second mask 124 over both the first STI structure 130 and the hard mask 122. The second mask 124 is a first blanket that is deposited and then patterned. The second mask 124 is used during the second etching orthogonal to the first STI structure 130. In a two-process etch, the second mask 124 is patterned to be orthogonal to the first STI structure 130 and may be one feature-width (1F-width) strips. .

FIG. 4 (a) is an elevational sectional view of the structure shown in FIG. 3, taken through section line A-A '. The second mask 124 is shown as protecting the area to be a plurality of separate diode stacks. 4B is an elevational cross sectional view of the structure shown in FIG. 3 taken through line B-B 'during etching to remove hard mask 122. FIG. Hard mask 122 is a nitride, such as silicon nitride, and etching may remove a portion of first STI structure 130, which is typically an oxide. Such etching conditions are known in the art.

FIG. 4C is an elevational sectional view after further processing the structure shown in FIG. 4B. FIG. After the removal etch of the hard mask 122, silicon etching is performed with the same patterning of the second mask 124. The etching method is optional to leave oxide of the first STI structure 130. After patterning and etching the silicon, it is an N-type dopant introduced into the base of each recess, about 10 ¹⁸ - 10 to form a pocket having a dopant concentration of ²² atoms / cm ³ approximately 200.

In this embodiment, the structure is substantially four winged quadrilateral recesses, but after silicon etching, the recess is filled with oxide to form a second shallow trench (STT) structure as shown in FIG. 5. Is formed. 5 is an elevational slope of a selected structure of the memory device of the present invention. In this embodiment, the formation of the first STI structure 130 precedes the formation of the SST structure 132. The first STI structure 130 is substantially continuous at the top surface. Because of silicon etching leaving the oxide material of the first STI structure 130, the SST structure 132 is substantially discontinuous. Thus, the SST structure 132 includes an intermittent top surface shallow trench isolation structure disposed in the second trench and the first STI structure 130 includes a continuous upper surface shallow trench isolation structure disposed in the first trench. do.

5 also shows the formation of a separation device 25 that is part of the diode stack. Separation device 25 is about 10 ¹⁷ - 10 ²² N-type silicon portion 150 that atoms / cm may have a dopant concentration of about ^three and about 10 ¹⁹ - which may have a dopant concentration of 10 ²¹ atoms / cm ³ degree And a PN diode formed of P-type silicon 160. While the PN diode is shown as the isolation device 25, it will be appreciated that other isolation structures are likewise suitable. Such separation devices include, but are not limited to, MOS devices. The memory cell structure 134 is shown as including an epitaxial portion 120, a signal line material 140, an N Si portion 150, and a P + Si portion 160 of P type epitaxial silicon.

The memory cell feature may be defined as the minimum geometry that defines the memory cell. For example, the first feature F ₁ can define an edge of the memory cell structure 134. The second feature F ₂ can define a first edge geometry of the first STI structure 130. The third feature F ₃ can define a second edge geometry of the memory cell structure 134. Finally, the fourth feature F ₄ may define the edge geometry of the SST structure 132. If the first and second features are substantially the same, they can be represented as 2F. In any event, the first through fourth features, when defined in a right angle configuration, may be represented as four feature squares (4F ² ) 136. Under the selected structure, it can be seen that the projection of 4F ² 136 shows the unit cell of the memory isolation of the present invention. In the present invention, a double trench isolation structure is achieved that serves to isolate the diode stack of the memory cell structure 134 by a distance of at least 1F in all directions. In this embodiment, the reducer material 170 (see FIG. 6) has not yet been formed and the surface that exposes the first STI structure 130, the SST structure 132 and the P-type silicon portion 160 by planarization. Is generated.

Since the memory cell structures 134 are separated by a double trench configuration, the possibility of crosstalk between adjacent memory cell structures is reduced. In addition, the trench depth may be between about 3,000 microns and about 7,000 microns, and the SST structure 132 may have an overall depth in the range of about 500 microns to about 3,500 microns. Trench depth is limited by etching time constraints. In addition, the 4F ² configuration is easily scalable, and is a simplified part for integrating with design rules as a geometry to keep decreasing from, for example, 0.35 μM, 0.25 μM, 0.18 μM, 0.13 μM, 0.11 μM, and the like. . In addition, the degree of vertical beta in the diode stack is increased compared to the prior art.

FIG. 6 illustrates after additional fabrication operations in memory cell regions 135A and 135B for the structure of FIG. 4C. A first conductor or signal line material 140 is positioned over the epitaxial portion 120 of the substrate 100. In one example, first conductor or signal line material 140 is, for example, a phosphoric (phosphorous) or arsenic of about 10 ¹⁸ - N-type, such as N ⁺ silicon is formed by introducing a concentration of 10 ²² atoms / cm ³ degree Doped polysilicon. In this example, the first conductor or signal line material 140 functions as an address line, a row line such as the row line 20 of FIG. 1. Above the first conductor or signal line material 140 is a separation device such as the separation device 25 of FIG. 1. In one example, the separation device is about 10 ¹⁷ - 10 ²² N-type silicon portion 150 that atoms / cm may have a dopant concentration of about ^three and about 10 ¹⁹ - which may have a dopant concentration of 10 ²¹ atoms / cm ³ degree PN diode formed of P-type silicon portion 160. While the PN diode 25 is shown, it will be appreciated that other isolation structures are likewise suitable. Such isolation devices include, but are not limited to, MOS devices.

Referring again to FIG. 6, above the isolation device 25 in the memory cell regions 135A and 135B, in this example, a reducer material 170 of refractory metal silicide, such as CoSi ₂ (cobalt silicide), is located. do. Reducer material 170 may be formed in one of several portions of the process of the present invention. If reducer material 170 is a metal silicide, it may be suitably formed as self-aligned silicide or salicide. Reducer material 170 may be formed at or later in this portion of the process. In one aspect, the reducer material 170 functions as a low resistance material in the manufacture of peripheral circuits, such as addressing circuits of circuit structures on a chip. Thus, reducer material 170 may not be necessary in terms of memory device formation as described. Nevertheless, because of its low resistivity property, what is included as part of the memory cell structure between the isolation device 25 and the memory element 30 is used in this embodiment.

FIG. 7 shows after introducing masking material 180 for the structure of FIG. 6. In one embodiment, a suitable material for masking material 180 is Si _x O _z (silicon oxide) or Si _x O _z N, although both in stoichiometric and other solid solution ratios. Other materials such as _y (silicon oxynitride) may be used, but are dielectric materials such as silicon nitride (Si ₃ N ₄ ) in both stoichiometric and other solid solution ratios.

Masking material 180 may function as a patterning to protect portions of first STI structure 130 and to protect memory cell region 135A for subsequent etching operations. In this embodiment, the masking material 180 may not be patterned and may function as a two-etch process etch stop. For example, if a contact corridor is formed, the two etch process allows for faster oxide etch to stop on the masking layer 180 and stop on silicon such as unlanded contact. A slower nitride etch follows.

In another embodiment, the formation of the separation device 25 may be performed prior to the formation of the SST structure 132. In this embodiment, the masking material 180 includes a patterned mask similar to the second mask 124. 8 is a front view of an xz perspective view of the substrate 100 illustrating this embodiment. In the present embodiment, planarization is preferably performed to such an extent that the hard mask 122 is entirely removed. Thus, the etching process flow can be simplified because no nitride etching is required. Formation of separation device 25 is completed such that P-type silicon portion 160 is exposed in FIG. 8. Preferably, the etching is performed with an etching method with selectivity that does not substantially support the material of the S-type structure 130 on silicon of the P-type silicon portion 160 or the conductive material 150. Such etching methods are known in the art and may be selected based on the doping that forms the separation device 25. From the patterning of the hard mask 180, the trench 90 (to be formed) will receive the SST structure (also to be formed).

FIG. 9 illustrates an xy perspective view of the structure of FIG. 8, illustrating the formation of trench 190 by patterning the x direction thickness of the memory cell material. FIG. 9 shows two memory cells 145A and 145B patterned from the memory cell region 135A shown in FIG. In this example, patterning can be accomplished using conventional techniques to etch refractory metal silicide and silicon material except masking material 180. In this example, the definition of the x-direction thickness includes etching of the conductive material 150 (N type silicon in this example) of the memory line stack to define the memory cells 145A, 145B of the memory cell region 135A. do. In the case of etching, the etching proceeds through the memory line stack to a signal line, which in this example is part of the conductor or in this case conductive material 150. Regular etching can be used to stop the etching at this point.

FIG. 10 illustrates an xy perspective view of the structure of FIG. 8, showing after filling the trench 190. Following patterning and etching, the N-type dopant is introduced at the base of each trench 190, 10 ¹⁸ of the trench (190) is 10 ²² atoms / cm ³ degrees of pockets 200 having a dopant concentration is formed, An N ⁺ region is formed between the memory cells 145A and 145B. The pocket 200, in a sense, functions to maintain the continuity of the row lines.

As shown in FIG. 10, an SST structure 132 is formed on the substrate 100 to substantially fill the trench 190. Although reducer material 170 is shown as provided in FIG. 10, it may be formed later, as disclosed herein. The SST structure 132 is formed in the second isolation trench 190 in a direction orthogonal to the first STI structure 130. SST structure 132 may be planarized to expose the diode stack. After planarization, both the first STI structure 130 and the SST structure 132 are exposed.

Prior to formation of the first STI structure 130 and / or the SST structure 132, as an alternative to processing, a thermal dielectric film may be formed in each trench (es). The thermal dielectric film (s) serve to help better formation of the trench (es).

11 shows a front view of the structure achieved after planarization. The first STI structure 130 is shown as being cut by etching the trench 190 (not shown) and filling it to form the SST structure 132. That is, the STI structure 130 has a discontinuous top surface and the SST structure 132 has a substantially continuous top surface. C-C 'shown in FIG. 11 shows a sectional view of the structure of FIG.

Memory cell structure 134 is also shown in FIG. The memory cell structure 134 may have an exposed layer, such as a reducer material 170, or, if not yet formed, a P type silicon portion 160, or the like. 11 shows a substantial separation of the memory cell structure 134, which is surrounded by two second STI structures 130 and two SST structures 132. The memory cell structure 134 is spaced apart from the adjacent memory cell structure 134 by any of four features. That is, the spaced separation of memory cell structure 134 is minimal by the smallest dimension of 4F ² configuration 136. Figure 11 also illustrates one inventive structure of the present invention, wherein a 4F ² 136 configuration is provided within dash line 136 to define the unit cell of the memory device.

Fig. 12 is an elevational elevation view of a selected structure of the memory device of the present invention according to this embodiment. In this embodiment, the formation of the first STI structure 130 precedes the formation of the SST structure 132 and the etching of the trench 190 is substantially similar for both the oxide of the first STI structure 130 and silicon. It is performed at the etch rate. Moreover, masking material 180 is not shown to expose SST structure 132. The memory cell structure 134 is exposed by the cut-away of the SST structure 132 ′. It can be seen that the projection of 4F ² 136 under the selected structure shows the unit cell of the memory isolation of the present invention. In the present invention, a double trench isolation structure is achieved that serves to separate the diode stack of the memory cell structure 134 by a distance of at least 1F in all directions. In this embodiment, the reducer material 170 has not yet been formed, and the planarization creates a surface that exposes the first STI structure 130, the SST structure 132, and the P-type silicon portion 160.

FIG. 13 is an elevational slope of the selected structure shown in FIG. 12, illustrating the formation of salicide of reducer material 170 after formation. Formation of salicide of reducer material 170 may need to follow planarization of the memory device.

FIG. 14 illustrates the structure of FIG. 5 or 12, illustrating planarization of the SST structure 132 and subsequent formation of optional salicylation of the reducer material 170. The depth of the first STI structure 130 and the SST structure 132 may vary depending on the desired application. In one embodiment, the depth of the first STI structure 130 is in the range of about 3,000 mm 3 to about 7,000 mm 3. SST structure 132 may have an overall depth in the range of about 500 microns to about 3,500 microns. In one embodiment, the total depth of the first STI structure starting at the bottom of the reducer material 170 is about 5,300 mm 3, and the total depth of the SST structure 132 is about 2,500 mm 3.

One aspect of the present invention includes the relative depth of shallow trench isolation structures. The memory cell structure 134 includes a P + Si structure 160 disposed on the N Si structure 150. P + Si structure 160 has a top and a bottom. N Si structure 150 also has a top and a bottom. As shown in FIG. 14, the SST structure 132 also has a top and a bottom, the bottom of the SST structure 132 is below the P + Si structure 160, and the top of the SST structure 132 has a P + Si structure ( 160) on the bottom.

Dielectric material 210 is formed and formation of trench 220 through dielectric material 210 is performed to expose reducer material 170. Formation of trench 220 may be performed using etch patterning with etchant (s) to etch dielectric material 210, and reducer material 170 may function as an etch stop. 170) may be optional.

Fig. 15 shows the process of the present invention for forming the lower electrode in the phase change memory device using the metal compound film of the present invention. The memory line stack may be referred to as the active region. FIG. 15 illustrates the structure of FIG. 14, showing after the introduction of the lower electrode material 230, which may be a conductive or semiconductive polysilicon material or a metal compound material, but may be referred to as a metal compound film. In one example, metal compound film 230 is a metal nitride compound, such as TaN, which may be provided in a stoichiometric or other metal compound film solid solution ratio, depending on the desired resistance.

The introduction is conformal in the sense that the metal compound film 230 is introduced along the sidewalls and the base of the trench 20 so that the metal compound film 230 is in contact with the reducer material 170. The conformal introduction of metal compound film 230, which is an inventive polysilicon, metal nitride and / or silicide compound, can follow conventional introduction, including CVD techniques, known to those skilled in the art.

As shown in FIG. 15, trench 220 may be referred to as a recess formed in first dielectric 210 to expose at least a portion of a memory cell stack. Although the recess is referred to as trench 220, the type of recess may be selected from substantially circular recesses, right angle (square) recesses and trench recesses.

The metal compound film 230 includes metal and at least one of nitrogen and silicon. The desired mixing of the metal compound may be performed by CVD of at least one component of nitrogen and silicon in relation to the metal. The material of the metal compound film 230 is preferably a high resistance metal compound such as metal nitride, refractory metal nitride, metal silicon nitride, refractory metal silicon nitride, metal silicide and refractory metal silicide. Preferably, the synthesis of the metal compound film 230 is controlled by the amount of feed stream to the CVD tool. According to certain embodiments, other CVD techniques such as plasma enhanced CVD (PECVD) may be used.

In another embodiment, the formation of the metal compound film 230 is performed by physical vapor deposition (PVD), and a target having the desired synthesis for the final metal compound film is selected. Alternatively, a plurality of targets may be combined to achieve desirable metal compound film synthesis. In PVD or CVD, the coverage defined as the ratio of wall deposition thickness to top deposition thickness is in the range of about 0.25 to about 1, preferably about 0.5. In the present invention, CVD formation of the lower electrode is preferred.

When metal nitride is selected for the metal compound film 230, the metal may be selected from Ti, Zr, and the like. It may also be selected from Ta, Nb and the like. It may also be selected from W, Mo and the like. It may also be selected from Ni, Co and the like. Preferably, the metal nitride is a refractory metal nitride compound of molecular formula M _x N _y . The ratio of M: N is in the range of about 0.5: 1 to about 5: 1, preferably in the range of about 0.6: 1 to about 2: 1, and most preferably about 1: 1. For example, one embodiment of the present invention has a Ta _x N ratio of about 0.5: 1 to about 5: 1, preferably about 0.6: 1 to about 2: 1, and most preferably 1: 1 ratio. _y compound. Another embodiment is a W _x N _y compound in the range from about 0.5: 1 to about 5: 1, preferably in the range from about 0.6: 1 to about 2: 1, most preferably about 1: 1.

In another embodiment of the present invention, the metal compound film 230 may be a metal silicon nitride compound. The metal may be selected from metals which may be selected from Ti, Zr and the like. In addition, the metal may be selected from Ta, Nb, and the like. In addition, the metal may be selected from W, Mo, and the like. In addition, the metal may be selected from Ni, Co, and the like. The metal silicon silicide compound may have a molecular formula M _x Si _z N _y and the ratio of M: Si: N is in the range of about 1: 0.5: 0.5 to about 5: 1: 1. Preferably such ratio is in the range of about 1: 1: 0.5 to 1: 0.5: 1, most preferably about 1: 1: 1. In one embodiment, the bottom electrode material compound is about 1: 0.5: 0.5 to about 5: 1: 1, preferably about 1: 1: 0.5 to 1: 0.5: 1, most preferably 1: 1: 1 Ti _x Si _y N _z .

In another embodiment, the lower electrode can be a metal silicide compound. The metal may be selected from metals which may be selected from Ti, Zr and the like. In addition, the metal may be selected from Ta, Nb, and the like. In addition, the metal may be selected from W, Mo, and the like. In addition, the metal may be selected from Ni, Co, and the like. The metal silicide compound may have a molecular formula M _x Si _z and the ratio of M: Si is in the range of about 0.5: 1 to about 5: 1. In one embodiment, the bottom electrode material compound is Ti _x Si _y in the range from about 0.5: 1 to about 5: 1, preferably in the range from about 0.6: 1 to 2: 1, most preferably 1: 1. In another embodiment, the lower electrode material compound is W _x Si _y in the range of about 0.5: 1 to about 5: 1, preferably in the range of about 0.6: 1 to about 2: 1, most preferably about 1: 1.

FIG. 16 shows another process of the structure shown in FIG. 15. Following the formation of the metal compound film 230, the recess 220 is filled with the second dielectric 250. The second dielectric 250 may be formed by CVD of a silicon containing material selected from silicon oxide, such as a tetra ethly ortho silicate (TEOS) process or the like. As shown in FIG. 16, following formation of the second dielectric 250, all material present above the top level 240 of the recess is removed. Removal of material may be performed by processes such as chemical mechanical planarization (CMP), mechanical planarization, and the like. Removal of material may be performed by processes such as isotropic etchback, anisotropic etchback, and the like.

FIG. 17 illustrates after introducing a volume of memory material 290 (indicated as memory element 30 in FIG. 1) for the structure of FIG. 16. In one example, memory material 290 is a phase change material. In a more particular example, the memory material 290 is chalcogen element (s). Examples of phase change memory material 290 include, but are not limited to, synthesis of a class of Te _x Ge _y Sb _z (tellerium-germanium-antimony) materials in both stoichiometric and solid solution ratios. In one example in accordance with current technology, a volume of memory material 290 is introduced and patterned to a thickness in the range of about 300 kPa to about 6,000 kPa.

Above the volume of memory material 290 in the structure of FIG. 17, barrier materials 300 and 310 of Ti (Titanium) and TiN (Titanium Nitride), respectively, are positioned. In one aspect, the barrier material prevents diffusion between the volume of memory material 290 and the second conductor or signal line material (eg, second electrode 10) over the volume of memory material 290. To function. A second conductor or signal line material 315 is positioned over the barrier material 300, 301. In this example, the second conductor or signal line material 315 functions as an address line, column line (eg, column line 10 of FIG. 1). The second conductor or signal line material 315 is patterned to be generally orthogonal to the first conductor or signal line material 140 in this embodiment (column lines are orthogonal to the row lines). For example, the second conductor or signal line material 315 is an aluminum material, such as aluminum alloy. Methods for introduction and patterning of barrier material and second conductor or signal line material 315 include techniques known to those skilled in the art.

18 illustrates the introduction of dielectric material 330 on second conductor or signal line material 315 for the structure of FIG. 17. Dielectric material 330 is, for example, SiO ₂ or other suitable material that surrounds second conductor or signal line material 315 and memory material 290 to electrically separate such structures. Following introduction, the dielectric material 330 is planarized and vias such as contact corridors are formed in the portion of the structure through the dielectric material 330, the dielectric material 210 and the masking material 180 to the reducer material 170. do. The via is filled with a conductive material 340 such as tungsten (W) and a barrier material 350 such as a combination of Ti and TiN. Techniques for introducing dielectric material 330, forming and filling conductive vias, and planarization techniques are known to those skilled in the art.

In addition, the structure shown in FIG. 18 is introduced and patterned to mirror the first conductor or signal line material 140 (eg, row line) formed on the substrate 100. Mirror conductor line material 320 reflects first conductor or signal line material 140 and is connected to first conductor or signal line material 140 through conductive vias. By reflecting a doped semiconductor such as N type silicon, in one aspect, mirror conductor line material 320 is resistive of conductor or signal line material 140 in a memory array, such as memory array 5 shown in FIG. Function to reduce. Suitable materials for the mirror conductor line material 320 include aluminum materials such as aluminum or aluminum alloys.

In the above description of the formation of a memory element such as the memory element 15 in FIG. 1, the metal compound film 230 is an electrode, and between the memory material and the conductor or signal line (e.g., row line and column line). Defined and have improved electrical properties. In the described embodiment, the resistance of the electrode is selected to make the desired metal compound film 230 as disclosed herein. In this method, the voltage supplied from the second conductor or signal line material 320 or the first conductor or signal line material 140 to the memory material 290 may be near the volume of the memory material 290, and may be phased. The consumption of energy causing change can be minimized. Description of the formation of one memory element of the memory array 5 is detailed. Other memory elements of the memory array 5 can be manufactured in the same way. Many memory elements of the memory array 5, and possibly all memory elements, as well as other integrated circuits, can be fabricated at the same time.

19 shows a graph of setting and resetting of a volume of phase change memory material. Referring to FIG. 1, the setting and reset memory element 15 (addressed by column line 10a and row line 20a), in one example, supplies a voltage to column line 10a, and FIG. 1. Introducing a volume of memory material 30 as shown in FIG. 12 or a memory material 290 as shown in FIG. The current causes the temperature to increase in the volume of memory material 30. Referring to FIG. 19, in order to amorphize the volume of the memory material, the volume of the memory material is heated to a temperature above the amorphous temperature T _M. Once the temperature exceeds T _M , the volume of memory material cools down or cools down quickly (by removing the current flow). Quenching is performed at a rate t ₁ which is faster than the rate at which the volume of memory material 30 is crystallized, so that the volume of memory material 30 remains amorphous. In order to crystallize the volume of the memory material 30, the temperature is raised by the current flow to the crystallization temperature for the material, and maintained at that temperature for a time sufficient to crystallize the material. After that time, the volume of memory material is cooled (by removing the current flow).

In each of these examples of resetting and setting the volume of memory material 30, the importance of focusing the temperature transfer in the volume of memory material 30 is illustrated. One way to do this is to modify part of the electrode as described above. The inset of FIG. 19 shows a memory cell 15 having an electrode with a modification 35 (shown as a resistor) to concentrate heating (current) in the volume of memory material 30.

In the previous example, the volume of memory material 30 is heated to a high temperature to amorphousize the material and reset the memory element (eg, program 0). Heating the volume of memory material to a lower crystallization temperature crystallizes the material and sets up the memory device (eg, program 1). It will be appreciated that the relevance of each of the resets and sets with amorphous and crystalline materials is customary and at least contrary practice may be employed. Also, from this example, it will be appreciated that the volume of memory material 30 need not be partially set or reset by varying the current flow and by the duration through the volume of memory material.

Another advantage is provided when using metal compound electrodes. Because there is a metal-to-metal interface between the lower electrode and the volume of memory material, there may be an interface resistance lower than that of the doped polysilicon chalcogenide interface.

Because of the chemical composition of the metal compound film 230 of the present invention forming the lower electrode, the process flow is simplified. For example, injection of polysilicon and its activation in the process flow is not necessary. The doped polysilicon bottom electrode requires treatment such as a doping process, annealing process to activate the doped electrode and make it a conductive barrier layer between the top surface of the bottom electrode, forming the top surface for enhanced heating at the top surface. It requires processing to modify it.

In contrast, the lower electrode of the present invention is formed of a metal compound film 230, and then a dielectric material is filled therein. Thereafter, CMP may be performed to deposit the memory material 290.

Those skilled in the art will appreciate that various changes in details, materials, and configurations of the techniques and depicted parts and method steps to illustrate the nature of the invention, without departing from the spirit and scope of the invention as described in the appended claims. It will be appreciated that other changes are possible.

Claims (27)

In a memory device, A memory cell structure, A first isolation trench adjacent the memory cell structure; A second isolation trench adjacent to the memory cell structure and orthogonal to the structure of the first isolation trench, A first edge of the memory cell structure defines a first feature of a unit cell, A second edge of the memory cell structure defines a second feature of the unit cell, An edge of the first isolation trench defines a third feature of the unit cell, An edge of the second isolation trench defines a fourth feature of the unit cell. Memory device. The method of claim 1, And the memory cell structure, the first isolation trench and the second isolation trench define four feature size squares (4F ² ). The method of claim 1, And the memory device is disposed on a substrate, and the first isolation trench is disposed on the substrate deeper than the second isolation trench. The method of claim 1, And the memory device is disposed on a substrate, the first isolation trench comprises a discontinuous top surface, and the second isolation trench comprises a substantially continuous top surface. The method of claim 1, And the memory cell structures are separated and separated by a single feature (1F). The method of claim 1, And the first isolation trench comprises a single shallow trench isolation structure. The method of claim 1, The memory cell structure, A P + Si structure disposed on an N Si structure, the P + Si structure having a top and a bottom, the N Si structure having a top and a bottom, and the second isolation trench having a top and a bottom; And a bottom of the second isolation trench beneath the P + Si structure. The method of claim 1, The memory cell structure, A P + Si structure disposed on an N Si structure, The P + Si structure has a top and a bottom, The N Si structure has a top and a bottom, The second isolation trench has a top and a bottom, The bottom of the second isolation trench is below the P + Si structure, The top of the second isolation trench is above the bottom of the P + Si structure. The method of claim 1, The memory cell structure includes a diode stack structure, The diode stack structure, N + Si row select, An N Si layer disposed on said N + Si row selection, A P + Si layer disposed on the N Si layer, A memory device comprising a silicide layer. In the process of forming a memory device, Forming a first trench in the substrate, Forming a second trench in the substrate, the second trench crossing the first trench, Forming a memory cell structure diode stack adjacent the first trench and the second trench. Memory device formation process. The method of claim 10, And the second trench is orthogonal to the first trench. The method of claim 10, And the second trench is shallower than the first trench. The method of claim 10, Forming the first trench comprises an etching process to achieve an etch depth in the range of about 3,500 kPa to about 7,000 kPa. The method of claim 10, Forming the second trench comprises an etching process to achieve an etching depth in the range of about 500 kPa to about 3,500 kPa. The method of claim 10, After forming the first trench, Filling the first trench with a separation dielectric, And planarizing the substrate. The method of claim 10, After forming the first trench, Forming a thermal dielectric film in the first trench, Filling the first trench with a separation dielectric, And planarizing the substrate. The method of claim 10, After forming the second trench, Filling the second trench with a separation dielectric, And planarizing the substrate. The method of claim 10, After forming the second trench, Forming a thermal dielectric film in the second trench, Filling the second trench with a separation dielectric, And planarizing the substrate. The method of claim 10, And forming a diode stack adjacent to the first trench and the second trench. The method of claim 10, Forming a diode stack adjacent to the first trench and the second trench, Forming a first dielectric film on the semiconductor diode, A recess is formed in the first dielectric film to expose the diode stack, Forming a lower electrode layer on the recess; And introducing a volume of phase change memory material on said lower electrode film. The method of claim 10, Forming a diode stack adjacent to the first trench and the second trench, Filling the first trench and the second trench, And forming a self-aligned silicide layer on the diode stack. A phase change memory device, A first trench disposed on the substrate, A second trench disposed in the substrate, the second trench being orthogonal to the first trench; A diode stack disposed adjacent the first trench and the second trench; A first dielectric disposed on the diode stack; A recess disposed in the first dielectric to expose the diode stack; A lower electrode disposed in the recess of the first dielectric; A volume of phase change material disposed on the lower electrode, At least one address line connected to said phase change material; Phase change memory device. The method of claim 22, An intermittent upper surface shallow trench isolation structure disposed in said second trench, And a substantially continuous top surface shallow trench isolation structure disposed in said first trench. The method of claim 23, The lower electrode, And further comprising a metal compound layer disposed on the diode stack in the recess, wherein the metal compound is formed from polysilicon, metal nitride, refractory metal nitride, metal silicon nitride, refractory metal silicon nitride, metal silicide and refractory metal silicide. Phase change memory device selected. A first trench disposed on a substrate, a second trench disposed on the substrate, the second trench being orthogonal to the first trench, a diode stack disposed adjacent to the first trench and the second trench; A first dielectric disposed on the diode stack, a recess disposed in the first dielectric to expose the diode stack, a lower electrode disposed in the recess of the first dielectric, and disposed on the lower electrode And a dedicated memory chip having a volume of phase shifted material and a memory array comprising addressing circuitry connected to the memory array. The method of claim 25, And the memory array further comprises an intermittent top surface shallow trench isolation structure disposed in the second trench and a substantially continuous top surface shallow trench isolation structure disposed in the first trench. The method of claim 26, The lower electrode includes a metal compound layer disposed on the diode stack in the recess, wherein the metal compound is polysilicon, metal nitride, refractory metal nitride, metal silicon nitride, refractory metal silicon nitride, metal silicide and fire resistance Device selected from metal silicides.