CN1533606A - Dual trench isolation structure for phase-change memory cell and method of making same - Google Patents

Dual trench isolation structure for phase-change memory cell and method of making same Download PDF

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CN1533606A
CN1533606A CNA028132548A CN02813254A CN1533606A CN 1533606 A CN1533606 A CN 1533606A CN A028132548 A CNA028132548 A CN A028132548A CN 02813254 A CN02813254 A CN 02813254A CN 1533606 A CN1533606 A CN 1533606A
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groove
isolated
silicon
diode stack
substrate
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丹尼尔·徐
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Intel Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H10N70/8413—Electrodes adapted for resistive heating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

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Abstract

The invention relates to a phase-change memory device. The device includes a double-trench isolation structure around the diode stack that communicates to the lower electrode. The present invention also relates to a method of making a phase-change memory device. The method includes forming two orthogonal and intersecting isolation trenches around a memory cell structure diode stack.

Description

The two groove isolation constructions and the manufacture method thereof of phase-changing memory unit
Technical field
The present invention relates to phase-change memory device.More specifically, the present invention relates to the isolation of storage component part.Especially, the present invention relates to a kind of phase-change memory device with minimal characteristic (feature) size.
Background technology
Along with the progress of microelectric technique, the demand of scheme that new data is preserved has appearred.A kind of such data preservation scheme is the chalcogenide phase change technique.Usually, phase-change memory device comprises bottom electrode, is also referred to as " match stick ".Bottom electrode can be polysilicon, metal or such as the metallic compound of metal nitride.
A challenge that forms bottom electrode in phase-changing memory unit is to dwindle cell size, and does not increase crosstalking between given memory cell and the neighbor memory cell simultaneously.
In substrate, be formed for exposing after the groove of active area (active region), need suitable shape (conformal) to introduce lower electrode material.Lower electrode material generally is any conduction or semi-conducting material, for example polysilicon, metal or metallic compound.The suitable shape of polysilicon lower electrode material is introduced (introduction) can follow traditional introducing technology known in those skilled in the art, comprises the chemical vapor deposition (CVD) technology.After this, dopant being introduced polysilicon adjust resistivity, wherein is the resistivity that reduces material on the one hand.Suitable dopant is P type dopant, for example boron of Yin Ruing.From in conjunction with polysilicon and dopant, need a silicification technics to form the silicide of bottom electrode.This technology generally is that doping, first is annealed, wet method is peeled off (wet strip) and second annealing.
correctly mix and filling groove after, need planarisation step to remove any horizontal composition of bottom electrode.After this, the modifier material must be introduced the part of lower electrode material, with the top near lower electrode material in conjunction with and/or reaction and form different materials.The formation of different materials also is ready to the top of match stick and comes to form suitable ohmic contact with phase-change material.Introduce modifier to improve the local electrical resistance of lower electrode material.Carry out modification by a part, can change the resistivity of partly locating in modification lower electrode material.Because material modified resistivity height, so to desired application, bottom electrode possibly can't provide ohmic contact enough suitable between bottom electrode and the certain volume storage material.In the case, can be at the following certain depth of the exposed surface of bottom electrode place with material modified introducing bottom electrode.For example, a kind of bottom electrode of polysilicon can have polysilicon at the exposed surface place, and has material modified at the following certain depth of exposed surface place.In addition, must add barrier material to prevent the cross pollution between chalcogenide material and the bottom electrode.
Description of drawings
In order to obtain the above-mentioned advantage of the present invention and other advantage, by with reference to the illustrated specific embodiment of accompanying drawing, with the present invention of detailed description brief description.Should be appreciated that these accompanying drawings have only described general embodiment of the present invention, these accompanying drawings do not need to draw in proportion, and therefore not will be understood that yet and limit the scope of the present invention.By using accompanying drawing, will describe and explain the present invention in detail.
Fig. 1 is the schematic diagram of memory cell arrays according to an embodiment of the invention;
Fig. 2 schematically illustrates the cross-sectional side view of the part of Semiconductor substrate according to one embodiment of present invention, and described substrate has first shallow trench isolation that forms with groove from (STI) structure, described ditch slot definition the z direction thickness of memory cell;
Fig. 3 is the top plan view of one embodiment of the invention;
Fig. 4 A is the cross-sectional elevational view of structure shown in Fig. 3;
Fig. 4 B is the cross-sectional elevational view of structure shown in Fig. 4 A after further handling;
Fig. 4 C is the cross-sectional elevational view of structure shown in Fig. 4 B after further handling;
Fig. 5 is the front oblique view of structure shown in Fig. 4 C after further handling, and it illustrates selected structure;
Fig. 6 shows after introducing diode stack (stack) part of dopant with the formation memory unit viewgraph of cross-section of the structure of Fig. 5 according to one embodiment of present invention;
Fig. 7 shows on memory unit the structure of introducing Fig. 6 after the mask material according to one embodiment of present invention;
Fig. 8 shows the schematic plan of the structure of Fig. 2 according to one embodiment of present invention, and wherein second etching groove has been removed a big chunk of first fleet plough groove isolation structure;
Fig. 9 shows patterning on the x of Semiconductor substrate structure direction thickness, and formation is orthogonal to after the second sti trench groove of first sti structure viewgraph of cross-section of the structure of Fig. 8;
Figure 10 shows after filling the second sti trench groove the same viewgraph of cross-section of the structure of Fig. 9 according to one embodiment of present invention;
Figure 11 is the top plan view of structure shown in Figure 10 after planarization, wherein illustrates of the present invention pair of groove aspect;
The front oblique view of the selected structure of the storage component part that Figure 12 is after planarization to be invented;
Figure 13 is another front oblique view of the selected structure of the storage component part invented afterwards at planarization and metal silication (salicidation);
Figure 14 shows the structure of after further handling with drag reduction (reducer) material that forms the band groove and dielectric material Fig. 5 or Figure 12, described groove and the connection of drag reduction material;
Figure 15 shows and introduce after the electrode material the same viewgraph of cross-section of the structure of Figure 14 on described structure according to one embodiment of present invention;
Figure 16 shows after filling groove and planarization, the same viewgraph of cross-section of the structure of Figure 15;
Figure 17 shows and introduce after the certain volume storage material and second conductor same viewgraph of cross-section of the structure of Figure 16 on described structure according to one embodiment of present invention;
Figure 18 according to one embodiment of present invention, show at second conductor and be coupled to introduce dielectric material on the 3rd conductor of first conductor after, the same viewgraph of cross-section of the structure of Figure 17; With
Figure 19 shows according to temperature and time, is provided with and resets the diagrammatic representation of certain volume phase-change memory material.
Embodiment
The present invention relates to a kind of storage component part, it comes the data memory storage with phase-change material.Described device uses the lower electrode material that is called " match stick ".Under this match stick, be provided with diode stack and activate bottom electrode.Forming first isolated groove, is second isolated groove subsequently.Second isolated groove is orthogonal to first isolated groove.Bottom electrode is formed on the diode stack of memory unit, and the certain volume phase-change memory material is positioned on the match stick.The metallic compound or the multi-crystal silicification compound of high resistivity can be used as bottom electrode.
Below describe and comprise term, for example upper and lower, first, second or the like, these terms only can not be understood as restriction as purpose of description.The embodiment of device of the present invention described herein or goods can make, use or transport with many positions and direction.Referring now to accompanying drawing, wherein similarly structure is provided with similar label.In order to clearly show that structure of the present invention, included here accompanying drawing is the graphic representation of integrated circuit structure.Therefore, it is different that for example actual look in microphoto of manufacturing structure may seem, but still comprised basic structure of the present invention.In addition, accompanying drawing only shows understanding the structure of necessity of the present invention.Do not comprise that accessory structure well known in the art is to keep the clear of accompanying drawing.
Fig. 1 shows the sketch of the memory array embodiment that is made up of a plurality of memory components of showing and form in the context of the invention.In this example, memory array circuit 5 comprises the array of memory component 30, memory component 30 and isolating device 25 series electrical interconnection on a chip part.In one embodiment, address wire 10 (for example row) and 20 (for example going) are connected to the outside addressing circuit well known to a person skilled in the art mode.The purpose that memory cell arrays combines with isolating device is, can read and write each discrete memories element and can not disturb adjacent or away from the array memory element in canned data.
Memory array such as memory array 5 can be formed in the part of substrate, also comprises whole substrates.Typical substrate comprises Semiconductor substrate, for example silicon substrate.Other substrate also is fit to, and described other substrate includes but not limited to, comprises ceramic material, organic material or the glass material substrate as a foundation structure part.Under the situation of silicon semiconductor substrate, memory array 5 can just be manufactured on the zone of substrate at wafer stage, change by single (singulation) subsequently and can make wafer become discrete tube core (die) or chip, partly or entirely have a memory array that forms thereon in tube core or the chip.Can form secondary addressing circuit well known to a person skilled in the art similar fashion such as sense amplifier, decoder or the like.
Fig. 2 to 18 illustrates the manufacturing of the representative store device element 15 of Fig. 1 according to different embodiment.Fig. 2 shows the part of substrate 100, and substrate 100 for example is a Semiconductor substrate.In one embodiment, the P type dopant such as boron is introduced into dark district 110.In an example, the suitable concn of P type dopant is at about every cubic centimetre 5 * 10 19-1 * 10 20Individual atom (atom/cm 3) magnitude, make the dark district 110 of substrate 100 be generally P ++In this example, on the dark district 110 of substrate 100 is the epitaxial part 120 of P type epitaxial silicon.In an example, the concentration of dopant of epitaxial part 120 is about 10 16-10 17Atom/cm 3Magnitude.The introducing in P type epitaxial part 120 and P++ moldeed depth district 110 and formation can be followed the technology of well known to a person skilled in the art.Fig. 2 also illustrates by the ion injection and in preferred depth and forms signal line material 140.Can use other embodiment known in the field, it does not use the structure such as P++ part and P epitaxial part.An example is exactly the p-n wafer.
Fig. 2 also shows first shallow trench isolation of formation in the epitaxial part 120 of substrate 100 from (STI) structure 130.Can under such as the help of the hard mask 122 of silicon nitride material, form first sti structure 130.Fig. 3 is with the top plan view of second mask 124 at first sti structure 130 and hard mask 122 substrate 100 after the patterning on both.At first cover deposition second mask 124, the patterning then.During second etching that is orthogonal to first sti structure 130, adopt second mask 124.In two step etchings, can make second mask 124 be orthogonal to first sti structure 130 with bar patterning second mask 124 of a characteristic width (1F-width).
Fig. 4 A is the cross-sectional elevational view that structure shown in Fig. 3 is got along hatching line A-A '.The zone of second shown mask 124 protections will the becoming diode stack of a plurality of isolation.Fig. 4 B is the cross-sectional elevational view that structure is got along hatching line B-B ' shown in Fig. 3 during the etching of removing hard mask 122.Wherein hard mask 122 is the nitride such as silicon nitride, and etching may be removed the part of first sti structure 130, and described part generally is an oxide.This etching condition is known in the field.
Fig. 4 C is the cross-sectional elevational view of structure shown in Fig. 4 B after further handling.After the etching of removing hard mask 122, carry out silicon etching with second mask, 124 same patternings.The method of etching is the oxide that optionally stays first sti structure 130.After patterning and silicon etching, can introduce N type dopant to form pocket (pocket) 200 in the bottom of each groove, its concentration of dopant is about 10 18-10 22Atom/cm 3Magnitude.
After silicon etching, oxide is inserted in the groove to form second shallow trench (SST) structure 132 as shown in Figure 5, although in this embodiment, this structure is the quadrangle groove that fills up substantially.Fig. 5 is the front oblique view of the selected structure of the storage component part invented.In this embodiment, before forming SST structure 132, formed first sti structure 130.First sti structure 130 is continuous substantially at the upper surface place.132 on SST structure is discontinuous substantially owing to the silicon etching that stays first sti structure, 130 oxide materials.Like this, SST structure 132 comprises the interruption upper surface fleet plough groove isolation structure that is arranged in second groove, and first sti structure 130 comprises the continuous upper surface fleet plough groove isolation structure that is arranged in first groove.
Fig. 5 also illustrates the formation as the isolating device 25 of a diode stack part.Isolating device 25 comprises that N type silicon part 150 can have about 10 by N type silicon part 150 and P type silicon part 160 formed PN diodes 17-10 22Atom/cm 3The concentration of dopant of magnitude, P type silicon part 160 can have about 10 19-10 21Atom/cm 3The concentration of dopant of magnitude.Though the PN diode shown makes isolating device 25, be appreciated that other similar isolation structure also is suitable.This isolating device comprises the MOS device, but is not limited to this.Described memory unit 134, it comprises epitaxial part 120, signal line material 140, N silicon part 150 and the P+ silicon part 160 of P type epitaxial silicon.
The memory cell feature may be defined as the minimum geometry (geometry) of determining memory cell.For example, the first feature F 1A limit of definable memory unit 134.The second feature F 2The first limit geometry of definable first sti structure 130.The 3rd feature F 3The second limit geometry of definable memory unit 134.At last, the 4th feature F 4The limit geometry of definable SST structure 132.Wherein first and second features are equal substantially, they can be appointed as 2F.In any case first to the 4th feature can be appointed as four feature square (4F in being defined in rectangular configuration the time 2) 136.Can see under selected structure 4F 2136 projection illustrates the unit cell of the memory isolation of being invented.In the present invention, obtained two groove isolation constructions, it is used on all directions coming with the distance of 1F at least the diode stack of sequestering memory cellular construction 134.In this embodiment, also do not form drag reduction (reducer) material 170 (see figure 6)s, and planarization produced a surface, it exposes first sti structure 130, SST structure 132 and P type silicon part 160.
Because memory unit 134 is isolated by two trench structures, so reduced the possibility of crosstalking between the neighbor memory cell structure.In addition, gash depth can from about 3,000 on the magnitude of about 7,000 , and the total depth of SST structure 132 is within from about 500 to the scope of about 3,500 .Gash depth is subjected to the restriction of etch period constraint.In addition, along with geometry reduces constantly, for example 0.35 micron, 0.25 micron, 0.18 micron, 0.13 micron, 0.11 micron or the like, 4F 2Structure scale easily and be can with the integrated simplification part of design specification.In addition, relative prior art has improved the degree of the vertical β (beta) in the diode stack.
Fig. 6 shows and carry out the further manufacturing operation structure of Fig. 4 C afterwards in memory cell area 135A and 135B.Cover substrate 100 epitaxial part 120 be first conductor or signal line material 140.In an example, first conductor or signal line material 140 are the N type doped polycrystalline silicon such as N+ silicon, and described N type doped polycrystalline silicon is by introducing concentration about 10 18-10 22Atom/cm 3The for example three valent phosphors of magnitude or arsenic and form.In this example, first conductor or signal line material 140 be as address wire, such as the line of the line 20 of Fig. 1.What cover first conductor or signal line material 140 is isolating device such as the isolating device 25 of Fig. 1.In an example, isolating device 25 is that N type silicon part 150 can have about 10 by N type silicon part 150 and P type silicon part 160 formed PN diodes 17-10 22Atom/cm 3The concentration of dopant of magnitude, P type silicon part 160 can have about 10 19-10 21Atom/cm 3The concentration of dopant of magnitude.Though show PN diode 25, be appreciated that other similar isolation structure also is suitable.This isolating device comprises the MOS device, but is not limited to this.
Again with reference to figure 6, what cover isolating device 25 in memory cell area 135A and 135B is drag reduction material 170, drag reduction material 170 in this example by such as cobalt disilicide (CoSi 2) refractory metal silicide form.Drag reduction material 170 can form at any one place in the several sections of the technology of being invented.When drag reduction material 170 was metal silicide, it can form autoregistration (self-aligned) silicide or metal silicide in position.Drag reduction material 170 can form in this part of technology or can after formation.On the one hand, drag reduction material 170 is as the low electrical resistant material of making on chip in the peripheral circuit, and described peripheral circuit for example is the addressing circuit of circuit structure.Like this, aspect the described memory component of formation, drag reduction material 170 is also unnecessary.Yet, because its low resistance characteristic uses it as the part of memory unit between isolating device 25 and memory component 30 in the present embodiment.
Fig. 7 shows the structure of Fig. 6 after introducing mask material 180.In one embodiment, are dielectric materials as the suitable material of mask material 180, for example with the silicon nitride (Si of stoichiometric proportion and other solid solution ratio 3N 4), although also can use other material, for example with the silica (Si of stoichiometric proportion and other solid solution ratio xO z) or silicon oxynitride (Si xO zN y).
Mask material 180 is used for patterning, with protected storage unit area 135A in follow-up etching operation and protect a plurality of parts of first sti structure 130.In this embodiment, mask material 180 can be an etching stop layer patterning and that not can be used as two step etching technics.For example, in the place that forms contact channels (corridor), two step etching technics allow quick oxide etching to stop on the mask layer 180, then are nitride etches at a slow speed, this at a slow speed nitride etch will on silicon, stop, for example not having the end of connecing contact (unlanded contact).
In another embodiment, can before forming SST structure 132, form isolating device 25.In this embodiment, mask material 180 comprises the pattern mask that is similar to second mask 124.Fig. 8 is the top plan view at xz visual angle of the substrate 100 of this embodiment of diagram.To this embodiment preferably, carrying out planarization is removed fully up to hard mask 122.Therefore, can simplify etch process flow because do not needed the etching nitride.Finish the formation of isolating device 25 like this, make and in Fig. 8, expose P type silicon part 160.Preferably, lithographic method carries out etching with having so optionally, i.e. the relative silicon of P type silicon part 160 or electric conducting material 150 is not more prone to the material of first sti structure 130.This lithographic method is being known in the art and can selecting based on the doping that forms isolating device 25.By the patterning of hard mask 180, groove (190, will form) will hold SST structure (also will form).
Fig. 9 shows on the x of memory cell material direction thickness patterning to form the structure of the Fig. 8 that sees from the xy visual angle after the groove 190.Fig. 9 shows from two memory cell 145A of the memory cell area 135A patterning shown in Fig. 2 and 145B.Can use traditional technology to finish patterning, at technology etching refractory metal silicide described in this example and silicon materials and non-etch mask material 180.In one embodiment, the definition of x direction thickness relates to the etching of the electric conducting material 150 (being N type silicon in this embodiment) to the memory lines stack, to determine memory cell 145A and the 145B of memory cell area 135A.Under the situation of etching, etching is proceeded through the memory lines stack in this example, and up to the part of conductor or holding wire, conductor or holding wire are exactly electric conducting material 150 in the case.Can utilize the timing etching to stop etching at this some place.
Figure 10 is illustrated in the structure of the Fig. 8 that sees from the xy visual angle after the filling groove 190.After patterning and etching to groove 190, can introduce N type dopant in the bottom of each groove 190 and form pocket 200, its concentration of dopant is about 10 18-10 22Atom/cm 3Magnitude between memory cell 145A and 145B, to form N +The zone.In some sense, pocket 200 is used for keeping the continuity of line.
As shown in figure 10, on substrate 100, form SST structure 132 to fill up groove 190 substantially.Though drag reduction material 170 is arranged shown in Figure 10, if any, it also can form as will providing here afterwards.SST structure 132 is formed on the direction that is orthogonal to first sti structure 130 in second isolated groove 190.But planarization SST structure 132 is to expose diode stack.After planarization, first sti structure 130 and SST structure 132 are all exposed.
Perhaps in processing, before forming first sti structure 130 and/or SST structure 132, can in each groove, form hot dielectric film.Described hot dielectric film is with helping form better groove.
Figure 11 illustrates the top plan view of resultant structure after planarization.Fill to form SST structure 132, so first sti structure 130 is illustrated as being cut by etching groove 190 (not shown) and with it.In other words, first sti structure 130 has discontinuous upper surface, and SST structure 132 has continuous substantially upper surface.Line C-C ' shown in Figure 11 has described the viewgraph of cross-section of the structure among Figure 10.
Also show memory unit 134 among Figure 11.Memory unit 134 may have the exposed surface such as drag reduction material 170, if perhaps drag reduction material 170 also forms, then is such as P type silicon part 160 etc.Figure 11 illustrates the main isolation of memory unit 134, and wherein it is centered on by two first sti structures 130 and two SST structures 132.Any of four features is all spaced apart with adjacent memory unit 134 with memory unit 134.In other words, the interval isolation minimum to memory unit 134 is exactly as 4F 2The minimum dimension of structure 136.Wherein there is 4F in a kind of structure that Figure 11 also illustrates the present invention and invented in dotted line 136 2 Structure 136 unit cells with the define storage device.
Figure 12 is the front oblique view of the selected structure of the storage component part invented according to this embodiment.In this embodiment, before forming SST structure 132, form first sti structure 130, and the etching of groove 190 has been obtained the etch rate all similar substantially with silicon to the oxide of first sti structure 130.In addition, not shown mask material 180 is to expose SST structure 132.Expose memory unit 134 by excision SST structure 132.Can see under selected structure 4F 2136 projection illustrates the unit cell of the memory isolation of being invented.In the present invention, obtained two groove isolation constructions, it is used on all directions coming with the distance of 1F at least the diode stack of sequestering memory cellular construction 134.In this embodiment, also do not form drag reduction material 170, and planarization produced a surface, it exposes first sti structure 130, SST structure 132 and P type silicon part 160.
Figure 13 is the front oblique view of the selected structure shown in Figure 12 after the metal silicide that forms drag reduction material 170.May after the storage component part planarization, form the metal silicide of drag reduction material 170.
Figure 14 shows in 132 planarizations of SST structure and the structure of Fig. 5 or Figure 12 after optionally the metal silicide of drag reduction material 170 forms.The degree of depth of first sti structure 130 and SST structure 132 can be according to preferred application and is different.In one embodiment, the degree of depth of first sti structure 130 can arrive in the scope of about 7,000 from about 3,000 .The total depth of SST structure 132 can be within from about 500 to the scope of about 3,500 .In one embodiment, from the bottom of drag reduction material 170, about 5,300 of the total depth of first sti structure, and about 2,500 of the total depth of SST structure 132.
One aspect of the present invention relates to the relative depth of fleet plough groove isolation structure.Memory unit 134 comprises the P+ silicon structure 160 that is positioned on the N silicon structure 150.P+ silicon structure 160 has top and bottom.N silicon structure 150 also has top and bottom.Illustrated in Figure 14, SST structure 132 also has top and bottom; And the bottom of SST structure 132 is under P+ silicon structure 160, and the top of SST structure 132 is on the bottom of P+ silicon structure 160.
Form dielectric material 210, and the formation of finishing the groove 220 that passes dielectric material 210 is to expose drag reduction material 170.Use etching patternization to form groove 220, described etching patternization is with such etching agent, and promptly etching dielectric material 210 and drag reduction material 170 had selectivity makes drag reduction material 170 can be used as etching stop layer.
Figure 15 illustrates the invention process that forms bottom electrode by using the metal compound film of being invented in phase-change memory device.The memory lines stack can refer to active area.Figure 15 is illustrated in suitable shape and introduces lower electrode material 230 structure of Figure 14 afterwards, and lower electrode material 230 can refer to metal compound film, although it can be conduction or semi-conductive polycrystalline silicon material or metallic compound material.In an example, metal compound film 230 is metal nitrides, TaN for example, and it depends on that desired resistivity can provide with stoichiometric proportion and other metal compound film solid solution ratio.
It is such meaning that suitable shape is introduced, and promptly metal compound film 230 is introduced along the sidewall and the bottom of groove 220, makes metal compound film 230 and drag reduction material 170 contact.The suitable shape of metal compound film 230 is introduced and can be followed traditional introducing technology known in those skilled in the art, comprises the chemical vapor deposition (CVD) technology, and wherein metal compound film 230 is polysilicon, metal nitride and/or silicide.
Groove 220 can refer to the illustrated groove as Figure 15, and this groove forms to expose at least a portion of memory cell stack in first dielectric 210.Though described groove dactylotome groove 220 can be selected the type of groove from ringwise groove substantially, rectangle (square) groove and groove.
Metal compound film 230 comprises at least a in a kind of metal and nitrogen or the silicon.Can and finish the given of metallic compound be mixed by at least a composition in chemical vapor deposition (CVD) nitrogen or the silicon together with metal.The material of metal compound film 230 is the metallic compound of high resistivity preferably, for example metal nitride, refractory metal nitride, metal silicide, refractory metal silicide, metal silicide and refractory metal silicide.Preferably, the composition of metal compound film 230 is by controlling to the feed rate of CVD instrument.Depend on specific embodiment, can use other CVD technology, for example plasma-enhanced CVD (PECVD).
In another embodiment, form metal compound film 230, select a kind of target to make final metal compound film have preferred composition by physical vapor deposition (PVD).Perhaps, a plurality of target capable of being combined is to obtain preferred metal compound film composition.In PVD or CVD, be defined as the coverage of wall deposit thickness and the ratio of top deposit thickness, from about 0.25 in about 1 scope, preferably be about 0.5.In the present invention, preferably form bottom electrode with CVD.
When being metal compound film 230 selection metal nitrides, metal can be selected from titanium, zirconium or the like.Also can from tantalum, niobium or the like, select.Also can from tungsten, molybdenum or the like, select.Also can from nickel, cobalt or the like, select.Metal nitride preferably structural formula is M xN yRefractory metal nitride.The ratio of M: N from about 0.5: 1 in about 5: 1 scope, preferably from about 0.6: 1 to about 2: 1, most preferably be about 1: 1.For example, one embodiment of the present of invention are Ta xN yThe ratio of compound preferably from about 0.6: 1 to about 2: 1, most preferably was about 1: 1 from about 0.5: 1 to about 5: 1.The example of another embodiment is W xN yThe ratio of compound preferably from about 0.6: 1 to about 2: 1, most preferably was about 1: 1 from about 0.5: 1 to about 5: 1.
In another embodiment of the present invention, metal compound film 230 can be a metal nitrogen silicon compound.Metal can be selected from titanium, zirconium or the like.Also can from tantalum, niobium or the like, select.Also can from tungsten, molybdenum or the like, select.Also can from nickel, cobalt or the like, select.Metal nitrogen silicon compound can have structural formula M xSi zN y, wherein the ratio of M: Si: N from about 1: 0.5: 0.5 in about 5: 1: 1 scope.Preferably, ratio from about 1: 1: 0.5 in about 1: 0.5: 1 scope, most preferably be about 1: 1: 1.In one embodiment, lower electrode material compound Ti xSi zN yRatio from about 1: 0.5: 0.5 to about 5: 1: 1, preferably from about 1: 1: 0.5 to about 1: 0.5: 1, most preferably be about 1: 1: 1.
In another embodiment, bottom electrode can be a metal silicide.Metal can be selected from titanium, zirconium or the like.Also can from tantalum, niobium or the like, select.Also can from tungsten, molybdenum or the like, select.Also can from nickel, cobalt or the like, select.Metal silicide can have structural formula M xSi z, wherein the ratio of M: Si from about 0.5: 1 in about 5: 1 scope.In one embodiment, lower electrode material compound Ti xSi yThe ratio of compound preferably from about 0.6: 1 to about 2: 1, most preferably was about 1: 1 from about 0.5: 1 to about 5: 1.In another embodiment, lower electrode material compound W xSi yThe ratio of compound preferably from about 0.6: 1 to about 2: 1, most preferably was about 1: 1 from about 0.5: 1 to about 5: 1.
Figure 16 illustrates the further technology of structure shown in Figure 15.After forming metal compound film 230, with second dielectric, 250 filling grooves 220.Chemical vapor deposition method that can be by silicon-containing material or the like forms second dielectric 250, and described silicon-containing material can be selected from the Si oxide such as tetraethoxysilane (TEOS).After forming second dielectric 250, remove all material that is positioned at becoming on the position of groove top 240 as shown in figure 16.Can finish the removal of material by such technology, for example chemico-mechanical polishing (CMP), mechanical polishing or the like.Can finish the removal of material by such technology, for example isotropic etch back (etchback), anisotropy are eat-back (etchback) or the like.
Figure 17 shows and is introducing certain volume storage material 290 (being expressed as memory component 30 among Fig. 1) structure of Figure 16 afterwards.In an example, storage material 290 is phase-change materials.At one more specifically in the example, storage material 290 comprises the chalcogen compound.The example of phase-change memory material 290 comprises the tellurium-germanium-antimony (Te with stoichiometric proportion and other solid solution ratio xGe ySb z) constituents, but be not limited to this.In a example according to current techniques, certain volume storage material 290 be introduced into and the thickness of patterning from about 300 in the scope of about 6,000 .
What cover certain volume storage material 290 in the structure of Figure 17 is the barrier material of being made up of for example titanium (Ti) and titanium nitride (TiN) respectively 300 and 310.On the one hand, barrier material is used for suppressing certain volume storage material 290 and covers second conductor of certain volume storage material 290 or the diffusion between the signal line material (for example second electrode 10).Covering barrier layer material 300 and 310 be second conductor or signal line material 315.In this example, second conductor or signal line material 315 are as address wire, i.e. alignment (for example alignment among Fig. 1 10).In one embodiment, second conductor or signal line material 315 are patterned to are orthogonal to first conductor or signal line material 140 (alignment is orthogonal to line) substantially.Second conductor or signal line material 315 for example are aluminum, for example aluminium alloy.The introducing and the patterning method of the barrier material and second conductor or signal line material 315 comprise technology known in those skilled in the art.
Figure 18 shows in second conductor or the structure of Figure 17 after the introducing dielectric material 330 above the signal line material 315.Dielectric material 330 for example is SiO 2Or other suitable material, it centers on second conductor or signal line material 315 and storage material 290 and isolates this structure with electricity.After introducing, planarization dielectric material 330, and form through hole (via) in a part of structure of drag reduction material 170 passing dielectric material 330, dielectric material 210 and mask material 180 such as contact channels.Through hole is filled such as the electric conducting material 340 of tungsten (W) and the barrier material 350 that makes up such as titanium (Ti) and titanium nitride (TiN).The technology of introducing dielectric material 330, formation and filled conductive through hole and planarization is known to those skilled in the art.
Structure shown in Figure 18 also shows extra conductor or signal line material 320, and it is introduced into patterning and is formed at first conductor or signal line material 140 (for example line) on the substrate 100 with mirror image.Mirror image conductor signal lines material 320 mirror images go out first conductor or signal line material 140, and are coupled to first conductor or signal line material 140 by conductive through hole.By the doped semiconductor of mirror image such as N type silicon, mirror image conductor signal lines material 320 is used for reducing first conductor in memory array or the resistance of signal line material 140, described memory array memory array 5 as illustrated in figure 1 on the one hand.The suitable material of mirror image conductor signal lines material 320 comprises aluminum, for example aluminum or aluminum alloy.
In above description to the formation memory component, such as the memory component among Fig. 1 15, metal compound film 230 is electrodes, and is described as be between storage material and conductor or the holding wire (for example line and alignment), and described electrode has the electrical characteristics of enhancing.In described embodiment, select the given metal compound film 230 of resistivity to make as to be set forth of electrode here.Use the method, the supply voltage from second conductor or signal line material 320 or first conductor or signal line material 140 to storage material 290 more multiaction can minimize the energy dissipation that causes phase transformation in certain volume storage material 290.Here gone through a memory component of memory array 5.Same methods is made other memory component of memory array 5.Should understand and can make the many of memory array 5 even all memory components simultaneously, and other integrated circuit.
Figure 19 has showed the diagrammatic representation that is provided with and resets the certain volume phase-change memory material.With reference to figure 1, in an example, setting and resetting memory element 15 (by alignment 10a and line 20a addressing) relate to alignment 10a supply voltage, electric current is introduced certain volume storage material 30 or storage material as shown in figure 12 290 as shown in Figure 1.Electric current makes the temperature at certain volume storage material 30 places raise.With reference to Figure 19,, the certain volume storage material is heated to decrystallized temperature T for making the certain volume storage material decrystallized MOn temperature.Be higher than T in case reach MTemperature, just fast cooling or (quench) (by removing electric current) certain volume storage material that quenches.With speed t 1Finish quenching, described speed makes certain volume storage material 30 keep its noncrystalline state faster than certain volume storage material 30 crystallizable speed.In order to make 30 crystallizations of certain volume storage material, by electric current temperature is brought up to the crystallization temperature of material, and keep the sufficiently long time of this temperature so that the material crystallization.After this, quenching certain volume storage material (by removing electric current).
Resetting and being provided with in each of these examples of certain volume storage material 30, the importance of concentrating temperature transfer (delivery) at certain volume storage material 30 places has been described.A kind of method of finishing it is to revise the part of aforesaid electrode.The illustration of Figure 19 shows memory cell 15, and it has band and revises the electrode of part 35 (being illustrated as resistor) to concentrate heat (electric current) at certain volume storage material 30 places.
In the example in front, certain volume storage material 30 is heated to high temperature so that material is decrystallized and replacement memory component (for example program 0).The certain volume storage material is heated to lower crystallization temperature to be made the material crystallization and memory component (for example program 1) is set.It will be appreciated that it is a kind of agreement that replacement and setting and amorphous and crystalline material are associated respectively, and can adopt opposite agreement at least.From then on example it is also to be understood that, need not to be provided with or replacement certain volume storage material 30 by the electric current and the duration part that change in the certain volume storage material.
Another advantage is arranged when using the metallic compound electrode.Because between bottom electrode and certain volume storage material, there is the interface of metal-metal, so can exist than doped polycrystalline silicon-lower interface resistance in chalcogenide interface.
Owing to form the chemical constituent of the metal compound film of being invented 230 of bottom electrode, simplified technological process.For example, in technological process, do not need to inject polysilicon and activate it.The doped polycrystalline silicon bottom electrode requires such processing, for example doping process, activate and be doped electrode so that the barrier layer between the annealing process of its conduction, bottom electrode and upper surface and handling from composition, the upper surface modification can be heated better at upper surface.
On the contrary, the bottom electrode of being invented is made up of metal compound film 230, and by its filled dielectric material.Therefore, but carry out CMP and deposit memory material 290 materials.
The easy understanding of those skilled in the art can be to making other various changes for explaining that essence of the present invention is described with illustrated a plurality of parts and the details in method stage, material and layout, and the principle and scope of the present invention that do not depart from the claim to be explained.

Claims (27)

1. storage component part comprises:
Memory unit;
First isolated groove is in abutting connection with described memory unit; With
Second isolated groove in abutting connection with described memory unit, and is orthogonal to described first isolated groove,
First limit of wherein said memory unit has defined first feature of unit cell,
Second limit of wherein said memory unit has defined second feature of described unit cell,
The limit of wherein said first isolated groove has defined the 3rd feature of described unit cell,
The limit of wherein said second isolated groove has defined the 4th feature of described unit cell.
2. storage component part as claimed in claim 1, wherein said memory unit, described first isolated groove and described second isolated groove have defined four characteristic size square (4F 2).
3. storage component part as claimed in claim 1, wherein said storage component part is arranged in substrate, and wherein said first isolated groove is positioned at than the darker position of described second isolated groove.
4. storage component part as claimed in claim 1, wherein said storage component part is arranged in substrate, and wherein said first isolated groove comprises discontinuous upper surface, and described second isolated groove comprises continuous substantially upper surface.
5. storage component part as claimed in claim 1, wherein said memory unit is separated out, and isolated with a feature (1F).
6. storage component part as claimed in claim 1, wherein said first isolated groove comprises single fleet plough groove isolation structure.
7. storage component part as claimed in claim 1, wherein said memory unit comprises:
Be positioned at the P+ silicon structure on the N silicon structure, wherein said P+ silicon structure has top and bottom, and wherein said N silicon structure has top and bottom; And wherein said second isolated groove has top and bottom; And
The bottom of wherein said second isolated groove is lower than described P+ silicon structure.
8. storage component part as claimed in claim 1, wherein said memory unit comprises: be positioned at the P+ silicon structure on the N silicon structure;
Wherein said P+ silicon structure has top and bottom;
Wherein said N silicon structure has top and bottom; And
Wherein said second isolated groove has top and bottom;
The bottom of wherein said second isolated groove is lower than described P+ silicon structure, and
The top of wherein said second isolated groove is on described P+ silicon structure bottom.
9. storage component part as claimed in claim 1, wherein said memory unit comprises:
The diode stack structure comprises:
The capable selection of N+ silicon;
Be positioned at the N silicon that described N+ silicon is capable to be selected;
Be positioned at the P+ silicon layer on the described N silicon layer; With
Silicide layer.
10. technology that forms storage component part comprises:
In substrate, form first groove;
Form second groove in described substrate, wherein said second groove intersects with described first groove; And
Form the memory unit diode stack adjacent with described second groove with described first groove.
11. technology as claimed in claim 10, wherein said second groove is orthogonal to described first groove.
12. technology as claimed in claim 10, wherein said second groove is more shallow than described first groove.
13. technology as claimed in claim 10 wherein forms described first groove and comprises etching technics, described etching technics obtains at about 3,500 to the interior etching depth of about 7,000 scopes.
14. technology as claimed in claim 10 wherein forms described second groove and comprises etching technics, described etching technics obtains at about 500 to the interior etching depth of about 3,500 scopes.
15. technology as claimed in claim 10 after forming described first groove, also comprises:
Fill described first groove with isolation dielectric; And
The described substrate of planarization.
16. technology as claimed in claim 10 after forming described first groove, also comprises:
In described first groove, form hot dielectric film;
Fill described first groove with isolation dielectric; And
The described substrate of planarization.
17. technology as claimed in claim 10 after forming described second groove, also comprises:
Fill described second groove with isolation dielectric; And
The described substrate of planarization.
18. technology as claimed in claim 10 after forming described second groove, also comprises:
In described second groove, form hot dielectric film;
Fill described second groove with isolation dielectric; And
The described substrate of planarization.
19. technology as claimed in claim 10 also comprises:
Formation is adjacent to the diode stack of described first groove and described second groove.
20. technology as claimed in claim 10 also comprises:
Formation is adjacent to the diode stack of described first groove and described second groove;
On described semiconductor diode, form first dielectric film;
In described first dielectric film, form groove to expose described diode stack;
In described groove, form the bottom electrode film; And
On described bottom electrode film, introduce the certain volume phase-change memory material.
21. technology as claimed in claim 10 also comprises:
Formation is adjacent to the diode stack of described first groove and described second groove;
Fill described first groove and described second groove; And
On described diode stack, form the self-aligned silicide layer.
22. a phase-change memory device comprises:
First groove is positioned among the substrate;
Second groove is positioned among the described substrate, and wherein said second groove is orthogonal to described first groove;
Diode stack is adjacent to described first groove and described second groove and arranges;
First dielectric is positioned on the described diode stack;
Groove is arranged in described first dielectric and exposes described diode stack;
Bottom electrode is arranged in described first dielectric described groove;
The certain volume phase-change material is positioned on the described bottom electrode; With
At least one address wire is coupled to described phase-change material.
23. phase-change memory device as claimed in claim 22 also comprises:
Be interrupted the upper surface fleet plough groove isolation structure, be arranged in described second groove; And
Substantially continuous upper surface fleet plough groove isolation structure is arranged in described first groove.
24. phase-change memory device as claimed in claim 23, wherein said bottom electrode comprises:
Metal compound layer, suitable morpheme is in described groove and on the described diode stack, and wherein said metallic compound is selected from following material: polysilicon, metal nitride, refractory metal nitride, metal silicide, refractory metal silicide, metal silicide and refractory metal silicide.
25. a device comprises:
Have the private memory chip of memory array, described memory array comprises: first groove that is arranged in substrate; Be arranged in second groove of described substrate, wherein said second groove is orthogonal to described first groove; Diode stack is adjacent to described first groove and described second channel layout; First dielectric is positioned on the described diode stack; Groove is arranged in described first dielectric and exposes described diode stack; Bottom electrode is arranged in described first dielectric described groove; The certain volume phase-change memory material is positioned on the described bottom electrode; And the addressing circuit that is coupled to described memory array.
26. device as claimed in claim 25, wherein said memory array also comprises: be interrupted the upper surface fleet plough groove isolation structure, be arranged in described second groove; With substantially continuous upper surface fleet plough groove isolation structure, be arranged in described first groove.
27. device as claimed in claim 26, wherein said bottom electrode comprises metal compound layer, the suitable shape of described metal compound layer ground is arranged on described groove and the described diode stack, and wherein said metallic compound is selected from following material: polysilicon, metal nitride, refractory metal nitride, metal silicide, refractory metal silicide, metal silicide and refractory metal silicide.
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