CN112490250A - Manufacturing method of semiconductor device and semiconductor device - Google Patents
Manufacturing method of semiconductor device and semiconductor device Download PDFInfo
- Publication number
- CN112490250A CN112490250A CN202011353916.7A CN202011353916A CN112490250A CN 112490250 A CN112490250 A CN 112490250A CN 202011353916 A CN202011353916 A CN 202011353916A CN 112490250 A CN112490250 A CN 112490250A
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor device
- substrate
- channel hole
- amorphous carbon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention provides a manufacturing method of a semiconductor device and the semiconductor device, the method comprises the following steps: providing a substrate, wherein a stack layer is formed on the substrate; forming a dummy channel hole through the stacked layers in a direction perpendicular to the substrate; forming a first barrier layer on the inner wall of the virtual channel hole; amorphous carbon is filled in the virtual channel hole formed with the first barrier layer, so that reliable supporting capacity can be provided for the stacked layer, collapse or depression of the stacked layer is avoided, and the yield of finished products of semiconductor devices is improved.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device and the semiconductor device.
[ background of the invention ]
Three-dimensional memory (3D NAND) is an emerging type of memory that addresses the limitations imposed by 2D or planar NAND flash memories by stacking memory particles together. Unlike placing memory cells on a single side, 3D NAND technology vertically stacks multiple layers of memory cells. Based on the technology, the storage device with the storage capacity which is several times higher than that of the similar NAND technology can be manufactured. The technology can support the accommodation of higher storage capacity in a smaller space, thereby bringing about great cost saving, energy consumption reduction and great performance improvement.
In the 3D NAND memory, a mode of vertically stacking a plurality of layers of grids is adopted, the central area of a stacking layer is a core area, the edge area of the stacking layer is a step area, the core area is used for forming storage units, a conducting layer in the stacking layer is used as a grid line of each layer of storage unit, and the grid line is led out through a contact on the step, so that the stacking type 3D NAND memory device is realized. Currently, a plurality of dummy channel structures for supporting are formed in the stacked layer to improve the supporting capability of the stacked layer and avoid collapse or recess, such as recess at the interface between the core region and the step region. The dummy trench structure includes a dummy trench hole and a filler in the dummy trench hole, and in order to reduce the cost, the dummy trench hole is usually filled with silicon dioxide, but the problem of recess at the junction cannot be solved well due to poor supporting performance of the silicon dioxide.
[ summary of the invention ]
The invention aims to provide a manufacturing method of a semiconductor device and the semiconductor device, which can provide a virtual channel structure with better supporting performance so as to avoid the problem of sinking at the junction of a core region and a step region.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a stack layer is formed on the substrate;
forming a dummy channel hole through the stacked layers in a direction perpendicular to the substrate;
forming a first barrier layer on the inner wall of the virtual channel hole;
and filling amorphous carbon in the virtual channel hole with the first barrier layer.
Wherein the amorphous carbon comprises SP3Hybrid bond and SP2Hybrid bond, the SP3The content of hybrid bonds is greater than the SP2Content of hybrid bonds.
After the dummy trench hole formed with the first barrier layer is filled with amorphous carbon, the method for manufacturing a semiconductor device further includes:
performing primary planarization treatment on the virtual channel hole filled with the amorphous carbon;
and cleaning the virtual channel hole after the planarization treatment.
The manufacturing method of the semiconductor device further comprises the following steps:
forming a gate line slit penetrating the stacked layers in a direction perpendicular to the substrate;
forming a common source structure through the gate line slit;
and carrying out primary planarization treatment on the common source structure.
The manufacturing method of the semiconductor device further comprises the following steps:
forming a storage channel hole penetrating the stacked layers in a direction perpendicular to the substrate;
forming a storage function layer on an inner wall of the storage channel hole;
forming a channel layer on the memory function layer.
In order to solve the above problem, the present invention also provides a semiconductor device comprising:
a substrate having a stack layer formed thereon;
a dummy channel structure that penetrates the stacked layers in a direction perpendicular to the substrate;
the dummy channel structure comprises a dummy channel hole, amorphous carbon filled in the dummy channel hole, and a first blocking layer located between the amorphous carbon and the dummy channel hole and surrounding the amorphous carbon.
Wherein the amorphous carbon comprises SP3Hybrid bond andSP2hybrid bond, the SP3The content of hybrid bonds is greater than the SP2Content of hybrid bonds.
The first barrier layer is made of a material including silicon oxide.
Wherein the semiconductor device further comprises:
and the storage channel structure penetrates through the stacking layer in the direction vertical to the substrate, and comprises a storage channel hole, and a storage functional layer and a channel layer which are sequentially stacked on the inner wall of the storage channel hole.
The storage function layer comprises a second blocking layer, a charge storage layer and a tunneling layer which are sequentially stacked on the inner wall of the storage channel hole.
The invention has the beneficial effects that: according to the manufacturing method of the semiconductor device and the semiconductor device, the virtual channel hole penetrating through the stacked layer is formed in the direction perpendicular to the substrate, the amorphous carbon and the first barrier layer which is located between the amorphous carbon and the virtual channel hole and surrounds the amorphous carbon are filled in the virtual channel hole, so that the high hardness, the strong insulating property, the better thermal stability and the better chemical stability of the amorphous carbon can be utilized, the reliable supporting capability is provided for the stacked layer, collapse or depression is avoided, and the yield of finished products of the semiconductor device is improved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic cross-sectional structure of a conventional semiconductor device;
fig. 2 is a schematic cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present application;
fig. 3 is a schematic top view of a portion of the core region and the stepped region of the semiconductor device of fig. 2;
fig. 4 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram comparing a partial process flow of a semiconductor device provided in an embodiment of the present application with a partial process flow of a conventional semiconductor device.
[ detailed description ] embodiments
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be noted that the following examples are only illustrative of the present invention, and do not limit the scope of the present invention. Similarly, the following examples are only some but not all examples of the present invention, and all other examples obtained by those skilled in the art without any inventive work are within the scope of the present invention.
It should be readily understood that directional terms used herein, such as [ upper ], [ lower ], [ front ], [ back ], [ left ], [ right ], [ inner ], [ outer ], etc., are merely directions that refer to the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals. The terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.
It should be readily understood that references to the meaning of "on … …", "above … …" and "above … …" in the present invention are to be interpreted in the broadest manner such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween.
Referring to fig. 1, fig. 1 is a schematic cross-sectional structure diagram of a conventional semiconductor device. Specifically, the semiconductor device 100 includes a substrate 101 and a stack layer 102 stacked on each other, the stack layer 102 is formed by alternately stacking a gate insulating layer 102A and a gate electrode layer 102B, and includes a core regionM1 and a step region M2, and a memory channel structure 103 is provided in the core region M1. In general, in order to avoid local collapse or recess of the stacked layer 102 when the sacrificial layer is replaced with the gate layer 102B, a dummy channel structure 104 penetrating the stacked layer 102 and used for supporting is further provided in a direction perpendicular to the substrate 101. The dummy trench structure 104 includes a dummy trench hole 1041, and a silicon oxide (SiO) filled in the dummy trench hole 10412)1042。
Although the dummy channel structure 104 can provide a certain supporting capability, the hardness of the silicon oxide 1042 is not high, so the supporting capability provided by the dummy channel structure 104 is very limited, the deposition thickness of these film layers needs to be set to be relatively thick when forming the protection layer (cap oxide layer) and the common source structure, and the film layers also need to be planarized by CMP (Chemical Mechanical Polishing), thereby increasing a plurality of process steps and costs virtually, and the stability of the silicon oxide 1042 is relatively general, and is easily affected in the subsequent steps like sacrificial layer removal, which results in unstable overall supporting performance.
Referring to fig. 2 and fig. 3, fig. 2 is a schematic cross-sectional structure diagram of a semiconductor device according to an embodiment of the present disclosure, and fig. 3 is a schematic top-view structure diagram of a portion of a core region and a step region of the semiconductor device in fig. 2. The semiconductor device 200 in the embodiment of the present application includes a substrate 201, a stack layer 202 stacked on the substrate 201, and a dummy channel structure 203 penetrating the stack layer 202 in a direction perpendicular to the substrate 201, wherein the dummy channel structure 203 includes a dummy channel hole 2031, amorphous carbon 2032 filled in the dummy channel hole 2031, and a first barrier layer 2033 located between the amorphous carbon 2032 and the dummy channel hole 2031 and surrounding the amorphous carbon 2032.
The substrate 201 is a semiconductor substrate, and may be, for example, Silicon, Germanium, or Silicon-On-Insulator (SOI) or Germanium-On-Insulator (GOI). In some embodiments, the substrate 201 may also be a substrate including other element semiconductors or compound semiconductors, such as gallium arsenide, indium phosphide, or silicon carbide. The first barrier layer 2033 is made of a material that primarily includes an insulating material, which may include an oxide, such as silicon oxide.
In this embodiment, the amorphous carbon 2032 contains a large amount of SP3The hybridized bond can make the amorphous carbon 2032 reach the hardness similar to that of diamond, such as the maximum hardness of 100Gpa, and the SP3The hybrid bond has good chemical stability and thermal stability, so that the amorphous carbon 2032 is not affected by the material and temperature used in the subsequent gate layer manufacturing process, and the support reliability of the virtual channel structure 203 is improved. Amorphous carbon 2032 further contains a small amount of SP2Hybrid bond due to SP2The hybrid bond has strong insulation, so that the resistivity of the amorphous carbon 2032 can be high, for example, the resistivity range can be 1012Ω/cm～1016Omega/cm, without adversely affecting the electrical performance of the semiconductor device 200.
In addition, the stack layer 202 includes an upper select gate layer, a lower select gate layer, and a plurality of gate layers 2021 and gate insulating layers 2022 alternately stacked between the upper select gate layer and the lower select gate layer, where the gate layer 2021 is formed by replacing a sacrificial layer. In addition to the dummy channel structure 203, a storage channel structure 204 is formed in the stacked layer 202 in a direction perpendicular to the substrate 201, and the storage channel structure 204 includes a storage channel hole 2041, and a storage functional layer 2042 and a channel layer 2043 sequentially stacked on an inner wall of the storage channel hole 2041, where the storage functional layer 2042 includes a second blocking layer, a charge storage layer, and a tunneling layer (not shown) sequentially stacked on an inner wall of the storage channel hole 2041.
Generally, the stacked layer 202 includes a core region N1 and a step region N2, the stacked layer 202 of the step region N2 is stepped in a direction perpendicular to the substrate 201, and the number of steps in the step region N2 may be determined according to the number of memory cells to be formed. The memory channel structure 204 is located in the core region N1, the dummy channel structure 203 is located in the step region N2, the stacked layer 202 of the step region N2 is further covered with a dielectric layer 205, and the dummy channel structure 203 penetrates through the stacked layer 202 of the step region N2 and the dielectric layer 205, wherein the material of the dielectric layer 205 may include oxides such as silicon oxide, hafnium oxide, aluminum oxide, tantalum oxide, and the like.
In some embodiments, the core region N1 may be located in the middle of the substrate 201 and the step region N2 may be located on both sides of the substrate 201, and in other embodiments, the core region N1 may be located on both sides of the substrate 201 and the step region N2 may be located in the middle of the substrate 201, with only a portion of the step region N2 being shown in fig. 2.
Different from the prior art, in the semiconductor device 200 provided in this embodiment of the present application, the dummy trench structure 203 penetrating through the stack layer 202 is formed in a direction perpendicular to the substrate 201, and the dummy trench structure 203 includes the dummy trench hole 2031, the amorphous carbon 2032 filled in the dummy trench hole 2031, and the first blocking layer 2033 located between the amorphous carbon 2032 and the dummy trench hole 2031 and surrounding the amorphous carbon 2032, so that the high hardness, the strong insulation property, and the better thermal stability and chemical stability of the amorphous carbon 2032 can be utilized to provide a reliable supporting capability for the stack layer 202, avoid the collapse or the recess of the stack layer 202, and facilitate the improvement of the yield of the semiconductor device 200.
Based on the semiconductor device 200 provided in the above embodiment, an embodiment of the present application further provides a manufacturing method of the semiconductor device 200, please refer to fig. 4 and fig. 2-3, where the manufacturing method includes the following steps:
step S101, providing a substrate 201, wherein a stack layer 202 is formed on the substrate 201.
The substrate 201 is a semiconductor substrate, and may be, for example, silicon, germanium, SOI, GOI, or the like.
Step s102. a dummy trench hole 2031 is formed through the stack of layers 202 in a direction perpendicular to the substrate 201.
Step s103, a first blocking layer 2033 is formed on the inner wall of the dummy trench hole 2031.
Step s104, amorphous carbon 2032 is filled in the dummy trench hole 2031 where the first blocking layer 2033 is formed, so as to obtain a dummy trench structure 203.
In this embodiment, the amorphous carbon 2032 contains a large amount of SP3The hybrid bond can make the amorphous carbon 2032 reach the hardness similar to that of diamond, such as the maximum hardness of 100Gpa,and, SP3The hybrid bond has good chemical stability and thermal stability, so that the amorphous carbon 2032 is not affected by the material and temperature used in the subsequent manufacturing of the gate layer, and the support reliability of the virtual channel structure 203 is improved. Amorphous carbon 2032 further contains a small amount of SP2Hybrid bond due to SP2The hybrid bond has strong insulation, so that the resistivity of the amorphous carbon 2032 can be high, for example, the resistivity range can be 1012Ω/cm～1016Ω/cm。
The stack layer 202 may include a plurality of sacrificial layers and gate insulating layers 2022 stacked alternately, the sacrificial layers and the gate insulating layers 2022 may be deposited alternately on the substrate 201 by CVD (Chemical Vapor Deposition), ALD (Atomic layer Deposition) technique or other suitable Deposition method, the material for forming the gate insulating layer 2022 may include any one of silicon oxide, silicon nitride, silicon oxynitride and silicon carbonitride, and the material for the sacrificial layers may include silicon nitride. The material from which the first barrier layer 2033 is made may comprise an oxide, such as silicon oxide.
It should be noted that, referring to fig. 5, since the hardness of the amorphous carbon 2032 may be sufficiently high, when the first barrier layer 2033 is formed, the amorphous carbon 2032 may be directly deposited on the inner wall by a deposition method such as CVD, and a two-step method is not required to deposit a layer of silicon nitride on the inner wall by ALD first, and then form dense silicon oxide (i.e., the first barrier layer 2033) after oxidizing the silicon nitride by ISSG (in-situ steam generation), which greatly simplifies the manufacturing process.
Further, after the step S104, the method for manufacturing the semiconductor device 200 may further include the steps of:
performing a planarization process on the dummy trench hole 2031 filled with the amorphous carbon 2032;
the dummy trench hole 2031 after the planarization process is cleaned.
Wherein the planarization process may be performed by a CMP technique.
In addition, after the dummy channel structure 203 is manufactured, if the sacrificial layer in the stacked layer 202 is to be replaced by the gate layer 2021, a gate line slit 206 penetrating through the stacked layer 202 is formed in the core region N1 of the stacked layer 202, and then the sacrificial layer is removed through the gate line slit 206 and filled with a metal material (such as tungsten) to obtain the gate layer 2021, thereby completing the replacement of the sacrificial layer. In this process, the first blocking layer 2033 in the dummy trench 2031 protects the amorphous carbon 2032 to ensure that the amorphous carbon 2032 is not affected by the material and temperature used in the replacement process, and to prevent the core region N1 from collapsing or sinking during the replacement process.
In this embodiment, the semiconductor device 200 further includes a common source structure (not shown), the common source structure is located in the gate line slit 206, and the manufacturing method of the semiconductor device 200 further includes:
forming a gate line slit 206 penetrating the stack layer 202 in a direction perpendicular to the substrate 201;
a common source structure is formed through the gate line slit 206;
and carrying out primary planarization treatment on the common source structure.
After the sacrificial layer is replaced by the gate line slit 206, a common source structure may be formed in the gate line slit 206, where the common source structure may include a spacer layer located on the sidewall surface of the gate line slit 206 and a common source (not shown in the figure) located on the surface of the spacer layer, where the spacer layer is made of an insulating material, such as an oxide, the common source is made of a conductive material, such as titanium or titanium nitride, polysilicon, and/or tungsten, and the bottom of the common source is connected to the substrate 201 to provide a conductive channel for source connection.
In this embodiment, the common source structure may be formed by deposition, and since the amorphous carbon 2032 is filled in the dummy trench hole 2031, and the hardness is high, the deposition thickness may be reduced compared to the common source structure that needs to deposit a thick film layer, so that the common source structure may be planarized by a subsequent CMP process, and may not need to be subjected to multiple CMP processes as in the conventional structure, thereby effectively reducing the process steps and the cost.
It is to be understood that, in addition to the dummy channel structure 203, a memory channel structure 204 is also required to be fabricated, that is, the fabrication method of the semiconductor device 200 further includes the following steps:
forming a memory channel hole 2041 through the stacked layers 202 in a direction perpendicular to the substrate 201;
a memory function layer 2042 is formed on the inner wall of the memory channel hole 2041;
a channel layer 2043 is formed on the memory function layer 2042, resulting in a memory channel structure 204.
The storage channel hole 2041 may be formed in the same process as the dummy channel hole 2031, or may be formed in a different process. The memory function layer 2042 may include a second blocking layer, a charge storage layer and a tunneling layer (not shown in the figure) which are sequentially stacked, and may be a silicon oxide-silicon nitride-silicon oxide (ONO) structure, that is, the second blocking layer and the tunneling layer are made of materials mainly including an insulating material, which may include an oxide such as silicon oxide, the charge storage layer is made of materials mainly including silicon nitride, and the channel layer 2043 is made of materials mainly including polysilicon.
Different from the prior art, in the method for manufacturing the semiconductor device 200 according to this embodiment, the dummy trench 2031 penetrating through the stack layer 202 is formed in a direction perpendicular to the substrate 201, the first blocking layer 2033 is formed on the inner wall of the dummy trench 2031, and then the amorphous carbon 2032 is filled, so that the stack layer 202 can be reliably supported by using the high hardness, the strong insulation property, and the better thermal stability and the chemical stability of the amorphous carbon 2032, and the collapse or the recess of the stack layer 202 is avoided, which is beneficial to improving the yield of the semiconductor device 200, and the process steps can be effectively reduced, the process flow can be simplified, and the process cost can be reduced.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate, wherein a stack layer is formed on the substrate;
forming a dummy channel hole through the stacked layers in a direction perpendicular to the substrate;
forming a first barrier layer on the inner wall of the virtual channel hole;
and filling amorphous carbon in the virtual channel hole with the first barrier layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the amorphous carbon includes SP3Hybrid bond and SP2Hybrid bond, the SP3The content of hybrid bonds is greater than the SP2Content of hybrid bonds.
3. The method for manufacturing a semiconductor device according to claim 1, further comprising, after filling amorphous carbon in the dummy trench hole in which the first barrier layer is formed:
performing primary planarization treatment on the virtual channel hole filled with the amorphous carbon;
and cleaning the virtual channel hole after the planarization treatment.
4. The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming a gate line slit penetrating the stacked layers in a direction perpendicular to the substrate;
forming a common source structure through the gate line slit;
and carrying out primary planarization treatment on the common source structure.
5. The method for manufacturing a semiconductor device according to claim 1, further comprising:
forming a storage channel hole penetrating the stacked layers in a direction perpendicular to the substrate;
forming a storage function layer on an inner wall of the storage channel hole;
forming a channel layer on the memory function layer.
6. A semiconductor device, comprising:
a substrate having a stack layer formed thereon;
a dummy channel structure that penetrates the stacked layers in a direction perpendicular to the substrate;
the dummy channel structure comprises a dummy channel hole, amorphous carbon filled in the dummy channel hole, and a first blocking layer located between the amorphous carbon and the dummy channel hole and surrounding the amorphous carbon.
7. The semiconductor device according to claim 6, wherein the amorphous carbon includes SP therein3Hybrid bond and SP2Hybrid bond, the SP3The content of hybrid bonds is greater than the SP2Content of hybrid bonds.
8. The semiconductor device according to claim 6, wherein a material for forming the first barrier layer comprises silicon oxide.
9. The semiconductor device according to claim 6, further comprising:
and the storage channel structure penetrates through the stacking layer in the direction vertical to the substrate, and comprises a storage channel hole, and a storage functional layer and a channel layer which are sequentially stacked on the inner wall of the storage channel hole.
10. The semiconductor device according to claim 9, wherein the memory function layer comprises a second barrier layer, a charge storage layer, and a tunneling layer sequentially stacked on an inner wall of the memory channel hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011353916.7A CN112490250A (en) | 2020-11-26 | 2020-11-26 | Manufacturing method of semiconductor device and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011353916.7A CN112490250A (en) | 2020-11-26 | 2020-11-26 | Manufacturing method of semiconductor device and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112490250A true CN112490250A (en) | 2021-03-12 |
Family
ID=74935796
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011353916.7A Pending CN112490250A (en) | 2020-11-26 | 2020-11-26 | Manufacturing method of semiconductor device and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112490250A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078163A (en) * | 2021-03-24 | 2021-07-06 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150236038A1 (en) * | 2014-02-20 | 2015-08-20 | Sandisk Technologies Inc. | Multilevel memory stack structure and methods of manufacturing the same |
| CN108470737A (en) * | 2018-03-19 | 2018-08-31 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
| CN108550578A (en) * | 2018-03-26 | 2018-09-18 | 长江存储科技有限责任公司 | Three-dimensional storage manufacturing method |
-
2020
- 2020-11-26 CN CN202011353916.7A patent/CN112490250A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150236038A1 (en) * | 2014-02-20 | 2015-08-20 | Sandisk Technologies Inc. | Multilevel memory stack structure and methods of manufacturing the same |
| CN108470737A (en) * | 2018-03-19 | 2018-08-31 | 长江存储科技有限责任公司 | Three-dimensional storage and its manufacturing method |
| CN108550578A (en) * | 2018-03-26 | 2018-09-18 | 长江存储科技有限责任公司 | Three-dimensional storage manufacturing method |
Non-Patent Citations (1)
| Title |
|---|
| 周升国: "《非晶碳薄膜概述》", 《耐磨防腐非晶碳薄膜技术》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113078163A (en) * | 2021-03-24 | 2021-07-06 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113707665B (en) | Memory and forming method thereof | |
| CN109075175B (en) | Through storage level through hole structure between stepped areas in three-dimensional storage device and preparation method thereof | |
| US9373400B2 (en) | Vertical structure semiconductor memory devices and methods of manufacturing the same | |
| US11631691B2 (en) | Three-dimensional flat memory device including a dual dipole blocking dielectric layer and methods of making the same | |
| US11700728B2 (en) | Non-volatile memory device | |
| CN110581138B (en) | Semiconductor element and manufacturing method thereof | |
| CN110010607B (en) | Non-volatile memory structure and manufacturing method thereof | |
| WO2021118621A1 (en) | Three-dimensional nor array including active region pillars and method of making the same | |
| US10804282B2 (en) | Three-dimensional memory devices using carbon-doped aluminum oxide backside blocking dielectric layer for etch resistivity enhancement and methods of making the same | |
| US20120256253A1 (en) | Vertical Memory Devices | |
| CN111403398B (en) | Method for forming step structure of 3D NAND, 3D NAND memory and manufacturing method thereof | |
| CN107958909A (en) | Flush memory device and its manufacture method | |
| US11756877B2 (en) | Three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same | |
| JP2019145635A (en) | Storage device | |
| CN112490250A (en) | Manufacturing method of semiconductor device and semiconductor device | |
| CN109411481A (en) | A kind of semiconductor devices and its manufacturing method | |
| CN108933145B (en) | Three-dimensional memory | |
| CN113345909B (en) | Three-dimensional memory, preparation method of three-dimensional memory and storage system | |
| CN116097919A (en) | Preparation method of three-dimensional memory | |
| TW202236615A (en) | Memory device and method for fabricating the same | |
| TW202137506A (en) | Memory element and method for manufacturing the same | |
| CN109524415B (en) | Manufacturing method of three-dimensional memory and three-dimensional memory | |
| CN114284214B (en) | Semiconductor device, preparation method thereof and storage device | |
| US20230232611A1 (en) | Semiconductor devices | |
| CN114551345A (en) | Three-dimensional memory and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210312 |
|
| RJ01 | Rejection of invention patent application after publication |