CN111403398B

CN111403398B - Method for forming step structure of 3D NAND, 3D NAND memory and manufacturing method thereof

Info

Publication number: CN111403398B
Application number: CN202010221370.3A
Authority: CN
Inventors: 张磊; 汤召辉; 周玉婷; 曾凡清
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2020-03-26
Filing date: 2020-03-26
Publication date: 2023-04-07
Anticipated expiration: 2040-03-26
Also published as: CN111403398A

Abstract

The invention provides a method for forming a step structure, a 3D NAND memory and a manufacturing method thereof. Thereby, the same step area comprises step structures respectively communicated with two adjacent core areas. The occupied area of the step structure on the substrate is reduced, so that the size of each memory cell on the substrate can be reduced, and the number of the memory cells on the substrate can be increased. An isolation structure is arranged between the partition steps between the two adjacent core regions, and the isolation structure is connected with the word line isolation layer in the common source electrode, so that the insulation of the first part and the second part in the partition steps is realized, the risk of short circuit of the word line layers in the two core regions is reduced, and the product yield is improved.

Description

Method for forming step structure of 3D NAND, 3D NAND memory and manufacturing method thereof

Technical Field

The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular, to a method for forming a step structure of a 3D NAND, a 3D NAND memory, and a method for manufacturing the same.

Background

As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and achieve lower cost per bit are becoming more and more popular. 3D memory is a technology for stacking data units, and stacking of more than 32 layers, even 72, 96, 128 or more layers of data units has been achieved. The vertical memory structure of the 3D memory device is formed by stacking a plurality of dielectric films, wherein a word line layer needs to be led out through a word line contact. It is common in the prior art to form step areas on both sides of the memory array, and to form contacts for each word line layer on the step areas.

In the prior art, step regions are generally formed on two sides of the core region, and in order to insulate adjacent core regions from each other, an isolation space is generally reserved between the adjacent step regions. Therefore, the occupied area of the step region on the substrate is increased, and the reduction of the size of the device is not facilitated.

Disclosure of Invention

In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for forming a step structure of a 3D NAND, a 3D NAND memory and a method for manufacturing the same, so as to reduce the occupied area of a step region on a substrate, which is beneficial to reducing the size of a device.

To achieve the above and other related objects, the present invention provides a method for forming a step structure of a 3D NAND memory, comprising the steps of:

providing a substrate, wherein a stacking structure is formed on the substrate and comprises a plurality of core areas and step areas positioned on two sides of the core areas;

forming a plurality of partition steps in the step area;

forming a first part and a second part in each of the partition steps between two adjacent core regions, the steps of the first part gradually decreasing from a first core region to a second core region in the two adjacent core regions, the steps of the second part gradually decreasing from the second core region to the first core region, and the first part and the second part being staggered with each other in a predetermined direction.

Optionally, the method for forming a step structure further includes:

forming an isolation structure in the partition step between two adjacent core regions, the isolation structure isolating the adjacent partition steps and isolating the first portion of the partition step from the second core region and isolating the second portion of the partition step from the first core region.

Optionally, the forming of the isolation structure in the partition step between two adjacent core regions further comprises:

forming a first trench extending in a first direction and penetrating the partition step in the partition step between two adjacent core regions;

second trenches extending in opposite directions in a second direction perpendicular to the first direction from both ends of the first trench are formed at both ends of the first trench.

Optionally, the forming of the first trench extending in the first direction and penetrating the partition step in the partition step between two adjacent core regions further comprises: the first groove is formed between two adjacent partition steps.

Optionally, forming second trenches at both ends of the first trench, the second trenches extending from both ends of the first trench in a second direction perpendicular to the first direction in opposite directions, further comprises:

forming the second trench between the first portion and the second core region;

forming the second trench between the second portion and the first core region.

Optionally, the method for forming the step structure further includes:

and filling an isolation material in the first trench and the second trench.

The invention also provides a manufacturing method of the 3D NAND memory, which comprises the following steps:

forming a step structure in the stacked structure of the substrate according to the above-described step structure forming method of the present invention;

forming a memory structure in a core region of the stacked structure;

forming a gate line slit penetrating the stacked structure in a stacking direction of the stacked structure, the gate line slit extending in a first direction perpendicular to the stacking direction and penetrating through the step structure;

a word line layer is formed in place of the sacrificial layer in the stacked structure.

Optionally, the forming of the gate line slit penetrating the stacked structure further includes:

the gate line slit is formed between a first portion and a second portion of the partition step between adjacent two of the core regions.

Optionally, the method further comprises the following steps:

forming a word line isolation layer on the side wall of the gate line gap;

and forming a common source contact in the grid line gap.

Optionally, the method further comprises the following steps:

forming a plurality of word lines respectively communicating with the word line layers of two core regions on both sides of the division step in the first and second portions of the division step between the adjacent two core regions.

Optionally, the forming a memory structure in the core region further comprises:

forming channel holes arranged in an array penetrating through the stacked structure in the core region;

forming a blocking layer, a charge trapping layer and a tunneling layer on the side wall of the channel hole in sequence;

a channel layer is formed in the channel hole.

The present invention also provides a 3D NAND memory, the 3D NAND memory including:

a substrate;

forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of core areas and step areas positioned on two sides of the core areas;

a partition step formed in the step area;

first and second portions formed in the partition step between the adjacent two core regions, the first and second portions communicating with the adjacent two core regions, respectively, and the first and second portions being staggered with each other in a predetermined direction;

a memory structure formed in the core region;

a common source through the stacked structure, the common source through the stacked structure.

Optionally, the first portion and the second portion are staggered.

Optionally, the 3D NAND memory further comprises an isolation structure between the first portion and the second portion.

Optionally, the isolation structure comprises:

a first trench extending in a first direction and penetrating the partition step;

a second trench extending in a second direction perpendicular to the first direction from both ends of the first trench in an opposite direction;

an isolation material filled in the first trench and the second trench.

Optionally, the storage structure comprises:

an array of trench holes extending through the stacked structure of the core region;

a blocking layer, a charge trapping layer and a tunneling layer sequentially formed on the sidewall of the channel hole;

a channel layer formed within the channel hole.

Optionally, the 3D NAND memory further comprises: forming a plurality of word lines in the partition step, the word lines being in communication with word line layers in the stacked structure.

As described above, the method for forming a step structure of a 3D NAND, the 3D NAND memory, and the method for manufacturing the same according to the present invention have at least the following advantageous effects:

in the forming process of the step structure and the 3D NAND memory, a plurality of core areas and step areas are formed in the stacked structure, the step areas form a plurality of partition steps, a first part and a second part which are insulated from each other are formed in each partition step positioned between two adjacent core areas, the first part and the second part are respectively communicated with the adjacent first core areas and the adjacent second core areas, and the first part and the second part are arranged in a staggered mode. Therefore, the same step area comprises step structures respectively communicated with two adjacent core areas. The occupied area of the step structure on the substrate is reduced, so that the size of each memory unit on the substrate can be reduced, and the number of the memory units on the substrate can be increased.

The isolation structure is arranged between the partition steps between the two adjacent core areas, the isolation structure is connected with the word line isolation layers in the memory, the insulation of the first part and the second part in the partition steps is realized, the first part and the second part are respectively communicated with the first core area and the second core area, meanwhile, the short circuit between the first core area and the second core area cannot occur, the risk of the short circuit of the word line layers in the two core areas is reduced, and the product yield is improved.

Drawings

Fig. 1 is a schematic plan view showing a substrate having a core region and a step region formed therein according to the prior art.

Fig. 2 is a schematic cross-sectional view taken along line L-L of fig. 1.

Fig. 3 is a flowchart illustrating a method for forming a step structure of a 3D NAND memory according to an embodiment of the invention.

Fig. 4 is a schematic diagram showing the formation of a stacked structure on a substrate.

Fig. 5 is a schematic plan view showing the formation of a step structure in the structure shown in fig. 4.

FIG. 6 is a schematic cross-sectional view taken along line L0-L0 of FIG. 5.

Fig. 7 is a schematic view of a structure for forming a first trench and a second trench in the structure shown in fig. 5.

Fig. 8 is a schematic structural diagram illustrating an isolation structure formed by filling an isolation material in the first trench and the second trench shown in fig. 7.

Fig. 9 is a schematic cross-sectional view taken along line L1-L1 of fig. 8.

FIG. 10 is a flowchart illustrating a method for fabricating a 3D NAND memory according to a second embodiment of the present invention.

Fig. 11 is a schematic plan view of a memory structure formed in a stacked configuration.

Fig. 12 is a schematic cross-sectional view taken along line L2-L2 of fig. 11 when a channel hole is formed in the stacked structure.

Fig. 13 is a schematic diagram of a structure for forming a memory structure in the structure shown in fig. 12.

Fig. 14 is a schematic plan view showing the formation of a gate line slit.

Fig. 15 is a schematic cross-sectional view taken along line L3-L3 of fig. 14.

Fig. 16 is a schematic structural view showing the formation of a gate trench.

Fig. 17 is a schematic view illustrating a structure of a word line layer formed in the gate trench shown in fig. 16.

Fig. 18 shows a schematic structure of a common source.

Description of the element reference numerals

01. Substrate and method of manufacturing the same

02. Stacking structure

021-1 core region

021-2 core region

022-1 step region

022-2 stepped region

023. Spacer region

100. Substrate and method of manufacturing the same

101. Stacking structure

1011. Insulating layer in stacked structure

1012. Sacrificial layer in stacked structure

1021. A first core region

1022. A second core region

103. Step area

104. Isolation structure

1041. First trench

1042. Second trench

105. Partition step

1051. First part of the partition step

1052. Second part of the partition step

106. Memory structure

1060. Channel hole

1061. Barrier layer

1062. Charge trapping layer

1063. Tunneling layer

1064. Channel layer

1065. Dielectric isolation material

107. Common source

1070. Grid line gap

1071. Word line isolation layer

1072. Common source contact

108. Gate trench

109. Word line layer

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention in a schematic manner, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of each component in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated.

As shown in fig. 1 and fig. 2, when forming a plurality of memory regions on the same substrate (e.g. a wafer), a plurality of core regions are usually formed on the substrate in the prior art, such as the core regions 021-1 and 021-2 and the step regions formed on both sides of the core region as shown in fig. 1. The stepped regions between the two core regions 021-1 and 021-2 include stepped regions 022-2 and 022-2 communicating with the core regions 021-1 and 021-2, respectively, and there is generally a spaced region 023 between the two stepped regions. Obviously, such an arrangement increases the area of the substrate occupied by the memory region, which is detrimental to reducing the substrate size and the size of the devices at a later stage.

In view of the above-mentioned drawbacks in the prior art, the present invention provides a method for forming a step structure of a 3D NAND, a 3D NAND memory and a method for manufacturing the same, so as to solve the above-mentioned drawbacks. The present invention will now be described in detail by the following specific embodiments in conjunction with the accompanying drawings.

Example one

The present embodiment provides a method for forming a step structure of a 3D NAND memory, as shown in fig. 3, the method including the steps of:

step S101: providing a substrate, wherein a stacking structure is formed on the substrate and comprises a plurality of core areas and step areas positioned on two sides of the core areas;

referring to fig. 4 and 5, a substrate 100 is provided, and the substrate 100 is formed in a first direction, i.e., an X direction shown in fig. 5, and a second direction, i.e., a Y direction shown in fig. 5. A stacked structure 101 is formed over the substrate 100 in a third direction, i.e., the Z direction shown in fig. 4, and the stacked structure 101 is formed by alternately arranging insulating layers 1011 and sacrificial layers 1012. Substrate 100 may be a silicon, single crystal silicon-on-insulator, or other suitable material substrate in this embodiment. The insulating layer 1011 in the stack structure may be silicon oxide and the sacrificial layer 1012 may be silicon nitride, i.e. the stack structure forms an ONO stack structure of alternating silicon oxide and silicon nitride, which may comprise 64, 96, 128 or other layers or even more.

As is well known to those skilled in the art, an etch stop layer (not shown), which may be silicon oxide, may be further formed between the substrate 100 and the stacked structure 101.

The stacked structure on the substrate comprises a plurality of core areas and step areas positioned on two sides of the core areas. In the present embodiment, referring to fig. 5, two

core areas

1021 and 1022 of the stacked structure 101, and a stepped area 103 located between the two core areas are illustrated. It should be understood that although not shown, stepped areas are also formed outside the core areas (1021, 1022), i.e., on the right side of the first core area 1021 and on the left side of the second core area 1022 in fig. 5.

Step S102: forming a plurality of partition steps in the step area;

as is well known, the stacked structure is etched, and steps extending from the core region to both sides and gradually decreasing are formed through multiple trimming and etching processes, that is, steps extending from the core region to both sides along the X direction and gradually decreasing are formed. Then, a plurality of partition steps (SDS) are formed in the step area 103 (see fig. 7). The partition steps form n, n-1, 8230, and 1 st partition steps from the middle part to both sides along the Y direction shown in FIG. 2, preferably, each partition step is symmetrically distributed with respect to the n-th partition step, each partition step includes steps increasing in the X direction along the direction toward the core region, and n is a natural number greater than 2. As is well known, the ends of the partition steps (i.e., the ends near the core region) in the X direction have redundant step regions (not specifically shown) having a plurality of same-step steps.

The partition steps are formed with steps in both the X direction and the Y direction, and each step is used to form word line contacts of a word line layer corresponding thereto, so that a floor area of the step can be reduced, an integration of the device can be improved, and the partition step 120 can have different partitions, for example, 3 partitions, 4 partitions, or more partitions, according to different needs. In the formed partition steps, the nth partition is positioned in the center, the (n-1) th partition, \8230 \ 8230:, the 2 nd partition and the 1 st partition are sequentially arranged from the nth partition to two sides along the Y direction and face the core storage area direction along the X direction, and the steps of each partition are sequentially increased by n levels. In the Y direction, the composite step of each layer is sequentially increased by 1 level from the 1 st partition to the nth partition. In the present invention, the partition manner and number are not limited.

Step S103: forming a first portion and a second portion in each of the partition steps between two adjacent core regions, forming a step that is stepped down from a first core region to a second core region in the two adjacent core regions in the first portion, forming a step that is stepped down from the second core region to the first core region in the second portion, the first portion and the second portion being staggered with each other in a predetermined direction.

Referring to fig. 6, the step area 103 between the adjacent two

core areas

1021 and 1022 is also formed with a plurality of partition steps 105, and a first portion 1051 and a second portion 1052 are formed in the partition steps 105. The first portion 1051 forms a stepwise decreasing step in the direction from the first core area 1021 to the second core area 1022, and the second portion 1052 forms a stepwise decreasing step in the direction from the second core area 1022 to the first core area 1021. The first portion 1051 and the second portion 1052 are formed in the same division step 105, and the first portion 1051 and the second portion 1052 are staggered with each other in the first direction, that is, both are formed in the same length area in the X direction, and the first portion and the second portion are staggered with each other to form an approximately zigzag arrangement. Compared with the prior art shown in fig. 2, the method is equivalent to only occupying one step region shown in fig. 2, and the length of the step region is greatly reduced, so that the area of the step region occupying the substrate in the X direction is greatly reduced, and the size of the substrate and the size of a later device are favorably reduced.

In a preferred embodiment, the above method further comprises: forming an isolation structure in the partition step between two adjacent core regions, the isolation structure isolating the adjacent partition steps and isolating the first portion of the partition step from the second core region and isolating the second portion of the partition step from the first core region.

First, as shown in fig. 7, a first trench 1041 is formed in the adjacent partition step 105, the first trench 1041 extending in the first direction (X direction) and penetrating the partition step 105. In a preferred embodiment, a first trench 1041 is formed between the first portion 1051 and the second portion 1052 of the partition step 105. As shown in fig. 7, the first trenches 1041 space the division steps in the Y direction.

Then, referring also to fig. 7, second trenches 1042 are formed at both ends of the first trench 1041, the second trenches 1041 extend in opposite directions in the Y direction at the ends of the first trench 1041, and also penetrate through the stacked structure. In a preferred embodiment, the second trench 1042 is formed between the first portion 1051 of the partition step 105 and the second core region 1022, and between the second portion 1052 and the first core region 1021. More preferably, the second trench 1042 is formed between the first portion 1051 and the second core region 1022 and is formed in a portion of the second portion 1052 in the Y direction between the second core region and the partition step 105. Also preferably, the second groove 1042 is formed between the second portion 1052 and the first core region 1021 between the first core region 1021 and the partition step 105 and is formed in part of the first portion 1051 in the Y direction. As shown in fig. 7, the first trench 1041 and the second trench 1042 are formed to penetrate each other to form an inverted "Z" structure.

The second trench 1042 formed as described above can ensure that the first portion and the second portion can be completely separated by the gate line slit formed in the subsequent memory formation process.

After the first trench 1041 and the second trench 1042 are formed, as shown in fig. 8, an isolation material is filled in the first trench 1041 and the second trench 1042 to form an isolation structure 104. The isolation structure spaces each partition step 105 apart, while leaving the first portion 1051 of each partition step spaced apart from the second core region 1022, and the second portion 1052 spaced apart from the first core region 1021. As shown in the cross-sectional view of fig. 9 along the line L1-L1 in fig. 8, it can be seen that the isolation structure 104 isolates the second portion 1052 of the partition step from the first core region 1021. Also, the isolation structure formed between the first portion and the second core region isolates the first portion from the second core region.

The step structure formed as described above, particularly the step structure formed between two adjacent core regions, the first portion and the second portion are staggered, so that the occupied area of the step structure on the substrate is greatly reduced, the size of each memory cell on the substrate can be reduced, and the number of memory cells on the substrate can be increased.

Example two

The present embodiment provides a method for manufacturing a 3D memory, as shown in fig. 10, the method includes the following steps:

step S201: forming a step structure in the stacked structure of the substrate according to the method of forming a step structure described in the above embodiment;

the step structure shown in fig. 8 and 9 is formed according to the method described in the first embodiment, and the method will not be described in detail.

Step S202: forming a storage structure in the core area;

as shown in fig. 11, after the step structures shown in fig. 8 and 9 are formed, the memory structures 106 are formed in the

core areas

1021 and 1022.

First, as shown in fig. 12, taking the cross-sectional view at the position indicated by the line L2-L2 in fig. 11 as an example, the stacked structure 101 on the substrate is etched first, and a channel hole 1060 penetrating the stacked structure is formed. In a preferred embodiment, portions of the substrate may be etched simultaneously such that the channel hole extends into the substrate.

Then, as shown in fig. 13, a selective epitaxial structure is formed at the bottom of the channel hole 1060. Before the selective epitaxial structure is formed, the channel hole can be cleaned after being etched, so that the cleanliness of the channel hole, particularly the cleanliness of the bottom of the channel hole, is ensured, the uniformity and consistency of the selective epitaxial structure are improved, and the electrical characteristics of the selective epitaxial structure are improved. A blocking layer 1061, a charge trapping layer 1062, a tunneling layer 1063, and a channel layer 1064 are then sequentially formed along the sidewalls of the channel hole toward the center, with the channel layer 1064 in communication with the selective epitaxial structure. In a preferred embodiment, after the channel layer is formed, a dielectric material may be further filled in the channel hole. In a preferred embodiment, the material of the barrier layer may be a high-K dielectric. The high-K dielectric material has a thinner Equivalent Oxide Thickness (EOT) which effectively reduces gate leakage while maintaining transistor performance. The high K dielectric may be, for example, alumina, zirconia, or the like. The barrier layer may be a single layer of dielectric oxide or a dual layer model, such as high K oxide and silicon oxide.

Step S203: forming a gate line slit penetrating the stacked structure in a stacking direction of the stacked structure, the gate line slit extending in a first direction perpendicular to the stacking direction and passing through the step structure;

as shown in fig. 14, a gate line slit 1070 is formed in the stacked structure, and the gate line slit 107 penetrates through the stepped structure. As shown in fig. 15, which illustrates a cross-sectional view along line L3-L3 of fig. 14, the stacked structure is etched to form a gate line slit 1070 that extends through the stacked structure. Preferably, as shown in fig. 15, portions of the substrate are simultaneously etched such that the gate line slits are simultaneously formed in portions of the substrate. The gate line slit 1070 penetrates through the step structure, and in the divisional step 105 between the two

core regions

1021 and 1022, the gate line slit 1070 is formed between the first portion 1051 and the second portion 1052, cutting off the first portion 1051 and the second portion 1052.

As described in the first embodiment, in the partition steps 105, the isolation structure spaces each partition step 105 apart, while allowing the first portion 1051 of each partition step to be spaced apart from the second core region 1022, and the second portion 1052 to be spaced apart from the first core region 1021. As shown in the cross-sectional view of fig. 9 along the line L1-L1 in fig. 8, it can be seen that the isolation structure 104 isolates the second portion 1052 of the partition step from the first core region 1021. Also, the isolation structure formed between the first portion and the second core region isolates the first portion from the second core region. Therefore, the gate line slit formed between the first portion and the second portion can penetrate through a portion of the isolation structure formed in the second trench, thereby completely isolating the first portion from the second portion, so that the first portion 1051 and the second portion 1052 staggered from each other in the first direction are isolated from each other.

Step S204: replacing a sacrificial layer in the stacked structure to form a word line layer;

after the gate line slit 1070 is formed, the sacrificial layer in the stacked structure is replaced by the gate line slit, forming a word line layer. First, as shown in fig. 16, the sacrificial layer 1012 in the stacked structure is removed, for example, an acid etching method commonly used in the art may be used, and an acid solution enters the stacked structure through the gate line slit 160 to etch the sacrificial layer and finally remove the sacrificial layer, so as to form the gate trench 108 at the position of the sacrificial layer. Then, as shown in fig. 17, a conductive material, for example, a metal material is filled in the gate trench 108 to form a word line layer 109.

In a preferred embodiment, after forming the word line layer shown in fig. 17, a step of forming the common source 107 (also refer to fig. 14) in the gate line slit 1070 is further included. As shown in fig. 18, a word line isolation layer 1071 is first formed on the sidewall of the gate line slit, and then a common source contact 1070 is formed by filling the gate line slit with a conductive material, such as polysilicon.

Referring to fig. 14, in the stepped structure between two adjacent core regions, the common source electrode 107 is also formed between the first portion 1051 and the second portion 1052 of the division step 105, whereby the word line isolation layer on the sidewall of the gate line slit and the isolation structure 104 in the division step are connected to each other, completely spacing the first portion 1051 and the second portion 1052, enabling the first portion and the second portion to communicate with the first core region and the second core region, respectively, while the first portion and the second portion are insulated from each other, preventing a short circuit between the adjacent core regions.

In a preferred embodiment, there is further included the step of forming a word line contact in communication with the word line layer and a plurality of word lines in the partition step 105. Particularly in a divisional step between adjacent two of the core regions, a plurality of word lines respectively communicating with the word line layers of two core regions on both sides of the divisional step are formed in the first portion and the second portion, respectively. Therefore, the lead-out of the word line layer of the core area at two sides can be formed in a smaller step area.

The first and

second portions

1051 and 1052 of the partition step 105 between the first and

second core regions

1021 and 1022 are staggered with respect to each other, communicating with the first and second core regions, respectively. Therefore, the occupied area of the step area on the substrate is greatly reduced, the size of each memory cell on the substrate can be reduced, and the number of the memory cells on the substrate can be increased.

EXAMPLE III

The present embodiment provides a 3D NAND memory, which can be similarly referred to fig. 4 to 9 and fig. 11 to 18, and includes:

a substrate; forming a stacked structure on the substrate, wherein the stacked structure comprises a plurality of core areas and step areas positioned on two sides of the core areas; a partition step formed in the step area; a first portion and a second portion formed in the partition step between two adjacent core regions, the first portion and the second portion being respectively communicated with the two adjacent core regions; a memory structure formed in the core region; and a common source through the stacked structure, the common source through the stacked structure.

Referring to fig. 14 to 18, the substrate 100 is formed in a plane in a first direction, i.e., an X direction shown in fig. 5, and a second direction, i.e., a Y direction shown in fig. 5. A stacked structure 101 is formed over the substrate 100 in a third direction, i.e., the Z direction shown in fig. 4. The stacked structure 101 is formed by alternately arranging insulating layers 1011 and word line layers 109. Substrate 100 may be a silicon, single crystal silicon-on-insulator, or other suitable material substrate in this embodiment. The insulating layer 1011 in the stack structure may be silicon oxide and the sacrificial layer 1012 may be silicon nitride, i.e. the stack structure forms an ONO stack structure with alternating silicon oxide and silicon nitride layers, which may comprise 64, 96, 128 or other layers or even more. The word line layer 109 may be a metal word line layer.

core regions

1021 and 1022 of the stacked structure 101 and the stepped region 103 located between the two core regions are illustrated. It should be understood that although not shown, stepped regions are also formed outside the core regions (1021, 1022), i.e., on the right side of the first core region 1021 and on the left side of the second core region 1022 in fig. 5.

The step area 103 is formed with a plurality of partition steps (SDS) (see fig. 7). The partition steps form n, n-1, 8230, and 1 st partition steps from the middle part to both sides along the Y direction shown in FIG. 2, preferably, each partition step is symmetrically distributed with respect to the n-th partition step, each partition step includes steps increasing in the X direction along the direction toward the core region, and n is a natural number greater than 2. As is well known, in the X direction, the ends of the zoning steps (i.e. the ends close to the core zone) have a redundant step zone (not specifically shown) with a plurality of sibling steps.

Referring to fig. 6, the step area 103 between the adjacent two

core areas

1021 and 1022 is also formed with a plurality of partition steps 105, and a first section 1051 and a second section 1052 are formed in the partition steps 105. The first portion 1051 forms a stepwise decreasing step in the direction from the first core area 1021 to the second core area 1022, and the second portion 1052 forms a stepwise decreasing step in the direction from the second core area 1022 to the first core area 1021. The first portion 1051 and the second portion 1052 are formed in the same partition step 105, and the first portion 1051 and the second portion 1052 are staggered in the first direction, that is, both are formed in the same length area in the X direction, compared with the prior art shown in fig. 2, the length of the partition step is greatly reduced, which is equivalent to only occupying one partition step shown in fig. 2, thereby greatly reducing the area of the partition step occupying the substrate, and being beneficial to reducing the size of the substrate and the size of the devices in the later period.

In a preferred embodiment, an isolation structure is formed in the partition step between two adjacent core regions, the isolation structure isolating the adjacent partition steps and isolating the first portion of the partition step from the second core region and isolating the second portion of the partition step from the first core region. The isolation structure spaces each partition step 105 apart while leaving a first portion 1051 of each partition step spaced apart from the second core region 1022 and a second portion 1052 spaced apart from the first core region 1021.

As shown in fig. 7, the isolation structure includes a first trench 1041 formed in the adjacent partition step 105, a second trench 1042 and an isolation material filled in the first trench and the second trench. The first trench 1041 extends in the first direction (X direction) and penetrates the partition step 105. In a preferred embodiment, a first trench 1041 is formed between the first portion 1051 and the second portion 1052 of the partition step 105. As shown in fig. 7, the first trenches 1041 space the division steps in the Y direction. The second trenches 1042 are formed at both ends of the first trench 1041, and the second trench 1041 extends in the opposite direction in the Y direction at the end of the first trench 1041, and also penetrates the stacked structure. In a preferred embodiment, the second trench 1042 is formed between the first portion 1051 of the partition step 105 and the second core region 1022, and between the second portion 1052 and the first core region 1021. More preferably, the second trench 1042 is formed between the first portion 1051 and the second core region 1022 and is formed in a portion of the second portion 1052 in the Y direction between the second core region and the partition step 105. Also preferably, the second groove 1042 is formed between the second portion 1052 and the first core region 1021 between the first core region 1021 and the partition step 105 and is formed in part of the first portion 1051 in the Y direction. As shown in fig. 7, the first trench 1041 and the second trench 1042 are formed to penetrate each other to form an inverted "Z" structure. As shown in the cross-sectional view of fig. 9 taken along line L1-L1 in fig. 8, it can be seen that the isolation structure 104 isolates the second portion 1052 of the partition step from the first core region 1021. Also, the isolation structure formed between the first portion and the second core region isolates the first portion from the second core region.

As shown in fig. 11, the memory structures 106 are formed in an array in the core region, and as shown in fig. 13, the memory structures include a selective epitaxial structure formed at the bottom of the channel hole 1060, and a blocking layer 1061, a charge trapping layer 1062, a tunneling layer 1063, and a channel layer 1064 sequentially formed along the sidewall of the channel hole toward the center, where the channel layer 1064 is in communication with the selective epitaxial structure. In a preferred embodiment, after the channel layer is formed, the channel hole may be further filled with a dielectric material. In a preferred embodiment, the material of the barrier layer may be a high-K dielectric. The high-K dielectric material has a thinner Equivalent Oxide Thickness (EOT) which effectively reduces gate leakage while maintaining transistor performance. The high-K dielectric may be, for example, alumina, zirconia, or the like. The barrier layer may be a single layer of dielectric oxide or a bilayer model, such as high K oxide and silicon oxide.

Referring to fig. 14, 17, and 18, the common source 107 through the stacked structure includes a gate line slit 1070 through the stacked structure, a word line isolation layer 1071 formed on a gate line slit sidewall, and a common source structure 1072 formed in the gate line slit. As shown in fig. 15, the common source is simultaneously formed in a portion of the substrate. The common source 107 runs through the stepped structure and the common source 107 is formed between the first section 1051 and the second section 1052 in the partition step 105 between the two

core regions

1021 and 1022, cutting off the first section 1051 and the second section 1052.

As described above, in the partition steps 105, the isolation structure 104 spaces each partition step 105 apart while allowing the first portion 1051 of each partition step to be spaced apart from the second core region 1022, and the second portion 1052 to be spaced apart from the first core region 1021. As shown in the cross-sectional view of fig. 9 along the line L1-L1 in fig. 8, it can be seen that the isolation structure 104 isolates the second portion 1052 of the partition step from the first core region 1021. Also, the isolation structure formed between the first portion and the second core region isolates the first portion from the second core region. Accordingly, the wordline isolation layer 1071 of the above-described common source 107 formed in the middle of the first and second portions is connected to the isolation structure 104 in the partition step to completely space the first and

second portions

1051 and 1052, enabling the first and second portions to communicate with the first and second core regions, respectively, while the first and second portions are insulated from each other, preventing short circuits between adjacent core regions.

In a preferred embodiment, the memory further includes word line contacts formed in the partition step 105 to communicate with the word line layer, and a plurality of word lines. Especially in a divisional step between adjacent two of the core regions, a plurality of word lines respectively communicating with the word line layers of two core regions on both sides of the divisional step are formed in the first portion and the second portion, respectively. Thereby, the lead-out of the word line layer of the core area at two sides can be formed in a smaller step area.

The first and

second portions

1051 and 1052 of the partition step 105 between the first and

second core regions

1021 and 1022 are staggered with respect to each other, communicating with the first and second core regions, respectively. Therefore, the occupied area of the step region on the substrate is greatly reduced, the size of each memory cell on the substrate can be reduced, and the number of the memory cells on the substrate can be increased.

As described above, the method for forming a step structure of a 3D NAND, the 3D NAND memory, and the method for manufacturing the 3D NAND memory according to the present invention have at least the following advantageous effects:

in the forming process of the step structure and the 3D NAND memory, a plurality of core areas and step areas are formed in the stacked structure, the step areas form a plurality of partition steps, a first part and a second part which are insulated from each other are formed in each partition step positioned between two adjacent core areas, the first part and the second part are respectively communicated with the adjacent first core areas and the adjacent second core areas, and the first part and the second part are arranged in a staggered mode. Therefore, the same step area comprises step structures respectively communicated with two adjacent core areas. The occupied area of the step structure on the substrate is reduced, so that the size of each memory cell on the substrate can be reduced, and the number of the memory cells on the substrate can be increased.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.

Claims

1. A method for forming a step structure of a 3D NAND memory is characterized by comprising the following steps:

forming a plurality of partition steps in the step area;

forming a first part and a second part in each of the partition steps between two adjacent core regions, wherein the steps of the first part gradually decrease from a first core region to a second core region in the two adjacent core regions, the steps of the second part gradually decrease from the second core region to the first core region, and the first part and the second part are arranged in a staggered manner in a preset direction.

2. The method of forming a stepped structure according to claim 1, further comprising:

3. The method as claimed in claim 2, wherein forming an isolation structure in the partition step between two adjacent core regions further comprises:

forming a first groove extending in a first direction and penetrating through the partition step in the partition step between two adjacent core regions;

4. The method as claimed in claim 3, wherein forming a first trench extending in the first direction and penetrating the step in the step between two adjacent core regions further comprises: the first trench is formed between two adjacent partition steps.

5. The method of forming a stepped structure according to claim 4, wherein forming second trenches at both ends of the first trench, extending from both ends of the first trench in a second direction perpendicular to the first direction in opposite directions, further comprises:

forming the second trench between the first portion and the second core region;

forming the second trench between the second portion and the first core region.

6. The method of forming a stepped structure according to claim 3, further comprising:

and filling an isolation material in the first trench and the second trench.

7. A3D NAND memory manufacturing method is characterized by comprising the following steps:

forming a step structure in a stacked structure of a substrate according to the method of forming a step structure of any one of claims 1 to 6;

forming a memory structure in a core region of the stacked structure;

8. The method of manufacturing a 3D NAND memory of claim 7, forming a gate line slit through the stack structure further comprising:

the gate line slit is formed between the first portion and the second portion of the partition step between adjacent two of the core regions.

9. The method of manufacturing a 3D NAND memory of claim 8 further comprising the steps of:

forming a word line isolation layer on the side wall of the gate line gap;

and forming a common source contact in the grid line gap.

10. The method of manufacturing a 3D NAND memory of claim 7 further comprising the steps of:

forming a plurality of word lines respectively communicating with the word line layers of two core regions on both sides of the division step in the first and second portions of the division step between adjacent two of the core regions.

11. The method of manufacturing a 3D NAND memory as claimed in claim 7, wherein the step of forming a memory structure in the core area further comprises the steps of:

forming channel holes which penetrate through the array arrangement of the stacked structure in the core region;

forming a channel layer in the channel hole.

12. A3D NAND memory, comprising:

a substrate;

a partition step formed in the step area;

first and second portions formed in the partition step between the adjacent two core regions, the first and second portions being staggered with each other in a predetermined direction, and the first and second portions being respectively communicated with the adjacent two core regions;

a memory structure formed in the core region;

13. The 3D NAND memory of claim 12 wherein the first portion and the second portion are staggered in a first direction.

14. The 3D NAND memory of claim 13 further comprising an isolation structure between the first portion and the second portion.

15. The 3D NAND memory of claim 14 wherein the isolation structure comprises:

second trenches extending in opposite directions in a second direction perpendicular to the first direction from both ends of the first trenches;

an isolation material filled in the first trench and the second trench.

16. The 3D NAND memory of claim 12 wherein the storage structure comprises:

the array of the stacked structures penetrates through the core region;

a channel layer formed within the channel hole.

17. The 3D NAND memory of claim 12 further comprising: forming a plurality of word lines in the partition step, the word lines being in communication with the word line layer in the stacked structure.