CN113078163A - Manufacturing method of semiconductor device and semiconductor device - Google Patents
Manufacturing method of semiconductor device and semiconductor device Download PDFInfo
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- CN113078163A CN113078163A CN202110312228.4A CN202110312228A CN113078163A CN 113078163 A CN113078163 A CN 113078163A CN 202110312228 A CN202110312228 A CN 202110312228A CN 113078163 A CN113078163 A CN 113078163A
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
The invention discloses a manufacturing method of a semiconductor device and the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: forming a stack layer on a substrate, the stack layer including a plurality of interlayer sacrificial layers and interlayer insulating layers alternately stacked in a longitudinal direction; forming a dummy trench hole longitudinally penetrating the stack layer; oxidizing the side wall of the virtual channel hole to form an oxide layer; filling a dielectric layer in the virtual channel hole; removing the interlayer sacrificial layer to form a sacrificial gap in the stack layer; a gate layer is formed in the sacrificial gap. The invention can improve the supporting force of the stack layer and avoid collapse after removing the interlayer sacrificial layer.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
In the semiconductor device, the channel Hole includes a storage channel Hole and a Dummy channel Hole (Dummy Channal Hole). In the process of separately manufacturing the storage channel hole and the virtual channel hole, the virtual channel hole is sparsely distributed, and the material filled in the virtual channel hole shrinks after high-temperature treatment, so that after the interlayer sacrificial layer in the stack layer is removed, the collapse is easily caused due to insufficient supporting force of the stack layer.
Disclosure of Invention
The invention provides a manufacturing method of a semiconductor device and the semiconductor device, which can improve the supporting force of a stack layer and avoid collapse after an interlayer sacrificial layer is removed.
The invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
forming a stack layer on a substrate, the stack layer including a plurality of interlayer sacrificial layers and interlayer insulating layers alternately stacked in a longitudinal direction;
forming a dummy trench hole longitudinally penetrating the stack layer;
oxidizing the side wall of the virtual channel hole to form an oxide layer;
filling a dielectric layer in the virtual channel hole;
removing the interlayer sacrificial layer to form a sacrificial gap in the stack layer;
a gate layer is formed in the sacrificial gap.
Further preferably, the step of oxidizing the sidewall of the virtual channel hole to form an oxide layer includes:
and oxidizing the interlayer sacrificial layer exposed on the side wall of the virtual channel hole to form an oxide layer on the surface of the interlayer sacrificial layer on the side wall of the virtual channel hole.
Further preferably, the step of oxidizing the sidewall of the virtual channel hole to form an oxide layer includes:
etching the interlayer sacrificial layer exposed on the side wall of the virtual channel hole to form a groove;
and oxidizing the interlayer sacrificial layer in the groove to form an oxide layer in the groove.
Further preferably, the step of oxidizing the sidewall of the virtual channel hole to form an oxide layer includes:
forming a sacrificial layer on the side wall of the virtual channel hole;
and oxidizing the sacrificial layer to form an oxide layer covering the side wall of the virtual channel hole.
Further preferably, the thickness of the oxide layer is 10 nm.
Preferably, the interlayer sacrificial layer and the sacrificial layer are silicon nitride, and the oxide layer is silicon oxide.
Accordingly, the present invention also provides a semiconductor device comprising:
a substrate;
a stack layer on the substrate, the stack layer including a plurality of gate layers and interlayer insulating layers alternately stacked in a longitudinal direction;
and the virtual channel structure longitudinally penetrates through the stack layer and comprises a dielectric layer and an oxide layer covering at least part of the dielectric layer.
Further preferably, the oxide layer comprises a plurality of sub-oxide layers arranged at intervals in the longitudinal direction;
the multiple sections of sub-oxide layers are arranged in one-to-one correspondence with the multiple gate layers, and each section of sub-oxide layer is positioned between the dielectric layer and the corresponding gate layer so as to cover part of the side wall of the dielectric layer.
Further preferably, the dielectric layer is arranged between any two sections of the sub-oxide layers which are longitudinally adjacent.
Further preferably, one interlayer insulating layer is arranged between any two sections of the sub-oxide layers which are longitudinally adjacent.
Further preferably, the oxide layer completely covers the sidewall of the dielectric layer.
Further preferably, the oxide layer is silicon oxide.
The invention has the beneficial effects that: the side wall of the virtual channel hole is oxidized to form a compact oxidation layer at the side wall of the virtual channel hole, so that after the interlayer sacrificial layer in the stack layer is removed, the support effect of the stack layer is improved through the compact oxidation layer and the medium layer in the virtual channel hole, and the collapse of the stack layer is avoided.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2a to fig. 2e are schematic structural diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention;
fig. 3a to fig. 3d are schematic structural diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the invention;
fig. 4a to fig. 4d are schematic structural diagrams illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 6 is another schematic structural diagram of a semiconductor device according to an embodiment of the present invention;
fig. 7 is a schematic view of another structure of the semiconductor device according to the embodiment of the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in fig. 1, the method for manufacturing a semiconductor device according to the embodiment of the present invention includes steps 101 to 106:
As shown in fig. 2a, a stacked layer 2 is formed on a substrate 1, the stacked layer 2 includes a plurality of interlayer sacrificial layers 22 and interlayer insulating layers 21 alternately stacked in a longitudinal direction, where the longitudinal direction refers to a direction perpendicular to the substrate 1, and the number of stacked layers of the interlayer sacrificial layers 22 and the interlayer insulating layers 21 is not limited, such as 48 layers, 64 layers, and the like. The substrate 1 is a semiconductor substrate, and may be a silicon substrate, for example, or a substrate including another element semiconductor or a compound semiconductor. The interlayer insulating layer 21 includes, but is not limited to, silicon oxide, and the interlayer sacrificial layer 22 includes, but is not limited to, silicon nitride.
And 102, forming a virtual channel hole longitudinally penetrating through the stack layer.
The virtual channel hole refers to a channel hole in which a storage unit is not formed subsequently, and the virtual channel hole is mainly used as a supporting column through the subsequent filling of other film layers. As shown in fig. 2a, a dummy trench hole 4 is formed in the stacked layer 2, and the dummy trench hole 4 longitudinally penetrates the stacked layer 2 and extends into the substrate 1.
A storage channel hole (not shown) is formed in the stacked layer 2 and extends longitudinally through the stacked layer 2 to the inside of the substrate 1, and the storage channel hole is a channel hole through which a memory cell can be formed later. The stack layer 2 may include a core region and a step region, the channel hole formed in the core region is a storage channel hole, and the channel hole formed in the step region is a dummy channel hole.
In the process of separately manufacturing the storage channel hole and the virtual channel hole, an epitaxial layer is formed at the bottom of the storage channel hole, a storage medium layer is formed on the inner surface of the storage channel hole, a bottom through hole is formed in the storage medium layer at the bottom of the storage channel hole, then a channel layer is formed on the surface of the storage medium layer in the storage channel hole and the inner surface of the bottom through hole, and then an insulating layer is filled in the storage channel hole. The storage medium layer includes a charge blocking layer, a charge storage layer and a tunnel layer, that is, the charge blocking layer is formed on the inner surface of the storage channel hole, then the charge storage layer is formed on the surface of the charge blocking layer, and the tunnel layer is formed on the surface of the charge storage layer.
And 103, oxidizing the side wall of the virtual channel hole to form an oxide layer.
Because the distribution of the virtual channel holes is sparse, and the film layer subsequently filled in the virtual channel holes is easy to shrink after high-temperature treatment, the supporting effect of the virtual channel holes is poor, and the stack layer is easy to collapse due to insufficient supporting force after the interlayer sacrificial layer in the stack layer is subsequently removed, the side wall of the virtual channel hole is firstly oxidized before the virtual channel holes are filled, so that a compact oxide layer is formed at the side wall of the virtual channel hole, the supporting effect of the virtual channel hole is improved, and the collapse of the stack layer after the interlayer sacrificial layer in the stack layer is subsequently removed is avoided.
The sidewall of the virtual channel hole can be oxidized in different modes, and different positions of the sidewall of the virtual channel hole can also be oxidized, namely the oxidation layer can be positioned at different positions of the sidewall of the virtual channel hole.
In one embodiment, oxidizing the sidewalls of the virtual channel hole in step 103 to form an oxide layer comprises:
and oxidizing the interlayer sacrificial layer exposed on the side wall of the virtual channel hole to form an oxide layer on the surface of the interlayer sacrificial layer on the side wall of the virtual channel hole.
Because the stack layer includes the interlayer sacrificial layers and the interlayer insulating layers which are alternately stacked In the longitudinal direction, the side wall of the virtual channel hole penetrating through the stack layer exposes the interlayer sacrificial layers and the interlayer insulating layers which are alternately stacked In the longitudinal direction, the interlayer sacrificial layers exposed on the side wall of the virtual channel hole are an Oxidation object, the interlayer sacrificial layers exposed on the side wall of the virtual channel hole can be oxidized by adopting Remote Plasma Oxidation (RPO), In-Situ Steam Generation (ISSG), Furnace Oxidation (burn Oxidation) and other processes, and the interlayer sacrificial layers exposed on the side wall of the virtual channel hole are oxidized to form a compact oxide layer which is attached to the surface of the interlayer sacrificial layer, namely the oxide layer is positioned on the surface of the interlayer sacrificial layer at the side wall of the virtual channel hole. When the interlayer sacrificial layer is silicon nitride, the oxidized interlayer sacrificial layer (i.e., the oxide layer) is silicon oxide. The thickness of the oxidized layer can be controlled by adjusting parameters in the process, such as the oxidation duration and the like, so that the thickness of the oxidized layer can be controlled.
Because the oxide layer is formed on the surface of the interlayer sacrificial layer at the side wall of the virtual channel hole, and the oxide layer is not formed on the surface of the interlayer insulating layer at the side wall of the virtual channel hole, the concavity and convexity of the side wall of the virtual channel hole are uneven (the oxide layer forms a bulge), but the thickness of the oxide layer (the bulge) is extremely small relative to the size (such as the aperture) of the virtual channel hole, so that the filling of the virtual channel hole is not influenced while the supporting effect of the stack layer after the subsequent interlayer sacrificial layer is removed is ensured.
As shown in fig. 2b, the interlayer sacrificial layer 22 exposed on the sidewall of the dummy trench 4 is directly oxidized to form an oxide layer 3 on the surface of the interlayer sacrificial layer 22 at the sidewall of the dummy trench 4.
And 104, filling a dielectric layer in the virtual channel hole.
As shown in fig. 2c, after the oxide layer 3 is formed on the sidewall of the dummy trench 4, the dielectric layer 5 is continuously filled in the dummy trench 4, and since the thickness of the oxide layer 3 is much smaller than the size (e.g., aperture) of the dummy trench, the formation of the oxide layer 3 does not affect the filling effect of the dielectric layer 5. After the dielectric layer 5 is filled, the dielectric layer 5 and the oxide layer 3 provide a supporting function together, and the supporting effect of the stack layer 2 is effectively improved. The material of the dielectric layer 5 includes, but is not limited to, silicon oxide.
Because the interlayer sacrificial layer in the stack layer needs to be replaced by a gate electrode layer, after the storage channel hole and the virtual channel hole are filled with corresponding film layers, a gate line slit longitudinally penetrating through the stack layer is formed, the interlayer sacrificial layer in the stack layer is removed through the gate line slit by adopting a wet etching process, and a sacrificial gap is formed in a region where the interlayer sacrificial layer is removed. Because the dielectric layer and the oxide layer in the virtual channel hole provide a supporting effect together, the supporting effect is improved, and the collapse of the stack layer after the interlayer sacrificial layer is removed is avoided.
As shown in fig. 2d, the interlayer sacrificial layer 22 in the stacked layer 2 is removed through a gate line slit (not shown) to form a sacrificial gap 23 in the stacked layer 2.
And 106, forming a gate layer in the sacrificial gap.
As shown in fig. 2e, a gate layer 24 is formed in the sacrificial gap 23 by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the material of the gate layer 24 includes, but is not limited to, a metal (e.g., tungsten, etc.), doped polysilicon, etc.
In another embodiment, oxidizing the sidewalls of the dummy channel hole in step 103 to form an oxide layer includes:
etching the interlayer sacrificial layer exposed on the side wall of the virtual channel hole to form a groove;
and oxidizing the interlayer sacrificial layer in the groove to form an oxide layer in the groove.
In order to avoid uneven concavity and convexity of the side wall of the virtual channel hole caused by directly oxidizing the interlayer sacrificial layer at the side wall of the virtual channel hole, the interlayer sacrificial layer exposed at the side wall of the virtual channel hole can be etched first, so that a groove is formed between the etched interlayer sacrificial layer and the adjacent interlayer insulating layer, namely the groove is formed on the side wall of the virtual channel hole, the groove wall of the groove is the interlayer insulating layer, and the groove bottom of the groove is the interlayer sacrificial layer. The height of the recess may be set according to the thickness of the oxide layer to be formed.
Then, the interlayer sacrificial layer at the bottom of the groove can be oxidized by adopting the processes of remote plasma oxidation, in-situ water vapor generation, furnace tube oxidation and the like, a compact oxide layer is formed in the groove after the interlayer sacrificial layer at the bottom of the groove is oxidized, the thickness of the oxide layer can be controlled by adjusting parameters in the processes such as oxidation duration and the like, so that the oxide layer is just filled in the groove, the unevenness of the side wall of the virtual channel hole is avoided, and the subsequent filling of the virtual channel hole is not influenced. In addition, the oxide layer is positioned between the interlayer insulating layers, so that the supporting effect of the stack layer after the subsequent interlayer sacrificial layer is removed is further improved.
As shown in fig. 3a, the interlayer sacrificial layer 22 exposed on the sidewall of the dummy trench hole 4 is etched to form a groove 25, the wall of the groove 25 is the interlayer insulating layer 21, and the bottom of the groove 25 is the interlayer sacrificial layer 22. Then, as shown in fig. 3b, the interlayer sacrificial layer 22 at the bottom of the groove 25 is oxidized, the interlayer sacrificial layer 22 is oxidized to form the oxide layer 3, and the oxide layer 3 just fills the groove 25. Then, as shown in fig. 3c, the dummy trench hole 4 is filled with a dielectric layer 5. As shown in fig. 3d, the interlayer sacrificial layer 22 in the stack layer 2 is replaced with a gate layer 24. In this embodiment, the oxide layer 3 and the dielectric layer 5 provide a supporting function together, and the oxide layer 3 is located between the interlayer insulating layers 21, so as to further improve the supporting effect and prevent the collapse of the stack layer 2 when the interlayer sacrificial layer 22 is replaced with the gate layer 24.
In yet another embodiment, the step of oxidizing the sidewalls of the virtual channel hole to form an oxide layer in step 103 includes:
forming a sacrificial layer on the side wall of the virtual channel hole;
and oxidizing the sacrificial layer to form an oxide layer covering the side wall of the virtual channel hole.
And forming a sacrificial layer on the whole side wall of the virtual channel hole, wherein the thickness of the sacrificial layer can be set according to the thickness of the oxide layer required to be formed.
Then, the sacrificial layer in the virtual channel hole can be oxidized by adopting the processes of remote plasma oxidation, in-situ water vapor generation, furnace tube oxidation and the like so as to oxidize the sacrificial layer into an oxide layer. The oxidized thickness of the sacrificial layer can be controlled by adjusting parameters in the process, such as the oxidation time and the like, so that the thickness of the oxide layer is controlled. Preferably, the sacrificial layer is fully oxidized into the oxide layer, that is, after the sacrificial layer is oxidized, the sacrificial layer is no longer on the sidewall of the virtual channel hole, but only the oxide layer is formed on the surface of the interlayer sacrificial layer and the interlayer insulating layer at the sidewall of the virtual channel hole. Preferably, the sacrificial layer is silicon nitride and the oxide layer is silicon oxide.
After the sacrificial layer is completely oxidized, a compact oxide layer is formed on the whole side wall of the virtual channel hole, and the supporting effect of the stack layer after the subsequent interlayer sacrificial layer is removed is further improved.
As shown in fig. 4a, the sacrifice layer 6 is formed on the surface of the interlayer sacrifice layer 22 and the interlayer insulating layer 21 exposed to the side wall of the dummy trench hole 4. Then, as shown in fig. 4b, the sacrificial layer 6 is oxidized to completely oxidize the sacrificial layer 6 into the oxide layer 3, so that a dense oxide layer 3 is formed on the entire sidewall of the dummy channel hole 4. Then, as shown in fig. 4c, the filling of the dielectric layer 5 in the dummy trench hole 4 is continued. As shown in fig. 4d, the interlayer sacrificial layer 22 in the stack layer 2 is replaced with a gate layer 24. In this embodiment, the oxide layer 3 and the dielectric layer 5 provide a supporting function together, and the oxide layer 3 is located on the entire sidewall of the virtual channel hole 4, so as to further improve the supporting effect and prevent the collapse of the stack layer 2 when the interlayer sacrificial layer 22 is replaced with the gate layer 24.
As can be seen from the above, in the manufacturing method of the semiconductor device provided in the embodiment of the present invention, the dense oxide layer 3 is formed on the sidewall of the dummy trench hole 4 by oxidizing the sidewall of the dummy trench hole 4, so that after the interlayer sacrificial layer 22 in the stack layer 2 is removed, the support effect of the stack layer is improved by the dense oxide layer 3 and the dielectric layer 5 in the dummy trench hole 4, and the collapse of the stack layer 2 is avoided.
Correspondingly, the embodiment of the invention also provides a semiconductor device which can be manufactured by adopting the manufacturing method of the semiconductor device in the embodiment.
Fig. 5 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention.
As shown in fig. 5, the present embodiment provides a semiconductor device including a substrate 1, a stack layer 2, and a dummy channel structure 40. The stack layer 2 is located on the substrate 1, and the stack layer 2 includes a plurality of gate layers 24 and interlayer insulating layers 21 alternately stacked in the longitudinal direction. The dummy trench structure 40 longitudinally penetrates through the stack layer 2 and extends into the substrate 1, the dummy trench structure 40 includes an oxide layer 3 and a dielectric layer 5, and the oxide layer 3 covers at least a portion of the sidewall of the dielectric layer 5. The dielectric layer 5, together with the oxide layer 3, provides support to prevent collapse of the stack 2 during replacement of the interlayer sacrificial layer into the gate layer 24.
The semiconductor device may further comprise a memory channel structure (not shown) extending longitudinally through the stacked layers 2 and into the substrate 1. The storage channel structure includes a storage medium layer, a channel layer formed on a surface of the storage medium layer, and an insulating layer formed on a surface of the channel layer, which are not described in detail herein.
In some embodiments, the oxide layer 3 includes a plurality of sub-oxide layers 31 disposed at intervals in a longitudinal direction, the plurality of sub-oxide layers 31 are disposed corresponding to the plurality of gate layers 24, and each sub-oxide layer 31 is located between the dielectric layer 5 and the corresponding gate layer 24 to cover a portion of a sidewall of the dielectric layer 5. Each section of sub-oxide layer 31 is disposed around the dielectric layer 5, and the thickness of each section of sub-oxide layer 31 is the same as that of the corresponding gate layer 24, so that each section of sub-oxide layer 31 is located right between the dielectric layer 5 and the corresponding gate layer 24.
Any two sections of longitudinally adjacent sub-oxide layers 31 may have the dielectric layer 5 therebetween, as shown in fig. 5. Specifically, as shown in fig. 2a to 2e, interlayer sacrificial layers 22 and interlayer insulating layers 21 which are alternately stacked in the longitudinal direction are formed on a substrate 1, then a virtual trench hole 4 which longitudinally penetrates through the stacked layers 2 is formed, the interlayer sacrificial layers 22 exposed in the virtual trench hole 4 are directly oxidized, so that a section of sub-oxide layer 31 is formed on the surface of each interlayer sacrificial layer 22 at the side wall of the virtual trench hole 4, a dielectric layer 5 is filled in the virtual trench hole 4, and the dielectric layer 5 fills the remaining space of the virtual trench hole 4, so that the dielectric layer 5 is arranged between any two adjacent sections of sub-oxide layers 31. The interlayer sacrificial layer 22 is replaced by a gate layer 24, so that each sub-oxide layer 31 is located between the dielectric layer 5 and the corresponding gate layer 24 in the finally obtained semiconductor device.
One interlayer insulating layer 21 may be provided between any two longitudinally adjacent segments of the sub-oxide layer 31, as shown in fig. 6, that is, a gate layer 24 and a sub-oxide layer 31 are provided between any two adjacent interlayer insulating layers 21. Specifically, as shown in fig. 3a to 3d, first, interlayer sacrificial layers 22 and interlayer insulating layers 21 that are alternately stacked in the longitudinal direction are formed on a substrate 1, then a dummy trench hole 4 that penetrates through a stack layer 2 in the longitudinal direction is formed, each interlayer sacrificial layer 22 exposed in the dummy trench hole 4 is etched to form a groove 25 at each interlayer sacrificial layer 22, then the interlayer sacrificial layer 22 in each groove 25 is oxidized to form a sub-oxide layer 31 in each groove 25, a dielectric layer 5 is filled in the dummy trench hole 4, the dummy trench hole 4 is filled with the dielectric layer 5, and then the remaining interlayer sacrificial layers 22 are replaced with a gate layer 24, so that each sub-oxide layer 31 is located between the dielectric layer 5 and the gate layer 24 corresponding to the dielectric layer in the finally obtained semiconductor device.
In some embodiments, the oxide layer 3 completely covers the sidewalls of the dielectric layer 5, as shown in fig. 7. Specifically, as shown in fig. 4a to 4d, first, interlayer sacrificial layers 22 and interlayer insulating layers 21 that are alternately stacked in the longitudinal direction are formed on a substrate 1, then a dummy trench 4 that penetrates through a stack layer 2 in the longitudinal direction is formed, a sacrificial layer 6 is formed on the entire sidewall of the dummy trench 4, then the sacrificial layer 6 is completely oxidized to an oxide layer 3, a dielectric layer 5 is filled in the dummy trench 4, and then the interlayer sacrificial layer 22 is replaced with a gate layer 24, so that in the finally obtained semiconductor device, the oxide layer 3 surrounds the dielectric layer 5 and completely covers the entire sidewall of the dielectric layer 5.
In some embodiments, the oxide layer 3 is silicon oxide.
The semiconductor device provided by the embodiment of the invention can improve the supporting effect of the stack layer 2 through the compact oxide layer 3 and the dielectric layer 5 when the gate layer 24 in the stack layer 2 is replaced by forming the virtual channel structure longitudinally penetrating through the stack layer, wherein the virtual channel structure comprises the dielectric layer 5 and the oxide layer 3 covering at least part of the dielectric layer 5, so that the collapse of the stack layer 2 is avoided.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (11)
1. A method for manufacturing a semiconductor device, comprising:
forming a stack layer on a substrate, the stack layer including a plurality of interlayer sacrificial layers and interlayer insulating layers alternately stacked in a longitudinal direction;
forming a dummy trench hole longitudinally penetrating the stack layer;
oxidizing the side wall of the virtual channel hole to form an oxide layer;
filling a dielectric layer in the virtual channel hole;
removing the interlayer sacrificial layer to form a sacrificial gap in the stack layer;
a gate layer is formed in the sacrificial gap.
2. The method of claim 1, wherein the step of oxidizing the sidewalls of the dummy trench hole to form an oxide layer comprises:
and oxidizing the interlayer sacrificial layer exposed on the side wall of the virtual channel hole to form the oxide layer on the surface of the interlayer sacrificial layer on the side wall of the virtual channel hole.
3. The method of claim 1, wherein the step of oxidizing the sidewalls of the dummy trench hole to form an oxide layer comprises:
etching the interlayer sacrificial layer exposed on the side wall of the virtual channel hole to form a groove;
and oxidizing the interlayer sacrificial layer in the groove to form the oxide layer in the groove.
4. The method of claim 1, wherein the step of oxidizing the sidewalls of the dummy trench hole to form an oxide layer comprises:
forming a sacrificial layer on the side wall of the virtual channel hole;
and oxidizing the sacrificial layer to form the oxide layer covering the side wall of the virtual channel hole.
5. The method according to claim 4, wherein the interlayer sacrificial layer and the sacrificial layer are each silicon nitride, and the oxide layer is silicon oxide.
6. A semiconductor device, comprising:
a substrate;
a stack layer on the substrate, the stack layer including a plurality of gate layers and interlayer insulating layers alternately stacked in a longitudinal direction;
and the virtual channel structure longitudinally penetrates through the stack layer and comprises a dielectric layer and an oxide layer covering at least part of the dielectric layer.
7. The semiconductor device according to claim 6, wherein the oxide layer comprises a plurality of segments of sub-oxide layers arranged at intervals in a longitudinal direction;
the multiple sections of sub-oxide layers are arranged in one-to-one correspondence with the multiple gate layers, and each section of sub-oxide layer is positioned between the dielectric layer and the corresponding gate layer so as to cover part of the side wall of the dielectric layer.
8. The semiconductor device according to claim 7, wherein the dielectric layer is provided between any two longitudinally adjacent segments of the sub-oxide layer.
9. The semiconductor device according to claim 7, wherein one interlayer insulating layer is provided between any two longitudinally adjacent segments of the sub-oxide layers.
10. The semiconductor device of claim 6, wherein the oxide layer completely covers sidewalls of the dielectric layer.
11. The semiconductor device according to claim 9, wherein the oxide layer is silicon oxide.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10559566B1 (en) * | 2018-09-17 | 2020-02-11 | International Business Machines Corporation | Reduction of multi-threshold voltage patterning damage in nanosheet device structure |
| CN112310105A (en) * | 2020-10-30 | 2021-02-02 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN112420716A (en) * | 2020-11-17 | 2021-02-26 | 长江存储科技有限责任公司 | Semiconductor device and preparation method thereof |
| CN112490250A (en) * | 2020-11-26 | 2021-03-12 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN112820735A (en) * | 2021-01-28 | 2021-05-18 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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2021
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10559566B1 (en) * | 2018-09-17 | 2020-02-11 | International Business Machines Corporation | Reduction of multi-threshold voltage patterning damage in nanosheet device structure |
| CN112310105A (en) * | 2020-10-30 | 2021-02-02 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN112420716A (en) * | 2020-11-17 | 2021-02-26 | 长江存储科技有限责任公司 | Semiconductor device and preparation method thereof |
| CN112490250A (en) * | 2020-11-26 | 2021-03-12 | 长江存储科技有限责任公司 | Manufacturing method of semiconductor device and semiconductor device |
| CN112820735A (en) * | 2021-01-28 | 2021-05-18 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
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