CN103296049B - Phase transition storage and manufacture method thereof - Google Patents
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- CN103296049B CN103296049B CN201210053872.5A CN201210053872A CN103296049B CN 103296049 B CN103296049 B CN 103296049B CN 201210053872 A CN201210053872 A CN 201210053872A CN 103296049 B CN103296049 B CN 103296049B
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Abstract
The invention provides a kind of phase transition storage and manufacture method thereof, described phase transition storage comprises: substrate, be positioned at the memory cell array on substrate and circuit unit, described circuit unit is positioned at around described memory cell array, described phase transition storage also comprise between described memory cell array and described circuit unit, around the groove isolation construction of described memory cell array.The manufacture method of described phase transition storage, comprising: provide substrate; Memory cell region on substrate forms memory cell array; Substrate is formed the groove isolation construction around described memory cell array; On substrate, the peripheral region of groove isolation construction forms circuit unit.Described groove isolation construction can make to insulate between described memory cell array and described circuit unit, can reduce the parasitic diode between memory cell array and circuit unit, to improve the performance of phase transition storage.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly relate to a kind of phase transition storage and manufacture method thereof.
Background technology
Phase transition storage (PhaseChangeMemory, PCM) as a kind of emerging nonvolatile storage technologies, relative to flash memory, all there is larger superiority in all many-sides such as read or write speed, read-write number of times, data hold time, cellar area, many-valued realizations.
A kind of phase transition storage is disclosed in US Patent No. 6531373.With reference to figure 1, show the structural representation of phase transition storage one embodiment in described United States Patent (USP), described phase transition storage is positioned at the space formed by X-axis, Y-axis, Z axis pairwise orthogonal.Particularly, described phase transition storage comprises substrate 001, and described substrate 001 surface is formed with the wordline 105 of some numbers, and the wordline 105 of described some numbers is arranged along X-direction, carries out electric isolution between wordline and the wordline be adjacent by insulating material.Every bar wordline 105 all extends along Y direction.
Wherein along in Z-direction, described every bar wordline 105 surface is all formed with the memory cell 101 of some numbers, and the memory cell 101 of described some numbers presses array arrangement, each described memory cell 101 includes the phase change resistor 102 and gate diode 103 that are connected in series.
Continue with reference to figure 1, be positioned at described memory cell 101 surface and be formed with bit line 104, described bit line 104 is arranged along Y direction, and every bit lines 104 extends along X-axis, the memory cell 101 being positioned at different wordline 105 connected, the memory cell 101 be positioned in every bar wordline 105 connects by every bit lines 104 respectively.
Continue with reference to figure 1, in the plane that X-axis and Z axis are formed, described wordline and be adjacent wordline, is formed with deep trench isolation region 106, is filled with isolated material (not shown) in described deep trench isolation region 106 between described memory cell and the memory cell be adjacent.Described deep trench isolation region 106 by wordline and wordline, memory device and with its altogether memory device of wordline isolate.In substrate 001 described in described deep trench isolation region 106 embedded part.
Continue with reference to figure 1, in the plane that Y-axis and Z axis are formed, described bit line and the bit line be adjacent, be formed with shallow plough groove isolation area 107, be filled with isolated material (not shown) in described shallow plough groove isolation area 107 between described memory cell and the memory cell be adjacent.Described shallow plough groove isolation area 107 is by bit line and bit line, and the memory device of memory device and wordline common with it is isolated.
Continue with reference to figure 1, aa ' direction and bb ' direction along bit line 104 bearing of trend, cc ' direction is along wordline bearing of trend.Wherein, be along described shallow plough groove isolation area 107 gained cutaway view along described bb ' direction gained cutaway view; Be along bit line 104 gained cutaway view along described aa ' direction gained cutaway view.
Figure 2 shows that the schematic equivalent circuit of Fig. 1, in each memory cell 101 of described phase transition storage, all include the phase change resistor 102 and gate diode 103 that are connected in series.Composition graphs 1 and Fig. 2, when carrying out write operation to described phase transition storage, larger electrical potential difference is defined corresponding in bit line 104 and the wordline 105 of a certain memory cell 101 to be selected, described electrical potential difference makes gate diode 103 forward conduction, and then larger reset current is formed on phase change resistor 102, said write electric current makes phase change resistor 102 state change, and data are also able to record.
In the phase transition storage of prior art, be also provided with the circuit be connected with described gate diode 103 in the neighboring area of memory cell 101, be used as the switch controlling gate diode 103.In conjunction with reference to figure 3, show the side schematic view of another embodiment of prior art phase transition storage, present embodiment illustrates the structure of memory cell region I and circuit region II intersection in phase transition storage.As shown in Figure 3, as memory cell switch is P-type crystal pipe, comprises P type substrate 110, is positioned at the N-type well region 111 in P type substrate 110, be positioned at the grid structure 113 in N-type well region 111, and be positioned at the P type doped region 112 of N-type well region 111 below grid structure 113.Described gate diode 103 comprises N-type doped layer 109, the P type doped layer 108 be positioned on N-type doped layer 109.At memory cell region I and circuit region II intersection, P type doped region 112 and the N-type doped layer 109 in described gate diode 103 of described transistor, in described gate diode 103, N-type doped layer 109 form respectively parasitic diode with the P type substrate 110 of transistor, and described parasitic diode can affect the performance of phase transition storage.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of phase transition storage and the manufacture method thereof that reduce parasitic diode.
In order to solve the problem, the invention provides a kind of phase transition storage, comprise: substrate, be positioned at the memory cell array on substrate and circuit unit, described circuit unit is positioned at around described memory cell array, described phase transition storage also comprise between described memory cell array and described circuit unit, around the groove isolation construction of described memory cell array.
Alternatively, described memory cell array comprises multiple parallel shallow plough groove isolation area, deep trench isolation region that multiple and described shallow plough groove isolation area is vertical, and described deep trench isolation region comprises: be formed at the groove in substrate; Be covered in the laying in described trench bottom surfaces and sidewall surfaces; Be filled in the first packed layer in described groove; Be covered in the barrier layer on described first packed layer; Be filled in described groove, the second packed layer be positioned on described barrier layer.
Alternatively, described groove isolation construction is the enclosed construction around described memory cell array.
Alternatively, described groove isolation construction is the segmentation structure around described memory cell array.
Alternatively, described groove isolation construction is identical with described deep trench isolation region.
Alternatively, the material of described laying is silica, and described first packed layer is polysilicon, and described barrier layer is silica, and described second packed layer is silica.
Correspondingly, the present invention also provides a kind of manufacture method of phase transition storage, comprising: provide substrate; Memory cell region on substrate forms memory cell array; Substrate is formed the groove isolation construction around described memory cell array; On substrate, the peripheral region of groove isolation construction forms circuit unit.
Alternatively, step substrate forming memory cell array comprises: form multiple parallel deep trench isolation region, form the vertical shallow plough groove isolation area of multiple and described deep trench isolation region; The step forming groove isolation construction comprises: formed in memory cell region in the process of deep trench isolation region, form the groove isolation construction identical with described deep trench isolation region.
Alternatively, formed in memory cell region in the process of deep trench isolation region, the step forming the groove isolation construction identical with described deep trench isolation region comprises: on substrate, form well region, epitaxial loayer successively; Well region, epitaxial loayer described in patterning, form multiple first deep trench arranged in parallel and the second deep trench around described memory cell region in memory cell region; All laying is covered in the lower surface of described first deep trench and the second deep trench and sidewall surfaces; In described first deep trench and the second deep trench, fill the first material, form the first packed layer; Described first packed layer forms barrier layer; Barrier layer in described first deep trench and the second deep trench is continued filling second material, form the second packed layer.
Alternatively, the material of described laying is silica, and described first material is polysilicon, and the material on described barrier layer is silica, and described second material is silica.
Compared with prior art, the present invention has the following advantages:
1. groove isolation construction described in can make to insulate between described memory cell array and described circuit unit, can avoid forming parasitic diode between memory cell array and circuit unit, to improve the performance of phase transition storage.
2., in phase transition storage manufacture method, described groove isolation construction can be formed in the process forming memory cell array simultaneously, not increase processing step, thus simplify manufacture method, do not increase material, thus provide cost savings.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of prior art phase transition storage one embodiment;
Fig. 2 is the schematic equivalent circuit of phase transition storage shown in Fig. 1;
Fig. 3 is the schematic diagram of another embodiment of prior art phase transition storage;
Fig. 4 is the schematic top plan view of phase transition storage one embodiment of the present invention;
Fig. 5 is the side schematic view of phase transition storage shown in Fig. 4;
Fig. 6 is the schematic flow sheet of phase transition storage manufacture method one execution mode of the present invention;
Fig. 7 is the schematic flow sheet of phase transition storage manufacture method one embodiment of the present invention.
Embodiment
Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, and when describing the embodiment of the present invention in detail, for ease of illustrating, described schematic diagram is example, and it should not limit the scope of protection of the invention at this.
In order to solve the problem of prior art, the invention provides a kind of phase transition storage, comprise: substrate, be positioned at the memory cell array on substrate and circuit unit, described circuit unit is positioned at around described memory cell array, described phase transition storage also comprise between described memory cell array and described circuit unit, around the groove isolation construction of described memory cell array.Described groove isolation construction can make to insulate between described memory cell array and described circuit unit, can avoid forming parasitic diode between memory cell array and circuit unit, and then improve the performance of phase transition storage.
Below in conjunction with specific embodiment, technical scheme of the present invention is described further.
With reference to figure 4, show the schematic top plan view of phase transition storage one embodiment of the present invention.It should be noted that only the right side of memory cell region 1 is provided with circuit unit in figure 4 in order to accompanying drawing is succinct, clear in the present embodiment, in side circuit, memory cell region 1 surrounding may arrange circuit unit.
As shown in Figure 4, described phase transition storage comprises substrate 210, be arranged in the memory cell array of memory cell region 1 on substrate 210, be positioned at circuit unit region 2 around memory cell region 1, wherein,
Described memory cell array comprises multiple deep trench isolation region 206 in X direction, described deep trench isolation region 206 is isolated between wordline and wordline for making, described memory cell array also comprises multiple shallow plough groove isolation area (not shown) along Y-direction, isolates between bit line and bit line for making.Substrate 210 is divided into the latticed district of mutually insulated by described multiple deep trench isolation region 206 in X direction and multiple shallow plough groove isolation area along Y-direction, a memory cell that each grid is namely corresponding, thus forms memory cell array.
In the present embodiment, be arranged in the circuit unit in circuit unit region 2 for providing switching voltage to memory cell.Particularly, described circuit unit comprises grid 213, is positioned at the doped region 212 of grid 213 both sides.
Described phase transition storage also comprises between described memory cell array and described circuit unit, around the groove isolation construction 214 of described memory cell array, described groove isolation construction 214 is embedded in substrate 210, can avoid the formation of parasitic diode.
In the present embodiment, described groove isolation construction 214 is enclosed " mouth " type loop configuration.But the present invention does not limit this, described groove isolation construction 214 is between described memory cell array and described circuit unit, the arrangement situation of combined circuit unit around memory cell array, described groove isolation construction 214 can also be arranged to the structure of segmented, such as: described groove isolation construction 214 can be made up of 4 strip groove isolation structures around described memory cell array.
In conjunction with reference to figure 5, show the side schematic view of phase transition storage shown in Fig. 4.As shown in Figure 5, described phase transition storage comprises substrate 210, is formed at the memory cell array on substrate 210 in memory cell region 1 and is arranged in the circuit unit in circuit unit region 2.In the present embodiment, the substrate that described substrate 210 adulterates for P type.
Particularly, described memory cell array comprises the well region 219 be formed at successively on substrate 210, gate diode 203, wherein, described gate diode 203 comprises N-type doped layer 209, the P type doped layer 208 be positioned on N-type doped layer 209, and described cells of memory arrays also comprises and is positioned at phase-change material (not shown) coupled on gate diode 203.
Described circuit unit comprises P-type crystal pipe, comprises the substrate 210 of P type, the N-type well region 211 be formed on substrate 210, the grid structure 213 be arranged in N-type well region 211, is positioned at the P type doped region 212 that grid structure 213 both sides are formed at N-type well region 211.
In the present embodiment, groove isolation construction 214 is between the gate diode 203 and the P type doped region 212 of P-type crystal pipe of memory cell array, and described groove isolation construction 214 bottom is positioned at the below of the N-type doped layer 209 of described gate diode 203, also be positioned at the below of the P type doped region 212 of described P-type crystal pipe, therefore can avoid between the N-type doped layer 209 and circuit unit P type doped region 212 of gate diode 203, between the N-type doped layer 209 of gate diode 203 and the substrate 210 of P type, produce parasitic diode.
Particularly, described groove isolation construction 214 is identical with the structure of the deep trench isolation region 206 in described memory cell array, same process can be adopted like this, generate described groove isolation construction 214 and described deep trench isolation region 206 simultaneously, thus the processing step manufacturing phase transition storage can not be increased, because this simplify processing procedure.
As shown in Figure 5, described groove isolation construction 214 includes with described deep trench isolation region 206: be formed at the groove in substrate 210, be covered in the laying 215 in described trench bottom surfaces and sidewall surfaces, be filled in the first packed layer 216 in described groove, be covered in the barrier layer 217 on described first packed layer 216; Be filled in described groove, the second packed layer 218 be positioned on described barrier layer 217.
Wherein, in described groove embedded part substrate 210, particularly, the bottom of described groove is positioned at the below of the N-type doped layer 209 of described gate diode 203, described groove is also positioned at the below of the P type doped region 212 of described P-type crystal pipe, thus make between N-type doped layer 209 and P type doped region 212, effectively insulation and isolation between the substrate 210 of the P type doping in N-type doped layer 209 and circuit unit region 2, to avoid the formation of parasitic diode.
Described laying 215 is for realizing the insulation between adjacent conducting diode 203, and the material of described laying 215 is silica.
Described first packed layer 216 is the good polysilicon of fillibility.
Described barrier layer 217 is for the protection of described first packed layer 216, and avoid it destroyed in subsequent etching processes, described barrier layer 217 is also for the protection of sidewall.Barrier layer 217 described in the present embodiment is directly carry out being oxidized the silica formed to described first packed layer 216.
Described second packed layer 218 is for realizing the insulation between memory cell, and in the present embodiment, described second packed layer 218 is the good silica material of fillibility.
In the present embodiment, the groove isolation construction 214 identical with deep trench isolation region 206 structure has good insulation property, thus make between N-type doped layer 209 and P type doped region 212, isolation of effectively insulating between the substrate 210 of the P type doping in N-type doped layer 209 and circuit unit region 2, avoid the formation of parasitic diode.
Correspondingly, the present invention also provides a kind of manufacture method of phase transition storage, and with reference to figure 6, show the schematic flow sheet of phase transition storage manufacture method one execution mode of the present invention, described phase transition storage manufacture method roughly comprises the following steps:
Step S1, provides substrate;
Step S2, the memory cell region on substrate forms memory cell array;
Step S3, substrate is formed the groove isolation construction around described memory cell array;
Step S4, on substrate, the peripheral region of groove isolation construction forms circuit unit.
Below in conjunction with specific embodiment, the technical scheme of phase transition storage manufacture method of the present invention is described further.
Perform step S1, provide substrate, substrate described in the present embodiment is the silicon substrate of P type doping.
Continue with reference to figure 5, perform step S2 and S3, the step that substrate is formed memory cell array comprises: form multiple parallel deep trench isolation region 206, form the vertical shallow plough groove isolation area (not shown) of multiple and described deep trench isolation region 206.
In the present embodiment, formed in memory cell region in the process of deep trench isolation region 206, form the groove isolation construction 214 identical with described deep trench isolation region 206.Described herein and described deep trench isolation region 206 is identical refers to that groove isolation construction 214 is identical with the cross-sectional openings of deep trench isolation region 206 and filler is identical, and identical technique can be adopted like this to form described groove isolation construction 214 and deep trench isolation region 206 simultaneously.
It should be noted that, before formation deep trench isolation region 206 and groove isolation construction 214, well region 219, epitaxial loayer need be formed successively on substrate.Particularly, ion doping is carried out to silicon substrate and forms described well region 219, afterwards, well region forms the epitaxial loayer of silicon materials.
As shown in Figure 7, formed in memory cell region in the process of deep trench isolation region, the step forming the groove isolation construction identical with described deep trench isolation region roughly comprises step by step following:
Step S11, patterning well region, epitaxial loayer, form multiple first deep trench arranged in parallel and the second deep trench around memory cell region in memory cell region;
Step S12, all covers laying in the lower surface of described first deep trench and the second deep trench and sidewall surfaces;
Step S13, fills the first material, forms the first packed layer in described first deep trench and the second deep trench;
Step S14, described first packed layer forms barrier layer;
Step S15, the barrier layer in described first deep trench and the second deep trench is continued filling second material, forms the second packed layer.
Perform step S11, form hard mask graph on said epitaxial layer there, be mask patterning described epitaxial loayer, well region and section substrate with hard mask graph, the first deep trench is formed in memory cell region, form the second deep trench around described memory cell region simultaneously, such as, described second deep trench is " mouth " type groove around described memory cell region.
Described first deep trench and the second deep trench adopt identical technique to be formed, and the cross-sectional openings of described first deep trench and the second deep trench is measure-alike.Described first deep trench is also identical with the degree of depth of the second deep trench, and particularly, described first deep trench and the second deep trench at least exceed the bottom of well region, are embedded in described substrate interior.
Perform step S12, in the present embodiment, the material of described laying is silica, concrete, can form described laying by the mode be oxidized lower surface and the sidewall surfaces of described first deep trench and the second deep trench.
Perform step S13, because polysilicon has good fillibility and excellent compactness, in the present embodiment, described first material is polysilicon, to form the first packed layer of polycrystalline silicon material.
Perform step S14, the material on described barrier layer is silica, and the mode being oxidized described first packed layer can be adopted to form described barrier layer.
Perform step S15, depositing second material on described barrier layer, until fill up deep trench, described second material can make to insulate between different memory cell.In the present embodiment, described second material is the good silica material of fillibility.
Follow-up also comprising removes the steps such as unnecessary silica material by flatening process, does not same as the prior artly repeat them here, to which form groove isolation construction.
Follow-up also comprising forms shallow plough groove isolation area step by step, does not same as the prior artly repeat them here.
Perform step S4, on substrate, the peripheral region of groove isolation construction forms circuit unit.It should be noted that, the process forming circuit unit is carried out with the process forming described memory cell array simultaneously, and the technique forming circuit unit is same as the prior art, does not repeat them here.
The phase transition storage that phase transition storage manufacture method of the present invention is formed comprises the groove isolation construction for buffer circuit unit and memory cell, can avoid the formation of parasitic diode.Phase transition storage manufacture method of the present invention can form described groove isolation construction in the process forming memory cell array simultaneously, does not increase processing step, thus simplifies manufacture method, do not increase material, thus provide cost savings.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (2)
1. a manufacture method for phase transition storage, is characterized in that, comprising:
Substrate is provided;
Memory cell region on substrate forms memory cell array, and described memory cell array comprises multiple parallel shallow plough groove isolation area and the vertical deep trench isolation region of multiple and described shallow plough groove isolation area;
Substrate is formed the groove isolation construction around described memory cell array;
On substrate, the peripheral region of groove isolation construction forms circuit unit;
It is characterized in that, described deep trench isolation region is identical with described groove isolation construction, and formed in memory cell region in the process of deep trench isolation region, the step forming the groove isolation construction identical with described deep trench isolation region comprises:
Substrate forms well region, epitaxial loayer successively;
Well region, epitaxial loayer described in patterning, form multiple first deep trench arranged in parallel and the second deep trench around described memory cell region in memory cell region;
All laying is covered in the lower surface of described first deep trench and the second deep trench and sidewall surfaces;
In described first deep trench and the second deep trench, fill the first material, form the first packed layer;
Described first packed layer forms barrier layer;
Barrier layer in described first deep trench and the second deep trench is continued filling second material, form the second packed layer.
2. the manufacture method of phase transition storage as claimed in claim 1, it is characterized in that, the material of described laying is silica, and described first material is polysilicon, and the material on described barrier layer is silica, and described second material is silica.
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| CN1505132A (en) * | 2002-12-05 | 2004-06-16 | 台湾积体电路制造股份有限公司 | Process for making shallow slot and deep slot isolation arrangement |
| CN101140896A (en) * | 2006-09-08 | 2008-03-12 | 上海华虹Nec电子有限公司 | Method for manufacturing semi-conductor shallow ridges and deep groove |
| CN101882602A (en) * | 2009-05-08 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of phase-changing random access memory |
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| US6534781B2 (en) * | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
| KR20110135285A (en) * | 2010-06-10 | 2011-12-16 | 삼성전자주식회사 | Methods for fabricating phase change memory devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1505132A (en) * | 2002-12-05 | 2004-06-16 | 台湾积体电路制造股份有限公司 | Process for making shallow slot and deep slot isolation arrangement |
| CN101140896A (en) * | 2006-09-08 | 2008-03-12 | 上海华虹Nec电子有限公司 | Method for manufacturing semi-conductor shallow ridges and deep groove |
| CN101882602A (en) * | 2009-05-08 | 2010-11-10 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of phase-changing random access memory |
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