CN102262350A - Verification method of exposure program of exposure machine and mask used therewith - Google Patents
Verification method of exposure program of exposure machine and mask used therewith Download PDFInfo
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- CN102262350A CN102262350A CN2010101884020A CN201010188402A CN102262350A CN 102262350 A CN102262350 A CN 102262350A CN 2010101884020 A CN2010101884020 A CN 2010101884020A CN 201010188402 A CN201010188402 A CN 201010188402A CN 102262350 A CN102262350 A CN 102262350A
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Abstract
The invention discloses a verification method of exposure program of exposure machine and a mask used therewith. A chip coated with a photo-etching glue line is provided and a mask is provided. The mask comprises a substrate having a multilevel layer IC pattern and a verification pattern. The multilevel layer IC pattern at least comprises a first level layer IC pattern and a second level layer IC pattern. The verification pattern comprises at least a first mother pattern and a first sub-pattern which are respectively arranged at a first edge of the first level layer IC pattern and the outer edge of a second edge. The first edge and the second edge are opposite. The first mother pattern and the first sub-pattern are different. The first level layer IC pattern, the first mother pattern and the first sub-pattern are in correspondence with an exposure unit region. The exposure program using the mask comprises following steps of transferring the exposure unit region to a first position of the chip, transferring the exposure unit region to a second position adjacent to the first position. The opposite position of the first sub-pattern on the first position and the first mother pattern on the second position is related to the correct or the wrong of the exposure program.
Description
Technical field
The invention relates to the verification method of exposure program of exposure machine and the mask of use thereof, particularly relevant for the verification method of the exposure program of the multistage layer of single mask of step-by-step exposure machine integrated circuit pattern and the mask of use thereof.
Background technology
(integrated circuit, IC) in the technology, the frequency of utilization of photoetching technique is frequent and for influencing the key factor of the final yield of product in SIC (semiconductor integrated circuit).Photoetching technique mainly be with the IC pattern transfer on the mask to chip.The IC pattern that is transferred to each grade layer on the chip need be aligned with each other, otherwise the IC pattern of other grade of misalignment layer will cause the final yield of product to reduce significantly as long as the IC pattern offset of a level layer is arranged, and is serious even can scrap.And whether the exposure program of exposure machine is errorless and accurate, is decision IC pattern transfer result's a very important factor.
Because cost an arm and a leg (making of a general IC need be used 18～23 masks) of mask, so semiconductor factory is actively wished invariably and can be reduced the cost of technology from the use amount that reduces mask.Therefore, present also someone uses the mask with multistage layer IC pattern to reach this benefit.What is called has single mask that the mask of multistage layer IC pattern refers to, and it has the integrated circuit pattern of a plurality of not peer layers (at least two level layers) simultaneously.Yet the mask that the step-by-step exposure machine utilization has multistage layer IC pattern carries out the exposure program that exposure technology must be used complexity, and complicated exposure program need could accurately be judged its correctness through proof procedure numerous and diverse and consuming time.
Summary of the invention
In view of this, fundamental purpose of the present invention provides a kind of verification method of exposure program of exposure machine and the mask of use thereof, can make the checking cost of exposure program of exposure machine low, fast and precisely.
According to purpose of the present invention, a kind of mask is proposed.The substrate of mask comprises multistage layer IC pattern and checking pattern.Multistage layer IC pattern comprises first order layer IC pattern and second level layer IC pattern at least.The checking pattern comprises at least the first supergraph sample and first sub-pattern, is separately positioned on first edge of first order layer IC pattern and the outside at second edge.First edge is relative with second edge.The first supergraph sample is different with first sub-pattern.
According to purpose of the present invention, a kind of verification method of exposure program of exposure machine is proposed also.The chip that is coated with photoresist layer is provided and mask is provided.Mask comprises a substrate, and substrate has multistage layer IC pattern and checking pattern.Multistage layer IC pattern comprises first order layer IC pattern and second level layer IC pattern at least.The checking pattern comprises at least the first supergraph sample and first sub-pattern, is separately positioned on first edge of first order layer IC pattern and the outside at second edge.First edge is relative with second edge.The first supergraph sample is different with first sub-pattern.First order floor IC pattern, the first supergraph sample and first sub-pattern correspond to a langley district.Use mask to carry out exposure program, comprise the langley district is transferred on the primary importance of chip, and then the langley district is transferred on the second place of contiguous primary importance of chip.The relative position of the first supergraph sample on first sub-pattern on the primary importance and the second place is relevant with the correctness of exposure program.
The present invention has following beneficial effect: because embodiments of the invention only need use a slice chip and carry out the exposure program of a level layer, can produce on chip is enough to whether executable checking pattern of determining program, and therefore the cost of checking is low and quick.In addition, chip need not experience repeated exposure, so do not have the aberration that produces because of multiexposure, multiple exposure or lose burnt and have influence on the problem of the accuracy of checking.In an embodiment of the present invention, the position relative relation that only need observe supergraph sample local on the chip and sub-pattern can be judged the enforceability of exposure program exactly, and needn't observe supergraph sample and sub-pattern all on the entire chip, therefore judge that the time of required cost is few.Therefore, compared to the existing way of Fig. 1 and Fig. 2, the verification method of the exposure program of exposure machine of the present invention have cost low, can be fast and the advantage of checking accurately.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Description of drawings
Fig. 1 is for having the mask of multistage layer IC pattern in the prior art that the inventor knew.
Fig. 2 has the chip that shifts the IC pattern that comes from mask.
Fig. 3 A is the mask of the first embodiment of the present invention.
Fig. 3 B is the mask of the second embodiment of the present invention.
Fig. 4 A is that having from mask of an embodiment shifted the next checking pattern and the chip of IC pattern.
Fig. 4 B is that having from mask of an embodiment shifted the next checking pattern and the chip of IC pattern.
Fig. 5 A shows the enlarged drawing that is transferred to the checking pattern on the chip of an embodiment.
Fig. 5 B shows the enlarged drawing that is transferred to the checking pattern on the chip of an embodiment.
Fig. 6 A shows the enlarged drawing that is transferred to the checking pattern on the chip of an embodiment.
Fig. 6 B shows the enlarged drawing that is transferred to the checking pattern on the chip of an embodiment.
[main element symbol description]
1A, 1B: when level layer IC pattern
2A, 2B, 3A, 3B, 4A, 4B: other grade layer IC pattern
5,300,302: mask
50,50 ': substrate
6A, 6B, 6C, 6D, 60: chip
10: first order layer IC pattern
70: second level layer IC pattern
80: third level layer IC pattern
90: fourth stage layer IC pattern
100: Cutting Road
110A, 110B, 110C: first order layer IC pattern
20 ', 20 ", 120A ', 120A ", 120B ', 120B ", 120C ', 120C ": the supergraph sample
21 ', 21 ", 121A ', 121A ", 121B ', 121B ", 121C ', 121C ": sub-pattern
Embodiment
The verification method of the mask that below illustrates the present inventor earlier and known and the exposure program of step-by-step exposure machine.The problem that is found in the mask known by the inventor and the verification method then can be described, and the verification method of the exposure program of mask of developing for the improvement problem and exposure machine.
Fig. 1 is for having the mask of multistage layer IC pattern in the prior art that the inventor knew.Fig. 2 shows the required chip that uses of checking exposure program that the inventor knows, has on the chip from mask to shift the IC pattern of coming.Please refer to Fig. 1, the substrate of mask 5 comprises as level layer (current layer) IC pattern 1A and other grade layer IC pattern 2A, 3A and 4A.Please refer to Fig. 2, the verification method of the exposure program of working as the level layer of step-by-step exposure machine is going up to form as a level layer IC pattern 1B when a level layer IC pattern 1A is transferred to chip 6A, 6B, 6C and 6D mask 5.Other grade layer IC pattern 2A, 3A and 4A with mask 5 is transferred to respectively on chip 6B, 6C and the 6D then, to work as other grade of level layer IC pattern 1B superimposed layer layer IC pattern 2B, 3B and a 4B.For asking simplification, Fig. 2 only shows IC pattern 1B, 2B, 3B and a 4B among every single chip 6A, 6B, 6C and the 6D.Yet after the exposure program that finishes once complete each grade layer, the IC pattern of each grade layer can be covered with on chip in fact.Then, on the detection chip 6A as a level layer IC pattern 1B, and work as grade correctness of layer exposure program when level layer IC pattern 1B judges with 4B alignment case each other with other grade layer IC pattern 2B, 3B on detection chip 6B, 6C and the 6D.
This verification method need use four chips, and to carry out step of exposure seven times, and each exposure needs 20 minutes at least, seven exposures must be spent at least 140 minutes, this also not very covers the switching time of exposing other grade layer IC pattern when level layer IC pattern, and is consuming time and uneconomical.And chip 6A, 6B, 6C and 6D that the IC pattern transfer is finished all need to carry out comprehensive observation, observe entire chip 6A and go up all as level layer IC pattern 1B, and observe entire chip 6A, 6B, 6C and 6D and go up all have or not skew to each other as level layer IC pattern 1B and other grade layer IC pattern 2B, 3B and 4B situation, could judge enforceability when level layer exposure program, very consuming time.In addition, chip is easy to generate aberration after repeated exposure, and this can influence the judgement of pattern lamination, and reduces the accuracy of checking.
Though use mask can reduce the mask expense, need many chips of cost and proving time with multistage layer IC pattern.And time of being spent of checking the more, and the time that the expression board can't volume production, the more the affected time of production capacity, the more production capacity was also lower.In addition, shipment also can postpone for client's time.In view of this, the verification method of the exposure program of a kind of mask that improves problem and exposure machine below is provided.
Fig. 3 A and Fig. 3 B are respectively the mask 300 and mask 302 of one first embodiment of the present invention and one second embodiment.Please refer to Fig. 3 A, the mask 300 of first embodiment comprises a substrate 50, and substrate 50 has checking pattern and multistage layer IC pattern.Multistage layer IC pattern for example comprises first order layer IC pattern 10 and second level layer IC pattern 70, the proof diagram sample as comprise different supergraph samples 20 ' with sub-pattern 21 '.Please refer to Fig. 3 B, the mask 302 of second embodiment also comprise a substrate 50 ', substrate 50 ' also have checking pattern and multistage layer of IC pattern.The multistage layer IC pattern of second embodiment for example comprises first order layer IC pattern 10, second level layer IC pattern 70, third level layer IC pattern 80 and fourth stage layer IC pattern 90.The proof diagram sample of second embodiment as comprise different supergraph samples 20 ', supergraph sample 20 ", sub-pattern 21 ' with sub-pattern 21 ".
In Fig. 3 A and Fig. 3 B, supergraph sample 20 ' with sub-pattern 21 ' the be separately positioned on outside of the opposite edges of first order layer IC pattern 10.Supergraph sample 20 ' greater than sub-pattern 21 '.Supergraph sample 20 " with sub-pattern 21 " is separately positioned on the outside of another opposite edges of first order layer IC pattern 10.Supergraph sample 20 " greater than sub-pattern 21 ".
Supergraph sample 20 ' with supergraph sample 20 " shape be not limited to the rectangle of hollow as shown in the figure, and also can be solid, or have other shape, for example circular, triangle or other polygon.Sub-pattern 21 ' with sub-pattern 21 " shape be not limited to as shown in the figure solid rectangle, and also can be hollow, or have other shape, for example circular, triangle or other polygon.Supergraph sample 20 ', the position of supergraph sample 20 ", sub-pattern 21 ' with sub-pattern 21 " for example can correspond to the position of the Cutting Road of a chip.The outside of the opposite edges of first order layer IC pattern 10 is not limited to only be provided with a pair of supergraph sample and sub-pattern, and how right supergraph sample and sub-pattern can be set according to circumstances.
The verification method of the exposure program of exposure machine comprises provides the chip that is coated with photoresist layer, and use mask carry out exposure program with the IC pattern transfer of mask to chip.Fig. 4 A and Fig. 4 B show that respectively the mask 300 and 302 that has from Fig. 3 A and Fig. 3 B shifts next IC pattern and the chip 60 of verifying pattern.Please refer to Fig. 3 A and Fig. 4 A, in an embodiment of verification method, be the exposure program of carrying out exposure machine, with the first order layer IC pattern 10 in the mask 300, supergraph sample 20 ' with the primary importance of sub-pattern 21 ' be transferred to chip 60 on and formation first order layer IC pattern 110A, supergraph sample 120A ' and sub-pattern 121A '.Then, mobile mask 300 is with first order layer IC pattern 10, supergraph sample 20 ' form first order layer IC pattern 110B, supergraph sample 120B ' and sub-pattern 121B ' on right-hand second place of primary importance with sub-pattern 21 ' be transferred to.Supergraph sample 120A ', supergraph sample 120B ', sub-pattern 121A ' and the position of sub-pattern 121B ' can correspond to the position of Cutting Road 100.The width of Cutting Road 100 for example is about 80 μ m.
Please refer to Fig. 3 B and Fig. 4 B, in other embodiment of verification method, be the exposure program of carrying out exposure machine, with the first order layer IC pattern 10 in the mask 302, supergraph sample 20 ', supergraph sample 20 ", sub-pattern 21 ' with sub-pattern 21 " is transferred on the primary importance of chip 60 and formation first order layer IC pattern 110A, supergraph sample 120A ', supergraph sample 120A ", sub-pattern 121A ' and sub-pattern 121A ".Then, mobile mask 302, with first order layer IC pattern 10, supergraph sample 20 ', supergraph sample 20 ", sub-pattern 21 ' with sub-pattern 21 " is transferred to and forms first order layer IC pattern 110B, supergraph sample 120B ', supergraph sample 120B ", sub-pattern 121B ' and sub-pattern 121B " on right-hand second place of primary importance.Perhaps, with the first order layer IC pattern 10 on the mask 302, supergraph sample 20 ', supergraph sample 20 ", sub-pattern 21 ' with sub-pattern 21 " is transferred on the 3rd position of primary importance top and form as a level layer IC pattern 110C, supergraph sample 120C ', supergraph sample 120C ", sub-pattern 121C ' and sub-pattern 121C ".The position of supergraph sample 120A ', supergraph sample 120A ", supergraph sample 120B ', supergraph sample 120B ", supergraph sample 120C ', supergraph sample 120C ", sub-pattern 121A ', sub-pattern 121A ", sub-pattern 121B ', sub-pattern 121B ", sub-pattern 121C ' and sub-pattern 121C " can correspond to the position of Cutting Road 100.
Fig. 5 A shows the enlarged drawing that is transferred to supergraph sample 120B ' and sub-pattern 121A ' on the chip of an embodiment.Fig. 5 B shows the enlarged drawing that is transferred to the supergraph sample 120A " with sub-pattern 121C " on the chip of an embodiment.Please refer to Fig. 5 A and Fig. 5 B, in a specific embodiment, the center of sub-pattern 121A ' and sub-pattern 121C " center aim at supergraph sample 120B ' and supergraph sample 120A respectively ", can judge that exposure program has been fit to be used for product is carried out technology this moment.(or the center of sub-pattern 121C ") only is the center of departing from supergraph sample 120B ' (or supergraph sample 120A ") a little if sub-pattern 121A ', and departure degree is within the Control Critical value time, the slip-stick artist can directly allow exposure machine that product is carried out exposure program according to experience, or after adjusting exposure program a little, allow exposure machine that product is carried out technology again.And if (or the center of sub-pattern 121C ") is when departing from the center of supergraph sample 120B ' (or supergraph sample 120A ") significantly as sub-pattern 121A ', as shown in Figure 6A, then be necessary after the adjustment program, to verify with another chip again, repeat this checking when the center relativeness of supergraph sample 120B ' (or the center of supergraph sample 120A ") and sub-pattern 121A ' (or sub-pattern 121C ") meets the requirements, could allow exposure machine that product is made.In certain embodiments, sub-pattern 121A ' even can be offset to the outside of supergraph sample 120B ' is shown in Fig. 6 B.
It should be noted that the embodiment of the invention is to judge by the position relative relation of supergraph sample and sub-pattern whether the exposure program of exposure machine correctly can be used to the volume production product, determination methods is very easy to.Because embodiments of the invention only need use a slice chip and carry out the exposure program of a level layer, can produce on chip is enough to whether executable checking pattern of determining program, and therefore the cost of verifying is low and quick.In addition, chip need not experience repeated exposure, so do not have the aberration that produces because of multiexposure, multiple exposure or lose burnt and have influence on the problem of the accuracy of checking.In an embodiment of the present invention, the position relative relation that only need observe supergraph sample local on the chip and sub-pattern can be judged the enforceability of exposure program exactly, and needn't observe supergraph sample and sub-pattern all on the entire chip, therefore judge that the time of required cost is few.Therefore, compared to the existing way of Fig. 1 and Fig. 2, the verification method of the exposure program of exposure machine of the present invention have cost low, can be fast and the advantage of checking accurately.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the scope that claim defines.
Claims (10)
1. a mask is characterized in that, comprising:
One substrate has one a multistage layer of integrated circuit (IC) pattern and a checking pattern, and this multistage layer IC pattern comprises a first order layer IC pattern and a second level layer IC pattern at least, and this checking pattern comprises:
At least one first supergraph sample and one first sub-pattern are separately positioned on one first edge of this first order layer IC pattern and the outside at one second edge, and this first edge is relative with this second edge, and this first supergraph sample is different with this first sub-pattern.
2. mask according to claim 1 is characterized in that, the area that outer rim contained of this first supergraph sample is different with the area that outer rim contained of this first sub-pattern.
3. mask according to claim 1 is characterized in that, the area that outer rim contained of this first supergraph sample is greater than the area that outer rim contained of this first sub-pattern.
4. mask according to claim 1 is characterized in that, the shape of this first supergraph sample is different with the shape of this first sub-pattern.
5. mask according to claim 4 is characterized in that, the shape of this first supergraph sample and this first sub-pattern comprises rectangle, triangle or circle.
6. mask according to claim 4 is characterized in that, this first supergraph sample and this first sub-pattern comprise hollow or solid shape.
7. mask according to claim 1 is characterized in that, the position of this first supergraph sample and this first sub-pattern corresponds to the position of the Cutting Road of a chip.
8. mask according to claim 1 is characterized in that, this mask is the exposure program in order to the checking exposure machine.
9. mask according to claim 1, it is characterized in that, this checking pattern more comprises at least one second supergraph sample and one second sub-pattern, be separately positioned on one the 3rd edge of this first order layer IC pattern and the outside at one the 4th edge, the 3rd edge is relative with the 4th edge and in abutting connection with this first edge and this second edge, and this second supergraph sample is different with this second sub-pattern.
10. the verification method of the exposure program of an exposure machine is characterized in that, comprising:
One chip is provided, is coated with a photoresist layer on this chip;
One mask is provided, this mask comprises a substrate, this substrate has one a multistage layer of IC pattern and a checking pattern, this multistage layer IC pattern comprises a first order layer IC pattern and a second level layer crystal IC pattern at least, this checking pattern comprises at least one first supergraph sample and one first sub-pattern, be separately positioned on one first edge of this first order layer IC pattern and the outside at one second edge, this first edge is relative with this second edge, this first supergraph sample is different with this first sub-pattern, this first order layer IC pattern, this first supergraph sample and this first sub-pattern correspond to a langley district; And
Use this mask to carry out this exposure program, comprise this langley district is transferred on the primary importance of this chip, and then this langley district is transferred on the second place of this primary importance of vicinity of this chip;
Wherein, the correctness of the relative position of this first supergraph sample on this first sub-pattern on this primary importance and this second place and this exposure program is relevant.
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| CN2010101884020A CN102262350A (en) | 2010-05-25 | 2010-05-25 | Verification method of exposure program of exposure machine and mask used therewith |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010101884020A CN102262350A (en) | 2010-05-25 | 2010-05-25 | Verification method of exposure program of exposure machine and mask used therewith |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050068515A1 (en) * | 2003-09-30 | 2005-03-31 | Lothar Bauch | Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer |
| CN1770419A (en) * | 2004-11-02 | 2006-05-10 | 力晶半导体股份有限公司 | Detection apparatus and method for exposure device |
| CN101435998A (en) * | 2007-11-15 | 2009-05-20 | 上海华虹Nec电子有限公司 | Method for reducing photolithography aligning partial difference caused by photoetching machine lens distortion |
| CN101592869A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Exposure equipment focal distance monitoring method |
| US20100123886A1 (en) * | 2008-11-18 | 2010-05-20 | Asml Netherlands B.V. | Lithographic Apparatus and Device Manufacturing Method |
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2010
- 2010-05-25 CN CN2010101884020A patent/CN102262350A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050068515A1 (en) * | 2003-09-30 | 2005-03-31 | Lothar Bauch | Method for detecting positioning errors of circuit patterns during the transfer by means of a mask into layers of a substrate of a semiconductor wafer |
| CN1770419A (en) * | 2004-11-02 | 2006-05-10 | 力晶半导体股份有限公司 | Detection apparatus and method for exposure device |
| CN101435998A (en) * | 2007-11-15 | 2009-05-20 | 上海华虹Nec电子有限公司 | Method for reducing photolithography aligning partial difference caused by photoetching machine lens distortion |
| CN101592869A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Exposure equipment focal distance monitoring method |
| US20100123886A1 (en) * | 2008-11-18 | 2010-05-20 | Asml Netherlands B.V. | Lithographic Apparatus and Device Manufacturing Method |
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