CN102254830A - DEPMOS (Drain Expansion P-type Metal Oxide Semiconductor) transistor and forming method thereof - Google Patents
DEPMOS (Drain Expansion P-type Metal Oxide Semiconductor) transistor and forming method thereof Download PDFInfo
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- CN102254830A CN102254830A CN2011102318975A CN201110231897A CN102254830A CN 102254830 A CN102254830 A CN 102254830A CN 2011102318975 A CN2011102318975 A CN 2011102318975A CN 201110231897 A CN201110231897 A CN 201110231897A CN 102254830 A CN102254830 A CN 102254830A
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Abstract
The invention provides a DEPMOS (Drain Expansion P-type Metal Oxide Semiconductor) transistor and a forming method thereof. The DEPMOS transistor comprises a semiconductor substrate, an N well positioned in the semiconductor substrate, a field oxide layer positioned on the semiconductor substrate, a gate dielectric layer and a grid electrode, a drain drift region, a source region and a drain region, wherein the gate dielectric layer and the grid electrode are arranged on the surface of the semiconductor substrate in sequence, the grid electrode is provided with a first side and a second side which are opposite; the drain drift region is positioned in the N well between the first side of the grid electrode and the field oxide layer; and the source region is arranged in the N well at the second side of the grid electrode and the drain region is positioned in the drain drift region, intervals are arranged between the drain region and the first side of the grid electrode and between the drain region and the filed oxide layer. According to the invention, electricity leakage is reduced or avoided by using a simple method.
Description
Technical field
The present invention relates to semiconductor device and semiconductor process techniques field, relate in particular to a kind of DEPMOS transistor and forming method thereof.
Background technology
Mesolow (12V～30V) driving element and module thereof, for example laterally diffused MOS transistor (LDMOS), drain terminal diffused mos transistor (DEMOS) etc., being widely used in fields such as LED driving, LCD driving, motor driven and chip controls, also is popular research field in recent years.Wherein, DEMOS transistor especially DEPMOS transistor (P type DEMOS transistor) is wherein very important device, and it mainly utilizes drain terminal to expand and forms the drift region, thereby obtains higher voltage endurance capability.
Periphery, the transistorized drain region of DEPMOS is surrounded by the drain terminal drift region.In the prior art, the drain terminal drift region is normally injected by ion before the transistorized grid of DEPMOS forms and is formed, and the ion implanted region territory in the drain region forming process is afterwards directly defined by active area (Active Area).In order to make the drain terminal drift region surround the drain region, it is enough big that the injection energy of the ion implantation process of drain terminal drift region is wanted, with the penetration field oxide layer, bigger injection energy makes that the degree of depth of drain terminal drift region is bigger, cause the junction depth difference of drain terminal drift region and the residing N trap of DEPMOS transistor just very little, cause drain terminal drift region, N trap and P type semiconductor substrate to form integrated PNP triode easily and cause the electric leakage problem.In order to reduce the electric leakage problem, often need in Semiconductor substrate, increase n type buried layer and epitaxial loayer in the prior art, make technology more complicated, cost is higher, is unfavorable for extensive industry application.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of DEPMOS transistor and forming method thereof, reduces the electric leakage problem in comparatively simple mode.
For solving the problems of the technologies described above, the invention provides the transistorized formation method of a kind of DEPMOS, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms the N trap, on described Semiconductor substrate, form field oxide;
Form gate dielectric layer and grid on the surface of described Semiconductor substrate successively, described grid has the first relative side and second side;
N trap between described grid first side and the field oxide is carried out ion inject, form the drain terminal drift region;
Form the photoresist figure, described photoresist graphical definition goes out the figure in source region and drain region, the figure in described source region is arranged in the N trap of described grid second side, the figure in described drain region in described drain terminal drift region and and described grid first side and field oxide between have at interval;
With described photoresist figure is that mask carries out the ion injection, to form the source region in the N trap of described grid second side, forms the drain region in described drain terminal drift region.
Alternatively, the spacing distance of the figure in described drain region and described grid first side is 0.4 to 0.8 μ m, with the spacing distance of described field oxide be 0.8 to 1.2 μ m.
Alternatively, the Semiconductor substrate between described grid first side and the field oxide is carried out ion inject, form the drain terminal drift region and comprise: with described grid and field oxide is that mask carries out the injection of autoregistration ion, forms the drain terminal drift region.
Alternatively, before carrying out described autoregistration ion injection, described formation method also comprises: form the barrier layer on described grid; After described autoregistration ion injected, described formation method also comprised: remove described barrier layer.
Alternatively, form after described source region and the drain region, described formation method also comprises:
Remove described photoresist figure;
On the surface of the drain terminal drift region between described drain region and grid first side and the field oxide, form blocking layer of metal silicide;
Surface at described source region, drain region and grid forms metal silicide.
The present invention also provides a kind of DEPMOS transistor, comprising:
Semiconductor substrate;
Be arranged in the N trap of described Semiconductor substrate;
Be positioned at the field oxide on the described Semiconductor substrate;
Be positioned at gate dielectric layer and grid on the described semiconductor substrate surface successively, described grid has the first relative side and second side;
Drain terminal drift region in the N trap between described grid first side and field oxide;
Be arranged in the source region of N trap of described grid second side and the drain region that is arranged in described drain terminal drift region, it is characterized in that,
Have between described drain region and described grid first side and the field oxide at interval.
Alternatively, the spacing distance of described drain region and described grid first side is 0.4 to 0.8 μ m, with the spacing distance of described field oxide be 0.8 to 1.2 μ m.
Alternatively, described drain terminal drift region is to be that mask is self aligned with described grid and field oxide.
Alternatively, described DEPMOS transistor also comprises the metal silicide that is positioned on described source region, drain region and the gate surface.
Alternatively, described DEPMOS transistor also comprises the lip-deep blocking layer of metal silicide of the drain terminal drift region between described drain region and grid first side and field oxide.
Compared with prior art, the present invention has the following advantages:
Have between the transistorized drain region of the DEPMOS of the embodiment of the invention and grid and the field oxide at interval, thereby in its forming process, the ion implantation process of drain terminal drift region does not need the penetration field oxide layer, thereby can avoid or slow down the too small problem of junction depth difference between drain terminal drift region and the N trap, thereby reduce or avoid the electric leakage problem.In the transistorized forming process of the DEPMOS of the embodiment of the invention, do not need to form n type buried layer and epitaxial loayer, its complexity is lower, can reduce a lot of costs to large-scale production.
Description of drawings
Fig. 1 is the schematic flow sheet of the transistorized formation method of the DEPMOS of the embodiment of the invention;
Fig. 2 to Fig. 7 is the cross-sectional view of each step in the transistorized formation method of the DEPMOS of the embodiment of the invention.
Embodiment
The injection zone in the conventional transistorized drain region of DEPMOS defines with active area in the prior art, makes the injection process of drain terminal drift region need the penetration field oxide layer, causes the degree of depth of drain terminal drift region excessive, is easy to generate the electric leakage problem.
Have between the transistorized drain region of the DEPMOS of the embodiment of the invention and grid and the field oxide at interval, thereby in its forming process, the ion implantation process of drain terminal drift region does not need the penetration field oxide layer, thereby can avoid or slow down the too small problem of junction depth difference between drain terminal drift region and the N trap, thereby reduce or avoid the electric leakage problem.In the transistorized forming process of the DEPMOS of the embodiment of the invention, do not need to form n type buried layer and epitaxial loayer, its complexity is lower, can reduce a lot of costs to large-scale production.
The invention will be further described below in conjunction with specific embodiments and the drawings, but should not limit protection scope of the present invention with this.
Fig. 1 shows the schematic flow sheet of the transistorized formation method of DEPMOS of present embodiment, comprising:
Step S11 provides Semiconductor substrate, forms the N trap in described Semiconductor substrate, forms field oxide on described Semiconductor substrate;
Step S12 forms gate dielectric layer and grid successively on the surface of described Semiconductor substrate, described grid has the first relative side and second side;
Step S13 carries out ion to the N trap between described grid first side and the field oxide and injects, and forms the drain terminal drift region;
Step S14, form the photoresist figure, described photoresist graphical definition goes out the figure in source region and drain region, and the figure in described source region is arranged in the N trap of described grid second side, the figure in described drain region in described drain terminal drift region and and described grid first side and field oxide between have at interval;
Step S15 is that mask carries out the ion injection with described photoresist figure, to form the source region in the N trap of described grid second side, forms the drain region in described drain terminal drift region.
Fig. 2 to Fig. 7 shows the cross-sectional view of each step in the present embodiment, below in conjunction with Fig. 1 and Fig. 2 to Fig. 7 present embodiment is elaborated.
In conjunction with Fig. 1 and Fig. 2, execution in step S11 provides Semiconductor substrate 10, forms N trap 11 in Semiconductor substrate 10, forms field oxide 12 on Semiconductor substrate 10.
Concrete, Semiconductor substrate 10 can be silicon substrate, germanium silicon substrate, the III-V group element compound substrate of P type doping or the Semiconductor substrate that well known to a person skilled in the art other types, what adopted in the present embodiment is silicon substrate.The formation method of N trap 11 can be conventional methods such as ion implantation, and the formation method of field oxide 12 can be thermal oxidation method or high density plasma deposition conventional methods such as (HDP).
In conjunction with Fig. 1 and Fig. 3, execution in step S12 forms gate dielectric layer 13 and grid 14 successively on the surface of Semiconductor substrate 10, and grid 14 has the first relative side and second side.
In the present embodiment, the material of gate dielectric layer 13 is a silica, and its formation method is thermal oxidation method or well known to a person skilled in the art additive method.The material of grid 14 is polysilicons, and its formation method is chemical vapor deposition (CVD) or well known to a person skilled in the art additive method.More specifically, after forming silicon oxide layer and polysilicon layer, can carry out graphically silicon oxide layer and polysilicon layer, thereby form gate dielectric layer 13 and the grid 14 shown in Fig. 3 by methods such as reactive ion etchings.
As a nonrestrictive example, the right side of grid 14 is first side in the present embodiment, and the left side is second side.
In addition, as a preferred embodiment, can also form the barrier layer (not shown) on the surface of grid 14, the material on barrier layer can be a silicon nitride.
In conjunction with Fig. 1 and Fig. 4, execution in step S13 carries out ion to the N trap 11 between grid 14 first sides and the field oxide 12 and injects, and forms drain terminal drift region 16.
Concrete, can form photoresist layer 15 and it is carried out graphically, expose the field oxide 12 of grid 14 (being specially the barrier layer that is positioned on the grid 14 in the present embodiment), grid 14 first sides and the surface of the Semiconductor substrate between the two 10.Afterwards, be that mask carries out the autoregistration ion and injects with the field oxide 12 of the grid 14 and first side thereof, injecting ion is P type ion, as the boron ion etc., thereby forms drain terminal drift region 16.
Before on the barrier layer that forms on the grid 14 in the autoregistration ion implantation process, can play barrier effect to the ion that injects, thereby strengthen the autoregistration effect of grid 14.After the autoregistration ion injects, the barrier layer on photoresist layer 15 and the grid 14 can be removed.
Need to prove, in the autoregistration ion implantation process that forms drain terminal drift region 16, inject ion and do not need penetration field oxide layer 12, also promptly under the equivalent device specification, compared with prior art, the energy of the ion implantation process of formation drain terminal drift region 16 is lower in the present embodiment, and the degree of depth of formed drain terminal drift region 16 is less, bigger with the junction depth difference of N trap 11, as can to reduce even avoid parasitic PNP triode to cause effectively electric leakage problem.
In conjunction with Fig. 1 and Fig. 5, execution in step S14, form photoresist figure 17, photoresist figure 17 defines the figure in source region 18 and drain region 19, the figure in source region 18 is arranged in the N trap 11 of grid 14 second sides, the figure in drain region 19 in drain terminal drift region 16 and and grid 14 first sides and field oxide 12 between have at interval; Execution in step S15 is that mask carries out the ion injection with photoresist figure 17, to form source region 18 in the N trap 11 of grid 14 second sides, forms drain region 19 in drain terminal drift region 16.
Concrete, the forming process of photoresist figure 17 can comprise: spin coating forms photoresist layer, the surface of cover gate 14, field oxide 12 and Semiconductor substrate 10; To formed photoresist layer expose, development etc., define the figure in source region 18 and drain region 19.In the present embodiment, the critical size of grid 14 (CD, Critical Dimension) is 1 μ m, and the spacing distance d1 of the figure in drain region 19 and grid 14 first sides is 0.4 to 0.8 μ m, is preferably 0.6 μ m; The spacing distance of the field oxide 12 of the figure in drain region 19 and grid 14 first sides is 0.8 to 1.2 μ m, is preferably 1.0 μ m.The ion that injects in source region 18 and the drain region 19 can be P type ions such as boron ion.
Owing to have between the figure in the drain region 19 that photoresist figure 17 is defined and grid 14 first sides and the field oxide 12 at interval, mask injects by the autoregistration ion forms and to be field oxides 12 with the grid 14 and first side thereof be in drain terminal drift region 16, thereby make the drain region 19 that forms be arranged in drain terminal drift region 16, also be the periphery that drain terminal drift region 16 is enclosed in drain region 19.After forming source region 18 and drain region 19, can pass through ashing method methods such as (ashing) photoresist figure 17 is removed.
Afterwards with reference to figure 6, on the surface of drain region 19 and the drain terminal drift region 16 of grid 14 first sides, and form blocking layer of metal silicide 20 on the surface of the drain terminal drift region 16 between the field oxide 12 of drain region 19 and grid 14 first sides, also on an end surfaces of grid 14 first sides, be formed with blocking layer of metal silicide 20 in the present embodiment.The material of blocking layer of metal silicide 20 can be silica, silicon nitride or its combination, and its formation method can be chemical vapour deposition (CVD) etc.Preferably, the blocking layer of metal silicide 20 between drain region 19 and field oxide 12 can extend on field oxide 12, and the width d3 of itself and field oxide 12 overlapping areas is 0.3 to 0.5 μ m, is preferably 0.4 μ m.
With reference to figure 7, on the surface of source region 18, drain region 19 and grid 14, form metal silicide 21 afterwards.The forming process of metal silicide 21 can comprise: form metal level, cover the surface of whole Semiconductor substrate 10, the surface that comprises field oxide 12, grid 14, source region 18, drain region 19 and blocking layer of metal silicide 20, the material of this metal level can be the alloys of titanium, cobalt, nickel or its combination in any; Semiconductor substrate 10 is annealed, make the surface of metal level and source region 18, drain region 19 and grid 14 react, generate metal silicide 21; Afterwards, the metal level that does not react is removed.Owing to be formed with blocking layer of metal silicide 20 on the drain terminal drift region 16 between drain region 19 and grid 14 first sides and the field oxide 12, thereby this zone can't form metal silicide 21.
So far, the transistorized structure of DEPMOS that present embodiment forms comprises: Semiconductor substrate 10 as shown in Figure 7; Be arranged in the N trap 11 of Semiconductor substrate 10; Be positioned at the field oxide 12 on the Semiconductor substrate 10; Be positioned at Semiconductor substrate 10 lip-deep gate dielectric layer 13 and grids 14 successively, grid 14 has the first relative side and second side; Drain terminal drift region 16 in the N trap 11 between grid 14 first sides and field oxide 12; Be arranged in the source region 18 of N trap 11 of grid 14 second sides and the drain region 19 that is arranged in drain terminal drift region 16, wherein, have between drain region 19 and grid 14 first sides and the field oxide 12 at interval.
In conjunction with Fig. 5, drain region 19 is 0.4 to 0.8 μ m with the spacing distance d1 of grid 14 first sides, and the spacing distance d2 between the field oxide 12 of drain region 19 and grid 14 first sides is 0.8 to 1.2 μ m.
In addition, also be formed with metal silicide 21 on the surface of the transistorized source region 18 of the DEMOS of present embodiment, drain region 19 and grid 14, be formed with blocking layer of metal silicide 20 on the interval between drain region 19 and grid 14 and the field oxide 12.In the present embodiment, all have between drain region 19 and grid 14 and the field oxide 12 at interval, be not to define with the active area between the two, thereby make ion in the forming process of drain terminal drift region 16 inject not need penetration field oxide layer 12, thereby avoid or reduced the excessive electric leakage problem that causes of drain terminal drift region 16 degree of depth.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1. the transistorized formation method of DEPMOS is characterized in that, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms the N trap, on described Semiconductor substrate, form field oxide;
Form gate dielectric layer and grid on the surface of described Semiconductor substrate successively, described grid has the first relative side and second side;
N trap between described grid first side and the field oxide is carried out ion inject, form the drain terminal drift region;
Form the photoresist figure, described photoresist graphical definition goes out the figure in source region and drain region, the figure in described source region is arranged in the N trap of described grid second side, the figure in described drain region in described drain terminal drift region and and described grid first side and field oxide between have at interval;
With described photoresist figure is that mask carries out the ion injection, to form the source region in the N trap of described grid second side, forms the drain region in described drain terminal drift region.
2. the transistorized formation method of DEPMOS according to claim 1 is characterized in that, the spacing distance of the figure in described drain region and described grid first side is 0.4 to 0.8 μ m, with the spacing distance of described field oxide be 0.8 to 1.2 μ m.
3. the transistorized formation method of DEPMOS according to claim 1, it is characterized in that, Semiconductor substrate between described grid first side and the field oxide is carried out ion to be injected, forming the drain terminal drift region comprises: with described grid and field oxide is that mask carries out the injection of autoregistration ion, forms the drain terminal drift region.
4. the transistorized formation method of DEPMOS according to claim 3 is characterized in that, before carrying out described autoregistration ion injection, also comprises: form the barrier layer on described grid; After described autoregistration ion injects, also comprise: remove described barrier layer.
5. the transistorized formation method of DEPMOS according to claim 1 is characterized in that, forms after described source region and the drain region, also comprises:
Remove described photoresist figure;
On the surface of the drain terminal drift region between described drain region and grid first side and the field oxide, form blocking layer of metal silicide;
Surface at described source region, drain region and grid forms metal silicide.
6. DEPMOS transistor comprises:
Semiconductor substrate;
Be arranged in the N trap of described Semiconductor substrate;
Be positioned at the field oxide on the described Semiconductor substrate;
Be positioned at gate dielectric layer and grid on the described semiconductor substrate surface successively, described grid has the first relative side and second side;
Drain terminal drift region in the N trap between described grid first side and field oxide;
Be arranged in the source region of N trap of described grid second side and the drain region that is arranged in described drain terminal drift region, it is characterized in that,
Have between described drain region and described grid first side and the field oxide at interval.
7. DEPMOS transistor according to claim 6 is characterized in that, the spacing distance of described drain region and described grid first side is 0.4 to 0.8 μ m, with the spacing distance of described field oxide be 0.8 to 1.2 μ m.
8. DEPMOS transistor according to claim 6 is characterized in that, described drain terminal drift region is to be that mask is self aligned with described grid and field oxide.
9. DEPMOS transistor according to claim 6 is characterized in that, also comprises the metal silicide that is positioned on described source region, drain region and the gate surface.
10. DEPMOS transistor according to claim 6 is characterized in that, also comprises the lip-deep blocking layer of metal silicide of the drain terminal drift region between described drain region and grid first side and field oxide.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110231897.5A CN102254830B (en) | 2011-08-12 | 2011-08-12 | DEPMOS (Drain Expansion P-type Metal Oxide Semiconductor) transistor and forming method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107359190A (en) * | 2017-07-12 | 2017-11-17 | 长沙方星腾电子科技有限公司 | A kind of high voltage PMOS transistor in low pressure process |
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| CN101901786A (en) * | 2009-05-26 | 2010-12-01 | 上海华虹Nec电子有限公司 | Preparation method for integrated circuit containing DMOS transistor |
| CN102130166A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Dddmos device |
| US20120001260A1 (en) * | 2010-07-02 | 2012-01-05 | Macronix International Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
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| US20090256212A1 (en) * | 2008-04-11 | 2009-10-15 | Texas Instruments, Inc. | Lateral drain-extended mosfet having channel along sidewall of drain extension dielectric |
| CN101901786A (en) * | 2009-05-26 | 2010-12-01 | 上海华虹Nec电子有限公司 | Preparation method for integrated circuit containing DMOS transistor |
| CN102130166A (en) * | 2010-01-20 | 2011-07-20 | 上海华虹Nec电子有限公司 | Dddmos device |
| US20120001260A1 (en) * | 2010-07-02 | 2012-01-05 | Macronix International Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
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| CN107359190A (en) * | 2017-07-12 | 2017-11-17 | 长沙方星腾电子科技有限公司 | A kind of high voltage PMOS transistor in low pressure process |
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