CN102254072A - Analytical model for threshold voltage of fence-structured MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) - Google Patents

Analytical model for threshold voltage of fence-structured MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) Download PDF

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CN102254072A
CN102254072A CN2011102192375A CN201110219237A CN102254072A CN 102254072 A CN102254072 A CN 102254072A CN 2011102192375 A CN2011102192375 A CN 2011102192375A CN 201110219237 A CN201110219237 A CN 201110219237A CN 102254072 A CN102254072 A CN 102254072A
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threshold voltage
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mosfet
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梅光辉
李佩成
胡光喜
倪亚路
刘冉
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Fudan University
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Abstract

本发明属于半导体技术领域，具体为一种计算围栅结构金属-氧化物-半导体场效应晶体管（MOSFET）阈值电压的解析模型。本发明通过求出围栅结构MOSFET的电势分布，根据电势分布求出其表面电荷密度，然后根据本发明阈值电压的定义方法，在器件虚电极处表面电荷密度等于临界电荷密度时候对应的栅电压为阈值电压，从而得到阈值电压解析模型。该阈值电压解析模型形式简洁、物理概念清晰，且计算精度高，为电路模拟软件在研究新型围栅器件时候，提供了一种快速精确的工具。

Figure 201110219237

The invention belongs to the technical field of semiconductors, in particular to an analytical model for calculating the threshold voltage of a metal-oxide-semiconductor field-effect transistor (MOSFET) with a surrounding gate structure. The present invention obtains the electric potential distribution of the gate-enclosed structure MOSFET, obtains its surface charge density according to the electric potential distribution, and then according to the definition method of the threshold voltage of the present invention, the gate voltage corresponding to when the surface electric charge density at the virtual electrode of the device is equal to the critical electric charge density is the threshold voltage, thus the threshold voltage analytical model is obtained. The threshold voltage analysis model is simple in form, clear in physical concept, and high in calculation accuracy, which provides a fast and accurate tool for circuit simulation software to study new gate-enclosed devices.

Figure 201110219237

Description

一种围栅结构MOSFET阈值电压解析模型An Analytical Model of Threshold Voltage of MOSFET with Enclosed Gate Structure

技术领域 technical field

本发明属于半导体技术领域，具体涉及一种计算围栅结构金属-氧化物-半导体场效应晶体管（MOSFET）阈值电压的模型。 The invention belongs to the technical field of semiconductors, and in particular relates to a model for calculating the threshold voltage of a metal-oxide-semiconductor field effect transistor (MOSFET) with a surrounding gate structure.

背景技术 Background technique

随着集成电路芯片集成度不断提高和器件几何尺寸的不断缩小，在纳米尺度MOSFET器件发展过程中,已经逐步从平面工艺向非平面立体结构发展。而在各类非传统平面器件结构中，围栅结构MOSFET，由于栅极可以将沟道完全包围，其集成密度最高，栅极控制能力最强，能够更好抑制短沟道效应，降低器件的静态功耗，使得亚阈值电流最小化。MOSFET器件进入纳米尺度是最理想的结构。因此对这种围栅MOSFET结构，创建解析模型变得尤为重要。同时以此围栅结构MOSFET 的阈值电压提取模型日益受到工业界关注。对于以往传统平面工艺的体硅MOSFET阈值电压模型已经不能适应，对于这种新型多栅纳米器件的建模与模拟带来了新的挑战。 With the continuous improvement of integrated circuit chip integration and the continuous reduction of device geometric size, in the development process of nanoscale MOSFET devices, it has gradually developed from planar technology to non-planar three-dimensional structure. Among all kinds of non-traditional planar device structures, the gate-enclosed MOSFET, because the gate can completely surround the channel, has the highest integration density and the strongest gate control ability, which can better suppress the short channel effect and reduce the device cost. quiescent power dissipation, which minimizes subthreshold current. It is the most ideal structure for MOSFET devices to enter the nanometer scale. Therefore, it is particularly important to create an analytical model for this gate-enclosed MOSFET structure. At the same time, the threshold voltage extraction model of the gate-enclosed MOSFET has been increasingly concerned by the industry. The threshold voltage model of the bulk silicon MOSFET in the traditional planar process can no longer be adapted, and it brings new challenges to the modeling and simulation of this new multi-gate nano-device.

阈值电压                                                

Figure 298096DEST_PATH_IMAGE001
是MOSFET最为重要参数之一，阈值电压的定义为：达到阈值反型点时候所需要的栅压，对于n型器件当表面势等于2倍的电子准费米电势
Figure 906932DEST_PATH_IMAGE002
时的器件状态，或者对于p型器件当表面势等于2倍的空穴准费米电势
Figure 893474DEST_PATH_IMAGE003
时的器件状态。为了使用电路模拟软件能够正确模拟电路特性，建立精确的阈值电压模型是非常重要的。 threshold voltage
Figure 298096DEST_PATH_IMAGE001
It is one of the most important parameters of MOSFET. The threshold voltage is defined as: the gate voltage required to reach the threshold inversion point. For n-type devices, when the surface potential is equal to twice the electron quasi-Fermi potential
Figure 906932DEST_PATH_IMAGE002
The device state at , or for a p-type device when the surface potential is equal to twice the quasi-Fermi potential of the hole
Figure 893474DEST_PATH_IMAGE003
device status at the time. In order to correctly simulate circuit characteristics using circuit simulation software, it is very important to establish an accurate threshold voltage model.

发明内容 Contents of the invention

有鉴于此，本发明目的在于提供一种形式简洁、物理概念清晰，且精度高的围栅结构MOSFET阈值电压模型。 In view of this, the purpose of the present invention is to provide a gate-enclosed structure MOSFET threshold voltage model with simple form, clear physical concept and high precision.

本发明提出的围栅结构MOSFET阈值电压解析模型，为了电路模拟软件在研究围栅器件时候，提供一种快速精确解析模型。 The gate-enclosed structure MOSFET threshold voltage analytical model proposed by the present invention provides a fast and accurate analytical model for circuit simulation software to study gate-enclosed devices.

对于全耗尽围栅MOSFET,当工作在耗尽区和弱反型还没有达到强反型时候电势分布主要是由于由不可移动的电离杂质决定的，可以忽略自由载流子的影响，本发明提出的阈值电压模型这里作了耗尽近似假设。在阈值区和亚阈值区可移动电荷很少可以忽略，在沟道强反型开始之前，对于围栅MOSFET沟道是全耗尽的，当沟道区P型掺杂，所以其沟道区电势分布可以通过柱坐标系下的泊松方程表示： For the fully depleted surrounding gate MOSFET, when working in the depletion region and the weak inversion has not reached the strong inversion, the potential distribution is mainly determined by the immovable ionized impurities, and the influence of free carriers can be ignored. The present invention The proposed threshold voltage model here makes a depletion approximation assumption. In the threshold region and sub-threshold region, the movable charge is seldom negligible. Before the strong inversion of the channel begins, the channel of the surrounding gate MOSFET is fully depleted. When the channel region is P-type doped, so its channel region The potential distribution can be expressed by Poisson's equation in cylindrical coordinate system:

Figure 904155DEST_PATH_IMAGE004
                   (1)
Figure 904155DEST_PATH_IMAGE004
(1)

Figure 934428DEST_PATH_IMAGE005
，
Figure 30560DEST_PATH_IMAGE006
，，
Figure 918936DEST_PATH_IMAGE008
      (2)
Figure 934428DEST_PATH_IMAGE005
,
Figure 30560DEST_PATH_IMAGE006
, ,
Figure 918936DEST_PATH_IMAGE008
(2)

式中，栅氧化层 

Figure 120110DEST_PATH_IMAGE009
，a为围栅MOSFET器件半径，t ox 为栅极氧化层厚度；
Figure 516588DEST_PATH_IMAGE010
和
Figure 828620DEST_PATH_IMAGE011
为硅和栅极氧化物的介电常数；L为沟道长度； 
Figure 813894DEST_PATH_IMAGE012
为电势分布函数；q为电子电量；
Figure 452815DEST_PATH_IMAGE013
为沟道区掺杂浓度； 
Figure 523539DEST_PATH_IMAGE014
,
Figure 639263DEST_PATH_IMAGE015
为源极Source的电势，
Figure 479043DEST_PATH_IMAGE016
为内建电势；
Figure 772752DEST_PATH_IMAGE017
是漏极Drain相对于源极电压；
Figure 127510DEST_PATH_IMAGE018
，
Figure 984608DEST_PATH_IMAGE019
为栅极Gate相对于源极的电压；
Figure 990479DEST_PATH_IMAGE020
为平带电压。 In the formula, the gate oxide layer
Figure 120110DEST_PATH_IMAGE009
, a is the radius of the surrounding gate MOSFET device, t ox is the thickness of the gate oxide layer;
Figure 516588DEST_PATH_IMAGE010
and
Figure 828620DEST_PATH_IMAGE011
is the dielectric constant of silicon and gate oxide; L is the channel length;
Figure 813894DEST_PATH_IMAGE012
is the potential distribution function; q is the electron quantity;
Figure 452815DEST_PATH_IMAGE013
is the doping concentration of the channel region;
Figure 523539DEST_PATH_IMAGE014
,
Figure 639263DEST_PATH_IMAGE015
is the potential of the source Source,
Figure 479043DEST_PATH_IMAGE016
is the built-in potential;
Figure 772752DEST_PATH_IMAGE017
is the drain Drain relative to the source voltage;
Figure 127510DEST_PATH_IMAGE018
,
Figure 984608DEST_PATH_IMAGE019
is the voltage of the gate Gate relative to the source;
Figure 990479DEST_PATH_IMAGE020
is the flat-band voltage.

为了求解电势分布泊松方程，把电势分解为只适用于长沟道情况下的一维电势

Figure 642040DEST_PATH_IMAGE021
和利用拉普拉斯方程求解包含所有边界条件的二维电势
Figure 749673DEST_PATH_IMAGE022
，所以总的电势方程就为： In order to solve the Poisson equation for the potential distribution, the potential is decomposed into a one-dimensional potential that is only applicable to the case of a long channel
Figure 642040DEST_PATH_IMAGE021
and using Laplace's equation to solve the 2D electric potential including all boundary conditions
Figure 749673DEST_PATH_IMAGE022
, so the overall potential equation is:

Figure 144882DEST_PATH_IMAGE023
                                 (3) 。
Figure 144882DEST_PATH_IMAGE023
(3).

于是，方程式（1）分解为关于一维电势

Figure 506725DEST_PATH_IMAGE024
的方程： Then, equation (1) decomposes into the one-dimensional electric potential
Figure 506725DEST_PATH_IMAGE024
The equation for:

Figure 594766DEST_PATH_IMAGE025
                                      (4)
Figure 594766DEST_PATH_IMAGE025
(4)

和关于二维电势的拉普拉斯方程： and with respect to the two-dimensional potential The Laplace equation for :

Figure 123017DEST_PATH_IMAGE027
                   (5) 。
Figure 123017DEST_PATH_IMAGE027
(5).

在求解一维电势

Figure 526316DEST_PATH_IMAGE028
的解析方法中，根据一维氧化层与体硅界面处的边界条件： Solving for one-dimensional electric potential
Figure 526316DEST_PATH_IMAGE028
In the analytical method of , according to the boundary conditions at the interface between the one-dimensional oxide layer and the bulk silicon:

Figure 96844DEST_PATH_IMAGE029
                                           (6)
Figure 96844DEST_PATH_IMAGE029
(6)

                            (7) (7)

解为：  The solution is:

Figure 650502DEST_PATH_IMAGE031
                            (8)
Figure 650502DEST_PATH_IMAGE031
(8)

其中

Figure 49253DEST_PATH_IMAGE032
，
Figure 790682DEST_PATH_IMAGE033
。 in
Figure 49253DEST_PATH_IMAGE032
,
Figure 790682DEST_PATH_IMAGE033
.

所以  so

   

Figure 766728DEST_PATH_IMAGE034
           (9)
Figure 766728DEST_PATH_IMAGE034
(9)

求解二维拉普拉斯方程：  Solve the Laplace equation in 2D:

 

Figure 369748DEST_PATH_IMAGE035
                                   (10)
Figure 369748DEST_PATH_IMAGE035
(10)

Figure 13219DEST_PATH_IMAGE036
                                        
Figure 13219DEST_PATH_IMAGE036
                                        

Figure 161435DEST_PATH_IMAGE037
                              
Figure 161435DEST_PATH_IMAGE037
                              

                                                             

Figure 348932DEST_PATH_IMAGE039
                                                        (11) 。
Figure 348932DEST_PATH_IMAGE039
(11).

利用分离变量法求解上面二维拉普拉斯方程给出它级数形式的解： Solving the above two-dimensional Laplace equation using the method of separation of variables gives its solution in series form:

Figure 909226DEST_PATH_IMAGE040
          (12)
Figure 909226DEST_PATH_IMAGE040
(12)

Figure 228343DEST_PATH_IMAGE041
             (13)
Figure 228343DEST_PATH_IMAGE041
(13)

Figure 444561DEST_PATH_IMAGE042
             (14)
Figure 444561DEST_PATH_IMAGE042
(14)

Figure 389383DEST_PATH_IMAGE043
              (15) 。
Figure 389383DEST_PATH_IMAGE043
(15).

是特征值；

Figure 995999DEST_PATH_IMAGE045
是n阶贝塞尔函数；
Figure 496251DEST_PATH_IMAGE046
是贝塞尔-傅里叶系数，特征值满足： 
Figure 729917DEST_PATH_IMAGE047
  。 is the characteristic value;
Figure 995999DEST_PATH_IMAGE045
is the nth order Bessel function;
Figure 496251DEST_PATH_IMAGE046
are the Bessel-Fourier coefficients, and the eigenvalues satisfy:
Figure 729917DEST_PATH_IMAGE047
.

传统阈值电压模型的定义：表面电势最低点的电势等于2倍的沟道表面电势即

Figure 202487DEST_PATH_IMAGE048
时所对应的栅电压。由此定义，先求出电势最低点的位置，然后即可求出阈值电压。本发明采用的阈值电压定义：依据器件虚电极处表面电荷密度等于临界电荷密度时候对应的栅电压。虚电极的位置是器件沿沟道方向的电势最低点。 The definition of the traditional threshold voltage model: the potential at the lowest point of the surface potential is equal to twice the channel surface potential, that is
Figure 202487DEST_PATH_IMAGE048
corresponding to the gate voltage. From this definition, the position of the lowest point of electric potential is obtained first, and then the threshold voltage can be obtained. The definition of threshold voltage used in the present invention is based on the corresponding gate voltage when the surface charge density at the virtual electrode of the device is equal to the critical charge density. The position of the dummy electrode is the lowest potential point of the device along the direction of the channel.

当器件表面反型层电荷密度等于电离杂质电荷等效面密度时，对于p型掺杂全耗尽沟道器件，临界电荷密度等于受主电离杂质电荷等效面密度

Figure 424259DEST_PATH_IMAGE049
。虚电极处表面反型层电荷密度可以通过对反型层电荷从沟道中心积分到表面得到： When the charge density of the inversion layer on the surface of the device is equal to the equivalent surface density of the ionized impurity charge, for a p-type doped fully depleted channel device, the critical charge density is equal to the equivalent surface density of the acceptor ionized impurity charge
Figure 424259DEST_PATH_IMAGE049
. The surface inversion layer charge density at the virtual electrode can be obtained by integrating the inversion layer charge from the center of the channel to the surface:

Figure 349489DEST_PATH_IMAGE050
                  (16) 。
Figure 349489DEST_PATH_IMAGE050
(16).

其中虚电极的位置 

Figure 636114DEST_PATH_IMAGE051
根据 ： where the position of the virtual electrode
Figure 636114DEST_PATH_IMAGE051
according to :

Figure 776240DEST_PATH_IMAGE052
                       (17)
Figure 776240DEST_PATH_IMAGE052
(17)

 

Figure 122907DEST_PATH_IMAGE053
       (18)
Figure 122907DEST_PATH_IMAGE053
(18)

求出电势最低点 

Figure 535434DEST_PATH_IMAGE051
，
Figure 609438DEST_PATH_IMAGE054
为虚电极处费米能级，费米能级
Figure 853338DEST_PATH_IMAGE055
，
Figure 121639DEST_PATH_IMAGE056
是本征载流子浓度，
Figure 83779DEST_PATH_IMAGE057
是热电压，在弱反型区可以认为： Find the lowest point of electric potential
Figure 535434DEST_PATH_IMAGE051
,
Figure 609438DEST_PATH_IMAGE054
is the Fermi level at the virtual electrode, the Fermi level
Figure 853338DEST_PATH_IMAGE055
,
Figure 121639DEST_PATH_IMAGE056
is the intrinsic carrier concentration,
Figure 83779DEST_PATH_IMAGE057
is the thermal voltage, which can be considered in the weak inversion region as:

Figure 649889DEST_PATH_IMAGE058
              (19) 。
Figure 649889DEST_PATH_IMAGE058
(19).

因此求出虚电极处表面反型层电荷密度为：  Therefore, the charge density of the surface inversion layer at the virtual electrode is calculated as:

Figure 991704DEST_PATH_IMAGE059
Figure 991704DEST_PATH_IMAGE059

(20) (20)

当时候，阈值电压等于所加的栅极电压： when When , the threshold voltage is equal to the applied gate voltage:

Figure 67293DEST_PATH_IMAGE061
(21) 。
Figure 67293DEST_PATH_IMAGE061
(twenty one) .

阈值电压数值计算时候，由于高阶项衰减极快对结果没有影响，取n=3，

Figure 984565DEST_PATH_IMAGE062
可以忽略，这样可以减小计算开销。 When calculating the threshold voltage value, since the high-order term decays very quickly and has no effect on the result, take n = 3,
Figure 984565DEST_PATH_IMAGE062
can be ignored, which reduces computational overhead.

式(21)为计算围栅MOSFET的阈值电压模型的解析表达式，优点是通过解析出围栅MOSFET阈值电压，简化计算模型使得计算开销小。 Equation (21) is an analytical expression for calculating the threshold voltage model of the gate-enclosed MOSFET. The advantage is that by analyzing the threshold voltage of the gate-enclosed MOSFET, the calculation model is simplified and the calculation cost is small.

附图说明 Description of drawings

图1为围栅MOSFET三维结构图。 Figure 1 is a three-dimensional structure diagram of a gate-enclosed MOSFET.

图2为围栅MOSFET沿沟道方向截面图。 FIG. 2 is a cross-sectional view of the gate-enclosed MOSFET along the channel direction.

图 3不同半径阈值电压随沟道长度的变化。 Fig. 3 Variation of threshold voltage with channel length for different radii.

图 4不同厚度的栅氧化层阈值电压随沟道长度的变化。 Figure 4 Variation of threshold voltage with channel length for gate oxide layers with different thicknesses.

图5为阈值电压建模流程示意图。 FIG. 5 is a schematic diagram of a threshold voltage modeling process.

具体实施方式 Detailed ways

针对背景技术提及的问题，现有的TCAD仿真软件中间计算围栅MOSFET阈值电压通过数值模拟进行计算。通过我们的解析模型计算，如图3所示本发明n型围栅MOSFET阈值电压随沟道长度变化的解析结果和TCAD模拟曲线,在相同栅极氧化层厚度

Figure 203056DEST_PATH_IMAGE063
条件下，选取3种不同半径尺寸类型的器件,其中沟道半径5，7.5，10和沟道长度分别为20, 30, 40, 50, 60, 70, 80, 90, 100,单位为纳米nm。如图4所示,在沟道半径
Figure 111DEST_PATH_IMAGE064
条件下，选取3种不同半径栅氧化层类型的器件,其中半径1，2，5和沟道长度分别为20, 30, 40, 50, 60, 70, 80, 90, 100,单位为纳米nm。对于每种器件
Figure 920531DEST_PATH_IMAGE065
,
Figure 156341DEST_PATH_IMAGE066
,常温
Figure DEST_PATH_IMAGE067
进行计算和TCAD软件中数值模拟出来结果对比，TCAD通过电流电压I/V特性曲线计算出阈值电压。 In view of the problems mentioned in the background technology, the existing TCAD simulation software calculates the threshold voltage of the surrounding gate MOSFET through numerical simulation. Calculated by our analytical model, as shown in Figure 3, the analytical results and TCAD simulation curves of the threshold voltage of the n-type gate MOSFET of the present invention changing with the channel length, in the same gate oxide layer thickness
Figure 203056DEST_PATH_IMAGE063
Under the conditions, select 3 types of devices with different radius sizes, in which the channel radius is 5, 7.5, 10 and the channel length is 20, 30, 40, 50, 60, 70, 80, 90, 100, the unit is nanometer nm . As shown in Figure 4, in the channel radius
Figure 111DEST_PATH_IMAGE064
Under the condition, select 3 kinds of devices with gate oxide layer with different radii, in which the radii 1, 2, 5 and channel length are 20, 30, 40, 50, 60, 70, 80, 90, 100, the unit is nanometer nm . for each device
Figure 920531DEST_PATH_IMAGE065
,
Figure 156341DEST_PATH_IMAGE066
, room temperature
Figure DEST_PATH_IMAGE067
Comparing the calculation with the numerical simulation results in TCAD software, TCAD calculates the threshold voltage through the current-voltage I/V characteristic curve.

Claims (2)

1. one kind is enclosed grid structure MOSFET threshold voltage analytic model, it is characterized in that the analytic expression of this threshold voltage model is:
Figure 2011102192375100001DEST_PATH_IMAGE001
Wherein, gate oxide
Figure 377148DEST_PATH_IMAGE002
, aBe the fense MOSFET device radius, t Ox Be thickness of grid oxide layer; With
Figure 231971DEST_PATH_IMAGE004
Specific inductive capacity for silicon and gate oxide; LBe the fense MOSFET device channel length; qBe electron charge;
Figure 11709DEST_PATH_IMAGE006
,
Figure 2011102192375100001DEST_PATH_IMAGE007
Be the electromotive force of source electrode,
Figure 2011102192375100001DEST_PATH_IMAGE009
Be built-in electromotive force; Be that drain electrode is with respect to source voltage;
Figure 2011102192375100001DEST_PATH_IMAGE013
, Be the voltage of grid with respect to source electrode;
Figure 656185DEST_PATH_IMAGE016
Be flat-band voltage,
Figure 2011102192375100001DEST_PATH_IMAGE017
Be empty electrode place Fermi level, Fermi level
Figure 2011102192375100001DEST_PATH_IMAGE019
,
Figure 595191DEST_PATH_IMAGE020
Be intrinsic carrier concentration,
Figure 2011102192375100001DEST_PATH_IMAGE021
Be the channel region doping content,
Figure 604605DEST_PATH_IMAGE022
Be thermal voltage,
Figure 2011102192375100001DEST_PATH_IMAGE023
Position for empty electrode;
Figure 809321DEST_PATH_IMAGE024
In the formula,
Figure 2011102192375100001DEST_PATH_IMAGE027
Figure 801734DEST_PATH_IMAGE028
Figure 2011102192375100001DEST_PATH_IMAGE029
Be the one dimension Potential Distributing,
Figure 982048DEST_PATH_IMAGE030
It is eigenwert;
Figure 2011102192375100001DEST_PATH_IMAGE031
Be n rank Bessel's functions;
Figure 674061DEST_PATH_IMAGE032
Be Bezier-Fourier coefficient, eigenwert satisfies:
Figure 2011102192375100001DEST_PATH_IMAGE033
2. the grid structure MOSFET threshold voltage analytic model that encloses according to claim 1 is characterized in that n=3.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102692543A (en) * 2012-06-01 2012-09-26 西安邮电大学 Method for extracting flat-band voltage and threshold voltage of MOSFET (metal-oxide-semiconductor field effect transistor) based on current generation of grid-control drain electrode
CN102779205A (en) * 2012-06-20 2012-11-14 上海华力微电子有限公司 Threshold voltage analytical model of short channel ring fence structure metal oxide semiconductor field effect transistor (MOSFET)
CN105005663A (en) * 2015-07-24 2015-10-28 集美大学 Resolving model for two-dimensional threshold voltage of body contact potential PD-SOI MOSFET, building method of resolving model for two-dimensional threshold voltage of body contact potential PD-SOI MOSFET and method for calculating threshold voltage
CN108388697A (en) * 2018-01-23 2018-08-10 华北水利水电大学 A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050027501A1 (en) * 2003-06-09 2005-02-03 Cadence Design Systems, Inc. Method and apparatus for modeling devices having different geometries
CN101464919A (en) * 2008-12-30 2009-06-24 上海集成电路研发中心有限公司 BSIM3 HCI reliability model used in MOSFET electrical simulation
CN101976283A (en) * 2010-10-21 2011-02-16 中国科学院上海微系统与信息技术研究所 Method for determining BSIMSOI4 (Berkeley Short-channel IGFET Model Silicon on Insulator 4) direct current model parameter

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050027501A1 (en) * 2003-06-09 2005-02-03 Cadence Design Systems, Inc. Method and apparatus for modeling devices having different geometries
CN101464919A (en) * 2008-12-30 2009-06-24 上海集成电路研发中心有限公司 BSIM3 HCI reliability model used in MOSFET electrical simulation
CN101976283A (en) * 2010-10-21 2011-02-16 中国科学院上海微系统与信息技术研究所 Method for determining BSIMSOI4 (Berkeley Short-channel IGFET Model Silicon on Insulator 4) direct current model parameter

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
《Solid-State and Integrated Circuit Technology(ICSICT),2010 10th IEEE International Conference on》 20101104 Guanghui Mei, et al 《A Threshold Voltage Model for the Surrounding -Gate MOSFETs》 1919-1921 1-2 , *
GUANGHUI MEI, ET AL: "《A Threshold Voltage Model for the Surrounding –Gate MOSFETs》", 《SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY(ICSICT),2010 10TH IEEE INTERNATIONAL CONFERENCE ON》, 4 November 2010 (2010-11-04), pages 1919 - 1921, XP031835418 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102692543A (en) * 2012-06-01 2012-09-26 西安邮电大学 Method for extracting flat-band voltage and threshold voltage of MOSFET (metal-oxide-semiconductor field effect transistor) based on current generation of grid-control drain electrode
CN102779205A (en) * 2012-06-20 2012-11-14 上海华力微电子有限公司 Threshold voltage analytical model of short channel ring fence structure metal oxide semiconductor field effect transistor (MOSFET)
CN105005663A (en) * 2015-07-24 2015-10-28 集美大学 Resolving model for two-dimensional threshold voltage of body contact potential PD-SOI MOSFET, building method of resolving model for two-dimensional threshold voltage of body contact potential PD-SOI MOSFET and method for calculating threshold voltage
CN105005663B (en) * 2015-07-24 2018-02-16 集美大学 A kind of body connects current potential PD SOI MOSFET Two Dimensional Thresholding voltage analytic modell analytical models and its method for building up and threshold voltage computational methods
CN108388697A (en) * 2018-01-23 2018-08-10 华北水利水电大学 A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models
CN108388697B (en) * 2018-01-23 2021-08-10 华北水利水电大学 Threshold voltage analysis method for MOSFET with asymmetric double-gate structure

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