CN108388697B - Threshold voltage analysis method for MOSFET with asymmetric double-gate structure - Google Patents

Threshold voltage analysis method for MOSFET with asymmetric double-gate structure Download PDF

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CN108388697B
CN108388697B CN201810081144.2A CN201810081144A CN108388697B CN 108388697 B CN108388697 B CN 108388697B CN 201810081144 A CN201810081144 A CN 201810081144A CN 108388697 B CN108388697 B CN 108388697B
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辛艳辉
袁合才
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North China University of Water Resources and Electric Power
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Abstract

The invention discloses a method for analyzing threshold voltage of an asymmetric double-gate MOSFET (metal-oxide-semiconductor field effect transistor), which obtains a certain boundary condition according to the characteristics of an asymmetric double-gate structure and a gradient doped channel. And (3) assuming that the front gate channel and the back gate channel are both in a weak inversion state, and calculating the surface potentials of the front gate and the back gate through a two-dimensional Poisson equation and boundary conditions on the basis of the assumption of parabolic approximation of the surface potential of the channel. On the basis, according to the definition of the threshold voltage, the analytical formula of the threshold voltage of the front gate and the back gate is obtained through derivation, wherein the smaller one of the threshold voltages of the front gate and the back gate is the analytical formula of the threshold voltage of the structure. The method can also be popularized to structures such as asymmetric double-gate uniformly-doped channels, symmetric double-gate gradient-doped channels and the like. The method has high precision and clear physical concept, and provides a rapid tool for simulation software in researching the double-gate field effect transistor device.

Description

Threshold voltage analysis method for MOSFET with asymmetric double-gate structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a threshold voltage analysis method of an asymmetric double-gate MOSFET.
Background
As the size of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices continues to decrease, MOSFET devices are subject to physical effects such as mobility degradation, short channel effects, and the like. In some current novel device structures, the double-gate device has more excellent properties, the control capability on a channel electric field is greatly enhanced, the sub-threshold slope is more ideal, and the carrier mobility is greatly improved. In addition, channel doping engineering is also applied to novel device structures. Therefore, the structure of the double-gate gradually-doped channel MOSFET device becomes more important, the asymmetric double-gate structure is a common form of the double-gate structure, and for the structure, an analytical model is established, and theoretical research and circuit simulation are necessary.
The threshold voltage is one of the most important electrical parameters of the MOS device, and the size of the threshold voltage is related to the frequency characteristic and the switching of the deviceCharacteristics, etc. all have important effects. For asymmetric double gate devices, the threshold voltage VthIs defined as: the gate-source voltage when one of the front gate channel or the back gate channel is just turned on and the other channel is not turned on, i.e. one of the front gate channel surface potential or the back gate channel surface potential is equal to 2 phif(φfFermi potential) to the corresponding gate-source voltage. It is necessary to establish an accurate analytical model of the threshold voltage to understand the electrical characteristics of the device.
Disclosure of Invention
In order to solve the above problems, the present invention provides a method for analyzing threshold voltage of an asymmetric double-gate MOSFET.
In order to achieve the purpose, the invention adopts the technical scheme that:
a threshold voltage analysis method of an asymmetric double-gate MOSFET comprises a front gate threshold voltage analysis method and a back gate threshold voltage analysis method, wherein the front gate threshold voltage analysis method comprises the following steps:
Figure GDA0003136163200000021
wherein the content of the first and second substances,
Figure GDA0003136163200000022
af＝2cosh(λ1L)-2-sinh2(λ1L)
bf＝[1-exp(λ1L)]·Vb1,f+[exp(-λ1L)-1]·Vb2,f+2sinh2(λ1L)·(U1,f+2ψF,Si)
cf＝Vb1,f·Vb2,f-sinh2(λ1L)·(U1,f+2ψF,Si)2
Vb1,f＝-(Vbi+U1,f)·exp(-λ1L)+(U1,f-U2,f)cosh(λ1(L-L1))+(Vbi+VDS+U2,f)
Vb2,f＝(Vbi+U1,f)·exp(λ1L)-(U1,f-U2,f)cosh(λ1(L-L1))-(Vbi+VDS+U2,f)
Figure GDA0003136163200000023
Figure GDA0003136163200000024
Figure GDA0003136163200000025
Figure GDA0003136163200000026
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1Is its length; n is a radical of2Representing the doping concentration of a high-doping area close to a drain terminal channel; vGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs the thermal voltage and q is the electric quantity of the electron. VFB,f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; vFB,f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;
effective gate voltage of a back gate close to a source end doped region: v'GS21＝VGS-VFB,b1；
Effective gate voltage of the back gate close to the drain terminal doped region: v'GS22＝VGS-VFB,b2；
Wherein, VFB,b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end; vFB,b2The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;
built-in potential between silicon channel and source:
Figure GDA0003136163200000031
in the formula, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons;
the analysis method of the back gate threshold voltage comprises the following steps:
Figure GDA0003136163200000032
wherein the content of the first and second substances,
Figure GDA0003136163200000033
ab＝2cosh(λ2L)-2-sinh2(λ2L)
bb＝[1-exp(λ2L)]·Vb1,b+[exp(-λ2L)-1]·Vb2,b+2sinh2(λ2L)·(U1,b+2ψF,Si)
cb＝Vb1,b·Vb2,b-sinh2(λ2L)·(U1,b+2ψF,Si)2
Vb1,b＝-(Vbi+U1,b)·exp(-λ2L)+(U1,b-U2,b)cosh(λ2(L-L1))+(Vbi+VDS+U2,b)
Vb2,b＝(Vbi+U1,b)·exp(λ2L)-(U1,b-U2,b)cosh(λ2(L-L1))-(Vbi+VDS+U2,b)
Figure GDA0003136163200000034
Figure GDA0003136163200000041
Figure GDA0003136163200000042
Figure GDA0003136163200000043
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1Is its length; n is a radical of2Representing the doping concentration of a high-doping area close to a drain terminal channel; vGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs the thermal voltage and q is the electric quantity of the electron. VFB,b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end; vFB,b2The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;
effective grid voltage of the front grid close to the source end doped region: v'GS11＝VGS-VFB,f1；
Effective grid voltage of a doped region of the front grid close to the drain end: v'GS12＝VGS-VFB,f2；
Wherein, VFB,f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; vFB,f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;
built-in potential between silicon channel and source:
Figure GDA0003136163200000044
in the formula, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
In the asymmetric double-gate device, the threshold voltage is the smaller of the threshold voltage of the front gate or the back gate:
Vth＝min(Vth,f,Vth,b)
a flat band voltage V between the back gate metal gate and the doped region of the silicon channel close to the source endFB,b1Calculated by the following formula:
Figure GDA0003136163200000051
flat band voltage V between back gate metal gate and doped region of silicon channel near drain terminalFB,b2Calculated by the following formula:
Figure GDA0003136163200000052
in the formula, phiM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
Flat band voltage V between the front gate metal gate and the doped region of the silicon channel near the source endFB,b1Calculated by the following formula:
Figure GDA0003136163200000053
flat band voltage V between the front gate metal gate and the doped region of the silicon channel near the drain terminalFB,f2Calculated by the following formula:
Figure GDA0003136163200000054
in the formula, phiM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
According to the characteristics of the asymmetric double-gate structure and the gradient doped channel, a certain boundary condition is obtained. And (3) assuming that the front gate channel and the back gate channel are both in a weak inversion state, and calculating the surface potentials of the front gate and the back gate through a two-dimensional Poisson equation and boundary conditions on the basis of the assumption of parabolic approximation of the surface potential of the channel. On the basis, according to the definition of the threshold voltage, the analytical formula of the threshold voltage of the front gate and the back gate is obtained through derivation, wherein the smaller one of the threshold voltages of the front gate and the back gate is the analytical formula of the threshold voltage of the structure. The method can also be popularized to structures such as asymmetric double-gate uniformly-doped channels, symmetric double-gate gradient-doped channels and the like. The method has high precision and clear physical concept, and provides a rapid tool for simulation software in researching the double-gate field effect transistor device.
Drawings
Fig. 1 is a diagram of an embodiment of an asymmetric double gate MOSFET according to the present invention.
Fig. 2 is a graph illustrating the variation of the threshold voltage of the front gate and the back gate with the channel length L.
FIG. 3 gradient doped channel (N)1＝1015cm-3，N2＝5×1016cm-3) And a uniformly doped channel (N)1＝N2＝1015cm-3) The threshold voltage comparison of (a) is shown.
Detailed Description
In order that the objects and advantages of the invention will be more clearly understood, the invention is further described in detail below with reference to examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In this embodiment, the conductive channel of the asymmetric dual-gate MOSFET adopts a graded doped silicon channel, the channel is divided into two regions, a portion near the source region is a low-doped region, and a portion near the drain region is a high-doped region. Neglecting the influence of the fixed oxide layer charge on the channel potential, when the front gate channel and the back gate channel are both in weak inversion, the potential distribution of the front gate channel and the potential distribution of the back gate channel can be expressed by a poisson equation:
Figure GDA0003136163200000061
Figure GDA0003136163200000062
Figure GDA0003136163200000063
Figure GDA0003136163200000071
wherein psi11(x,y1)、ψ12(x,y1) Are respectively N1Region, N2A front gate channel potential of the region; psi21(x,y2)、ψ22(x,y2) Are respectively N1Region, N2Region back gate channel potential. When the drain terminal is biased by VDSWhen the voltage is small, the longitudinal potentials of the front gate channel and the back gate channel are both approximated by a parabolic function,
ψ1j(x,y1)＝ψSj(x)+Cj1(x)y+Cj2(x)y1 2，j＝1,2 (5)
ψ2j(x,y2)＝ψBj(x)+Dj1(x)y+Dj2(x)y2 2，j＝1,2 (6)
ψSj(x)＝ψ1j(x,0), j ═ 1,2 are channels N, respectively1、N2Front gate channel surface potential of two doped regions, #Bj(x)＝ψ2j(x,0), j ═ 1,2 are channels N, respectively1、N2The back gate channel surface potentials of the two doped regions,
Cj1(x)、Cj2(x)、Dj1(x)、Dj2(x) Is a function related only to x.
The front gate channel surface potential and the back gate channel surface potential can be obtained by a two-dimensional poisson equation and boundary conditions, and the boundary conditions are as follows:
Figure GDA0003136163200000072
Figure GDA0003136163200000073
Figure GDA0003136163200000074
Figure GDA0003136163200000075
ψ11(L1,0)＝ψ12(L1,0) (11)
Figure GDA0003136163200000076
ψ21(L1,0)＝ψ22(L1,0) (13)
Figure GDA0003136163200000081
ψ11(0,0)＝ψS1(0)＝ψ21(0,0)＝ψB1(0)＝Vbi (15)
ψ12(L,0)＝ψS2(L)＝ψ22(L,0)＝ψB2(L)＝Vbi+VDS (16)
from the boundary conditions (7) to (10), coefficients C of (5) and (6) are obtainedj1(x)、Cj2(x)、Dj1(x)、Dj2(x) Is described in (1). And substituting the equations (5) and (6) into the equations (1) to (4), and enabling y to be 0, so as to obtain second-order equations of the surface potential of the front gate channel and the surface potential of the back gate channel respectively.
From the boundary conditions (11) - (16), the expression psi for the surface potential of the front gate channel and the surface potential of the back gate channel can be obtainedSj(x) And psiBj(x)。
The surface potential of the front gate channel is as follows:
ψSj(x)＝Aj exp(λ1x)+Bj exp(-λ1x)-ηj (17)
wherein eta isj＝β1j/λ1 2
Figure GDA0003136163200000082
Figure GDA0003136163200000083
Figure GDA0003136163200000084
Figure GDA0003136163200000085
Figure GDA0003136163200000086
Figure GDA0003136163200000087
The back gate channel surface potential is:
ψBj(x)＝Ej exp(λ2x)+Fj exp(-λ2x)-γj (18)
wherein the content of the first and second substances,
Figure GDA0003136163200000091
Figure GDA0003136163200000092
Figure GDA0003136163200000093
Figure GDA0003136163200000094
Figure GDA0003136163200000095
Figure GDA0003136163200000096
Figure GDA0003136163200000097
channel doping concentration N1＜N2With the minimum value of the channel surface potential at low doping N1And (4) a region. Order to
Figure GDA0003136163200000098
Minimum psi of surface potential of front gate trenchSminAnd the surface potential of back gate channelSmall value psiBmin。
Figure GDA0003136163200000099
Figure GDA00031361632000000910
According to the definition of the threshold voltage:
front gate threshold voltage Vth,fIs defined as psiSminEqual to 2 times the fermi potential of the lowly doped region, i.e.. psiSmin＝2ψF,SiThe gate-source voltage of time;
back gate threshold voltage Vth,bIs defined as psiBminEqual to 2 times the fermi potential of the lowly doped region, i.e.. psiBmin＝2ψF,SiThe gate-source voltage.
Wherein the content of the first and second substances,
Figure GDA00031361632000000911
and calculating to obtain the threshold voltage of the front gate and the back gate. For an asymmetric double-gate device, the threshold voltage of the asymmetric double-gate device is the smaller of the threshold voltages of a front gate or a back gate, namely: vth＝min(Vth,f,Vth,b)。
When N is present1＝N2When the structure is used, the front gate and back gate threshold voltage analytic expression is degenerated into a front gate and back gate threshold voltage analytic expression of the asymmetric double-gate uniformly-doped channel MOSFET, wherein the smaller one is the threshold voltage analytic expression of the structure; when M is1＝M2，t1＝t2When the structure is used, the disintegration is a front gate threshold voltage analytic expression and a back gate threshold voltage analytic expression of the symmetrical double-gate graded doped channel MOSFET, and the two are equal and are the structural threshold voltage analytic expression; when M is1＝M2，t1＝t2，N1＝N2When the threshold voltage is equal, the deciduation is the analytical formula of the threshold voltage of the front gate and the back gate of the symmetrical double-gate uniformly-doped channel MOSFET, and the analytical formula of the threshold voltage is the analytical formula of the threshold voltage of the structure.
The analytical formula of the front gate threshold voltage is as follows:
Figure GDA0003136163200000101
wherein the content of the first and second substances,
Figure GDA0003136163200000102
af＝2cosh(λ1L)-2-sinh2(λ1L)
bf＝[1-exp(λ1L)]·Vb1,f+[exp(-λ1L)-1]·Vb2,f+2sinh2(λ1L)·(U1,f+2ψF,Si)
cf＝Vb1,f·Vb2,f-sinh2(λ1L)·(U1,f+2ψF,Si)2
Vb1,f＝-(Vbi+U1,f)·exp(-λ1L)+(U1,f-U2,f)cosh(λ1(L-L1))+(Vbi+VDS+U2,f)
Vb2,f＝(Vbi+U1,f)·exp(λ1L)-(U1,f-U2,f)cosh(λ1(L-L1))-(Vbi+VDS+U2,f)
Figure GDA0003136163200000103
Figure GDA0003136163200000104
Figure GDA0003136163200000105
Figure GDA0003136163200000106
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer. The channel length L is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1Is its length; n is a radical of2Indicating the doping concentration of the highly doped region of the channel near the drain end. VGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs a thermal voltage;
effective gate voltage of a back gate close to a source end doped region: v'GS21＝VGS-VFB,b1
Effective gate voltage of the back gate close to the drain terminal doped region: v'GS22＝VGS-VFB,b2
VFB,b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end;
VFB,b2the flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal.
Figure GDA0003136163200000111
Figure GDA0003136163200000112
VFB,f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end;
VFB,f2the flat band voltage between the front gate metal gate and the doped region of the silicon channel near the drain terminal.
Figure GDA0003136163200000113
Figure GDA0003136163200000114
Built-in potential between silicon channel and source:
Figure GDA0003136163200000115
wherein phi isM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
The back gate threshold voltage has an analytical formula:
Figure GDA0003136163200000121
wherein the content of the first and second substances,
Figure GDA0003136163200000122
ab＝2cosh(λ2L)-2-sinh2(λ2L)
bb＝[1-exp(λ2L)]·Vb1,b+[exp(-λ2L)-1]·Vb2,b+2sinh2(λ2L)·(U1,b+2ψF,Si)
cb＝Vb1,b·Vb2,b-sinh2(λ2L)·(U1,b+2ψF,Si)2
Vb1,b＝-(Vbi+U1,b)·exp(-λ2L)+(U1,b-U2,b)cosh(λ2(L-L1))+(Vbi+VDS+U2,b)
Vb2,b＝(Vbi+U1,b)·exp(λ2L)-(U1,b-U2,b)cosh(λ2(L-L1))-(Vbi+VDS+U2,b)
Figure GDA0003136163200000123
Figure GDA0003136163200000124
Figure GDA0003136163200000125
effective grid voltage of the front grid close to the source end doped region: v'GS11＝VGS-VFB,f1
Effective grid voltage of a doped region of the front grid close to the drain end: v'GS12＝VGS-VFB,f2。
The parameters of the asymmetric double-gate MOSFET in this embodiment are chosen as follows,
the gate electrodes M1 and M2 respectively adopt work functions phiM1＝4.77eV、φM24.97eV metal material, lightly doped region N with channel doping concentration1＝1015cm-3Heavily doped region N2＝5×1016cm-3Doping concentration N of source and drainD＝1020cm-3The front gate dielectric layer and the back gate dielectric layer both adopt dielectric constant epsilonfHfO as high-k material of 202Thickness t of front gate dielectric layer11nm, back gate dielectric layer thickness t22nm, dielectric constant ε of siliconSi11.9eV, low doped region length L110nm and a channel length L of 40 nm.
The above parameters were chosen, resulting in fig. 2 and 3.
Fig. 2 obtains the analytical calculation results of the threshold voltages of the front gate and the back gate and the DESSIS simulation result. The threshold voltages of the front gate and the back gate calculated according to the analytic expression are basically consistent with the result obtained by DESSIS simulation software. The front gate threshold voltage is smaller and is the threshold voltage of the device.
As can be seen from fig. 3, for the uniformly doped channel MOSFET device, the threshold voltage has a significant drop with the decrease of the channel length when the channel length is less than 25nm, i.e., the short channel effect is more severe when the channel length is less than 25 nm. For a graded doped channel MOSFET device, the threshold voltage drops significantly as the channel length decreases when the channel length is less than 20 nm. Therefore, the device can better inhibit the short channel effect.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be construed as the protection scope of the present invention.

Claims (4)

1. The method for analyzing the threshold voltage of the MOSFET with the asymmetric double-gate structure is characterized by comprising a front gate threshold voltage analyzing method and a back gate threshold voltage analyzing method, wherein the front gate threshold voltage analyzing method comprises the following steps:
Figure FDA0003136163190000011
wherein the content of the first and second substances,
Figure FDA0003136163190000012
af＝2cosh(λ1L)-2-sinh2(λ1L)
bf＝[1-exp(λ1L)]·Vb1,f+[exp(-λ1L)-1]·Vb2,f+2sinh2(λ1L)·(U1,f+2ψF,Si)
cf＝Vb1,f·Vb2,f-sinh2(λ1L)·(U1,f+2ψF,Si)2
Vb1,f＝-(Vbi+U1,f)·exp(-λ1L)+(U1,f-U2,f)cosh(λ1(L-L1))+(Vbi+VDS+U2,f)
Vb2,f＝(Vbi+U1,f)·exp(λ1L)-(U1,f-U2,f)cosh(λ1(L-L1))-(Vbi+VDS+U2,f)
Figure FDA0003136163190000013
Figure FDA0003136163190000014
Figure FDA0003136163190000015
Figure FDA0003136163190000016
V′GS11＝VGS-VFB,f1；
V′GS12＝VGS-VFB,f2；
Figure FDA0003136163190000017
the analysis method of the back gate threshold voltage comprises the following steps:
Figure FDA0003136163190000021
wherein the content of the first and second substances,
Figure FDA0003136163190000022
ab＝2cosh(λ2L)-2-sinh2(λ2L)
bb＝[1-exp(λ2L)]·Vb1,b+[exp(-λ2L)-1]·Vb2,b+2sinh2(λ2L)·(U1,b+2ψF,Si)
cb＝Vb1,b·Vb2,b-sinh2(λ2L)·(U1,b+2ψF,Si)2
Vb1,b＝-(Vbi+U1,b)·exp(-λ2L)+(U1,b-U2,b)cosh(λ2(L-L1))+(Vbi+VDS+U2,b)
Vb2,b＝(Vbi+U1,b)·exp(λ2L)-(U1,b-U2,b)cosh(λ2(L-L1))-(Vbi+VDS+U2,b)
Figure FDA0003136163190000023
Figure FDA0003136163190000024
Figure FDA0003136163190000025
Figure FDA0003136163190000026
V′GS21＝VGS-VFB,b1
V′GS22＝VGS-VFB,b2
in the formula, Vth，fIs front gate threshold voltage, #F，SiIs the Fermi potential of silicon,. epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric，tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1The length of the low doped region close to the source end channel; n is a radical of2Representing the doping concentration of a high-doping area close to a drain terminal channel; vDSIs the drain-source voltage, VTIs thermal voltage, q is the electric quantity of electrons; vFB,f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; vFB,f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end; v'GS21The effective grid voltage of a back grid close to a source end doped region is obtained; v'GS22The effective grid voltage of the back grid close to the drain end doped region is obtained; v'GS11Is an effective grid voltage V 'of a front grid close to a source end doped region'GS12Effective grid voltage of a doped region of the front grid close to the drain end; vGSIs the gate-source voltage; vbiEstablishing an internal potential between the silicon channel and the source end; egIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si; vth，bIs the back gate threshold voltage, VFB,b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end; vFB,b2The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal.
2. The method for analyzing the threshold voltage of the MOSFET with the asymmetric double-gate structure as claimed in claim 1, wherein in the asymmetric double-gate device, the threshold voltage is the smaller of the threshold voltage of the front gate or the threshold voltage of the back gate:
Vth＝min(Vth,f,Vth,b)。
3. the method of claim 1, wherein a flat band voltage V between the back gate metal gate and the silicon channel near source end doped region is used for analyzing the threshold voltage of the MOSFET with the asymmetric double gate structureFB,b1Calculated by the following formula:
Figure FDA0003136163190000041
wherein chi is the electron affinity of the bulk silicon material; phi is aM2Work function for back gate metal gate;
flat band voltage V between back gate metal gate and doped region of silicon channel near drain terminalFB,b2Calculated by the following formula:
Figure FDA0003136163190000042
4. the method of claim 1, wherein the flat band voltage V between the front-gate metal gate and the silicon channel near-source doped region is VFB，f1Calculated by the following formula:
Figure FDA0003136163190000043
in the formula, phiM1Is the work function of the front gate metal gate; chi is the electron affinity of bulk silicon material;
flat band voltage V between the front gate metal gate and the doped region of the silicon channel near the drain terminalFB,f2Calculated by the following formula:
Figure FDA0003136163190000044
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