CN108388697A - A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models - Google Patents

Abstract

The invention discloses a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models, the characteristics of present invention is according to asymmetric double grid structure and gradient doping raceway groove, certain boundary condition is obtained.It is approximate based on channel surface gesture parabola it is assumed that by two-dimentional Poisson's equation and boundary condition assuming that preceding gate groove and backgate raceway groove are in weak anti-type state, calculate preceding canopy, backgate surface potential.On this basis, according to the definition of threshold voltage, be derived by the threshold voltage analytic modell analytical model of front gate, backgate, wherein front gate, backgate threshold voltage smaller be the threshold voltage analytic modell analytical model of the structure.The model can also be extended to the structures such as asymmetric double grid uniformly doped channel, symmetrical double grid uniformly doped channel, symmetrical double grid gradient doping raceway groove.Model accuracy height, clear physics conception, a kind of quick tool is provided for simulation softward when studying dual gate FET device.

Description

An Analytical Model of Threshold Voltage of MOSFET with Asymmetric Double Gate Structure

technical field

The invention relates to the technical field of semiconductors, in particular to an asymmetric double gate structure MOSFET threshold voltage analysis model.

Background technique

As the size of metal-oxide-semiconductor field-effect transistor (MOSFET) devices continues to decrease, MOSFET devices face some physical effects such as reduced mobility and short-channel effects. In some of the current new device structures, the double-gate device has more excellent properties, the ability to control the channel electric field is greatly enhanced, the subthreshold slope is more ideal, and the carrier mobility is greatly improved. In addition, channel doping engineering has also been applied to novel device structures. Therefore, the device structure of double-gate gradiently doped channel MOSFET becomes particularly important. Asymmetric double-gate structure is a common form of double-gate structure. For this structure, it is necessary to establish an analytical model, conduct theoretical research and circuit simulation.

Threshold voltage is one of the most important electrical parameters of MOS devices, and its magnitude will have an important impact on the frequency characteristics and switching characteristics of the device. For asymmetric double-gate devices, the threshold voltage _Vth is defined as: the gate-source voltage when one of the front gate channel or the back gate channel has just been turned on and the other channel has not been turned on, that is, the surface potential of the front gate channel or The corresponding gate-source voltage when one of the surface potentials of the back gate channel is equal to 2φ _f (φ _f is the Fermi potential). To understand the electrical characteristics of the device, it is necessary to establish an accurate analytical model of the threshold voltage.

Contents of the invention

In order to solve the above problems, the present invention provides an asymmetric double gate structure MOSFET threshold voltage analysis model.

In order to achieve the above object, the technical scheme that the present invention takes is:

An asymmetric dual-gate structure MOSFET threshold voltage analytical model, including a front gate threshold voltage model and a back gate threshold voltage model, the analytical formula of the front gate threshold voltage model is:

in,

a _f ＝2cosh(λ ₁ L)-2-sinh ² (λ ₁ L)

b _f =[1-exp(λ ₁ L)]·V _b1,f +[exp(-λ ₁ L)-1]·V _b2,f +2 sinh ² (λ ₁ L)·(U _1,f + 2ψ _{F, Si} )

c _f = V _{b1, f} · V _{b2, f} -sinh ² (λ ₁ L) · (U _{1, f} +2ψ _{F, Si} ) ²

V _b1,f ＝-(V _bi +U _1,f )·exp(-λ ₁ L)+(U _1,f -U _2,f )cosh(λ ₁ (LL ₁ ))+(V _bi +V _DS + U _{2, f} )

V _b2,f ＝(V _bi +U _1,f )·exp(λ ₁ L)-(U _1,f -U _2,f )cosh(λ ₁ (LL ₁ ))-(V _bi +V _DS + U2 _{, f} )

In the formula, ε _Si is the dielectric constant of silicon, ε _f is the dielectric constant of the gate dielectric, t _Si is the thickness of the silicon channel, t ₁ is the thickness of the front gate dielectric layer, and t ₂ is the back gate dielectric layer The thickness of the channel; L is the length of the channel, divided into two doped regions, N ₁ represents the doping concentration of the low-doped region near the source channel, L ₁ is its length; N ₂ represents the high channel near the drain The doping concentration of the doped region; V _GS is the gate-source voltage, V _DS is the drain-source voltage, V _T is the thermal voltage, and q is the electric quantity of electrons. V _{FB, f1} is the flat band voltage between the metal gate of the front gate and the doped region near the source end of the silicon channel; V _{FB, f2} is the flat band voltage between the metal gate of the front gate and the doped region of the silicon channel near the drain end Voltage;

The effective gate voltage of the doped region near the source end of the back gate: V′ _GS21 = V _GS -V _{FB, b1} ;

The effective gate voltage of the doped region of the back gate close to the drain: V' _GS22 = V _GS -V _{FB, b2} ;

Among them, V _{FB, b1} is the flat-band voltage between the back gate metal gate and the doped region of the silicon channel near the source end; V _{FB, b2} is the voltage between the back gate metal gate and the doped region of the silicon channel near the drain end flat band voltage;

Built-in potential between silicon channel and source:

In the formula, E _g is the bandgap width of bulk silicon material, n _i is the doping concentration of intrinsic Si, and q is the charge of electrons;

The analytical formula of the back gate threshold voltage model is:

in,

a _b ＝2cosh(λ ₂ L)-2-sinh ² (λ ₂ L)

b _b ＝[1-exp(λ ₂ L)]·V _b1,b +[exp(-λ ₂ L)-1]·V _b2,b +2 sinh ² (λ ₂ L)·(U _1,b + 2ψ _{F, Si} )

c _b ＝V _b1,b ·V _b2,b -sinh ² (λ ₂ L)·(U _1,b +2ψ _F,Si ) ²

V _b1,b ＝-(V _b1 +U _1,b )·exp(-λ ₂ L)+(U _1,b -U _2,b )cosh(λ ₂ (LL ₁ ))+(V _b1 +V _Ds + _U2,b )

V _b2,b ＝(V _bi +U _1,b )·exp(λ ₂ L)-(U _1,b -U _2,b )cosh(λ ₂ (LL ₁ ))-(V _b1 +V _DS + U2 _,b )

In the formula, ε _Si is the dielectric constant of silicon, ε _f is the dielectric constant of the gate dielectric, t _Si is the thickness of the silicon channel, t ₁ is the thickness of the front gate dielectric layer, and t ₂ is the back gate dielectric layer The thickness of the channel; L is the length of the channel, divided into two doped regions, N ₁ represents the doping concentration of the low-doped region near the source channel, L ₁ is its length; N ₂ represents the high channel near the drain The doping concentration of the doped region; V _GS is the gate-source voltage, V _DS is the drain-source voltage, V _T is the thermal voltage, and q is the electric quantity of electrons. V _{FB, b1} is the flat band voltage between the back gate metal gate and the doped region near the source end of the silicon channel; V _{FB, b2} is the flat band voltage between the back gate metal gate and the doped region near the drain end of the silicon channel Voltage;

The effective gate voltage of the doped region near the source end of the front gate: V′ _GS11 = V _GS -V _{FB, f1} ;

The effective gate voltage of the doped region near the drain end of the front gate: V′ _GS12 = V _GS -V _{FB, f2} ;

Among them, V _{FB, f1} is the flat-band voltage between the metal gate of the front gate and the doped region near the source end of the silicon channel; V _{FB, f2} is the voltage between the metal gate of the front gate and the doped region of the silicon channel near the drain end flat band voltage;

Built-in potential between silicon channel and source:

In the formula, E _g is the bandgap width of the bulk silicon material, _ni is the doping concentration of intrinsic Si, and q is the charge of electrons.

In an asymmetric dual-gate device, the threshold voltage is the smaller of the front-gate or back-gate threshold voltages:

V _{th =} min(V _{th, f} , V _{th, b} )

The flat-band voltage V _{FB, b1} between the metal gate of the back gate and the doped region near the source end of the silicon channel is calculated by the following formula:

The flat-band voltage V _{FB, b2} between the metal gate of the back gate and the doped region near the drain end of the silicon channel is calculated by the following formula:

In the formula, φ _M1 and φ _M2 are the work functions of the front gate metal gate and the back gate metal gate respectively; χ is the electron affinity of the bulk silicon material, E _g is the bandgap width of the bulk silicon material, and n _i is the intrinsic The doping concentration of Si, q is the charge of electrons.

The flat-band voltage V _{FB, b1} between the metal gate of the front gate and the doped region near the source end of the silicon channel is calculated by the following formula:

The flat-band voltage V _{FB, f2} between the metal gate of the front gate and the doped region near the drain end of the silicon channel is calculated by the following formula:

In the formula, φ _M1 and φ _M2 are the work functions of the front gate metal gate and the back gate metal gate respectively; χ is the electron affinity of the bulk silicon material, E _g is the bandgap width of the bulk silicon material, and n _i is the intrinsic The doping concentration of Si, q is the charge of electrons.

The invention obtains certain boundary conditions according to the characteristics of the asymmetrical double-gate structure and the gradually doped channel. Assuming that both the front gate channel and the back gate channel are in the weak inversion state, based on the assumption that the surface potential of the channel is approximated by a parabola, the surface potentials of the front gate and the back gate are calculated through the two-dimensional Poisson equation and boundary conditions. On this basis, according to the definition of threshold voltage, an analytical model of the threshold voltage of the front gate and the back gate is derived, and the threshold voltage of the front gate and the back gate is the smaller threshold voltage analytical model of the structure. This model can also be extended to structures such as asymmetric double-gate uniformly doped channel, symmetrical double-gate uniformly doped channel, and symmetrical double-gate gradually doped channel. The model has high accuracy and clear physical concept, which provides a fast tool for simulation software when studying dual-gate field-effect transistor devices.

Description of drawings

FIG. 1 is a specific embodiment of an asymmetric double-gate structure MOSFET in an embodiment of the present invention.

Fig. 2 Schematic diagram of the variation of the front gate and back gate threshold voltages with the trench length L.

Figure 3 Threshold voltage of graded doped channel (N ₁ =10 ¹⁵ cm ^-3 , N ₂ =5×10 ¹⁶ cm ^-3 ) and uniformly doped channel (N ₁ =N ₂ =10 ¹⁵ cm ^-3 ) Compare schematics.

Detailed ways

In order to make the objects and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

In this embodiment, the conduction channel of the asymmetric double-gate structure MOSFET adopts a graded doped silicon channel, and the channel is divided into two regions, the part near the source region is a low-doped region, and the part near the drain region is a highly doped region. Neglecting the influence of the fixed oxide layer charge on the channel potential, when both the front gate channel and the back gate channel are in weak inversion, the potential distribution of the front gate channel and the back gate channel can be expressed by the Poisson equation:

Among them, ψ ₁₁ (x, y ₁ ), ψ ₁₂ (x, y ₁ ) are the front gate channel potentials of N ₁ and N ₂ regions respectively; ψ ₂₁ (x, y ₂ ), ψ ₂₂ (x, y ₂ ) are the back gate channel potentials of the N ₁ region and the N ₂ region respectively. When the drain bias voltage V _DS is small, the longitudinal potentials of the front gate and back gate channels are approximated by parabolic functions,

ψ _1j (x, y ₁ ) = ψ _Sj (x) + C _j1 (x) y + C _j2 (x) y ₁ ² , j = 1, 2 (5)

ψ _2j (x, y ₂ ) = ψ _Bj (x) + D _j1 (x) y + D _j2 (x) y ₂ ² , j = 1, 2 (6)

ψ _Sj (x) = ψ _1j (x, 0), j = 1, 2 are the front gate channel surface potentials of the two doped regions of channel N ₁ and N ₂ respectively, ψ _Bj (x) = ψ _2j ( x, 0), j=1, 2 are the back gate channel surface potentials of the two doped regions of the channel N ₁ and N ₂ respectively, C _j1 (x), C _j2 (x), D _j1 (x), D _j2 (x) is a function related only to x.

The surface potential of the front-gate channel and the surface potential of the back-gate channel can be obtained from the two-dimensional Poisson equation and boundary conditions, and the boundary conditions are as follows:

ψ ₁₁ (L ₁ , 0) = ψ ₁₂ (L ₁ , 0) (11)

ψ ₂₁ (L ₁ , 0) = ψ ₂₂ (L ₁ , 0) (13)

ψ ₁₁ (0, 0) = ψ _S1 (0) = ψ ₂₁ (0, 0) = ψ _B1 (0) = V _b1 (15)

ψ ₁₂ (L, 0) = ψ _S2 (L) = ψ ₂₂ (L, 0) = ψ _B2 (L) = V _{b1 +} V _DS (16)

From the boundary conditions (7)-(10), the expressions of the coefficients C _j1 (x), C _j2 (x), D _j1 (x), and D _j2 (x) of (5) and (6) are obtained. Substituting (5) and (6) into equations (1)-(4), and setting y=0, the second-order equations of the surface potential of the front gate channel and the surface potential of the back gate channel can be obtained respectively.

From the boundary conditions (11)-(16), the expressions ψ _Sj (x) and ψ _Bj (x) of the surface potential of the front gate channel and the surface potential of the back gate channel can be solved.

The front gate channel surface potential is:

ψ _Sj (x)＝A _j exp(λ ₁ x)+B _j exp(-λ ₁ x)-η _j (17)

Among them, η _j =β _1j /λ ₁ ²

The surface potential of the back-gate channel is:

ψ _Bj (x)＝E _j exp(λ ₂ x)+F _j exp(-λ ₂ x)-γ _j (18)

in,

When the doping concentration of the channel is N ₁ <N ₂ , the minimum value of the surface potential of the channel is in the region of low doping N ₁ . make

and

The minimum value of the surface potential of the front gate channel ψ _Smin and the minimum value of the surface potential of the back gate channel ψ _Bmin can be obtained.

According to the definition of threshold voltage:

The front gate threshold voltage V _{th, f} is defined as the gate-source voltage when ψ _Smin is equal to twice the Fermi potential of the low-doped region, that is, ψ _Smin = 2ψ _{F, Si} ;

The back-gate threshold voltage V _th,b is defined as the gate-source voltage when ψ _Bmin is equal to twice the Fermi potential of the low-doped region, that is, ψ _Bmin = 2ψ _{F, Si} .

in,

Calculate the front gate and back gate threshold voltages. For an asymmetric double-gate device, its threshold voltage is the smaller of the threshold voltage of the front gate or the back gate, namely: V _th min(V _{th, f} , V _{th, b} ).

When N ₁ =N ₂ , the analytical model of the threshold voltage of the front gate and the back gate degenerates into the model of the threshold voltage of the front gate and the back gate of the asymmetric double-gate uniformly doped channel MOSFET, and the smaller one is the threshold value of the structure Voltage model; when M ₁ =M ₂ , t ₁ =t ₂ , it degenerates into the front gate and back gate threshold voltage models of the symmetrical double-gate gradient doped channel MOSFET, and the two are equal, which is the threshold voltage model of the structure; When M ₁ = M ₂ , t ₁ = t ₂ , N ₁ = N ₂ , it degenerates into the front gate and back gate threshold voltage model of symmetrical double-gate uniformly doped channel MOSFET, and the two are equal, which is the threshold voltage of the structure voltage model.

The analytical formula of the front gate threshold voltage model is:

in,

a _f ＝2cosh(λ ₁ L)-2-sinh ² (λ ₁ L)

b _f =[1-exp(λ ₁ L)]·V _b1,f +[exp(-λ ₁ L)-1]·V _b2,f +2 sinh ² (λ ₁ L)·(U _1,f + 2ψ _{F, Si} )

c _f = V _{b1, f} · V _{b2, f} -sinh ² (λ ₁ L) · (U _{1, f} +2ψ _{F, Si} ) ²

V _b1,f ＝-(V _bi +U _1,f )·exp(-λ ₁ L)+(U _1,f -U _2,f )cosh(λ ₁ (LL ₁ ))+(V _bi +V _DS + U _{2, f} )

V _b2,f ＝(V _bi +U _1,f )·exp(λ ₁ L)-(U _1,f -U _2,f )cosh(λ ₁ (LL ₁ ))-(V _bi +V _DS + U2 _{, f} )

In the formula, ε _Si is the dielectric constant of silicon, ε _f is the dielectric constant of the gate dielectric, t _Si is the thickness of the silicon channel, t ₁ is the thickness of the front gate dielectric layer, and t ₂ is the back gate dielectric layer thickness of. The channel length L is divided into two doped regions, N ₁ represents the doping concentration of the low doped region near the source channel, L ₁ is its length; N ₂ represents the doping concentration of the highly doped region near the drain channel . V _GS is the gate-source voltage, V _DS is the drain-source voltage, and V _T is the thermal voltage;

The effective gate voltage of the doped region near the source end of the back gate: V' _GS21 = V _GS -V _{FB, b1}

The effective gate voltage of the doped region of the back gate close to the drain: V' _GS22 = V _GS -V _{FB, b2}

V _{FB, b1} is the flat-band voltage between the metal gate of the back gate and the doped region of the silicon channel near the source;

V _{FB, b2} is the flat-band voltage between the metal gate of the back gate and the doped region near the drain end of the silicon channel.

V _{FB, f1} is the flat-band voltage between the metal gate of the front gate and the doped region near the source end of the silicon channel;

V _{FB, f2} is the flat-band voltage between the metal gate of the front gate and the doped region near the drain end of the silicon channel.

Built-in potential between silicon channel and source:

Among them, φ _M1 and φ _M2 are the work functions of the front gate metal gate and the back gate metal gate respectively; χ is the electron affinity of the bulk silicon material, E _g is the bandgap width of the bulk silicon material, and n _i is the intrinsic Si The doping concentration of , q is the charge of electrons.

The analytical formula of the back gate threshold voltage model is:

in,

a _b ＝2cosh(λ ₂ L)-2-sinh ² (λ ₂ L)

b _b ＝[1-exp(λ ₂ L)]·V _b1,b +[exp(-λ ₂ L)-1]·V _b2,b +2 sinh ² (λ ₂ L)·(U _1,b + 2ψ _{F, Si} )

c _b ＝V _b1,b ·V _b2,b -sinh ² (λ ₂ L)·(U _1,b +2ψ _F,Si ) ²

V _b1,b ＝-(V _b1 +U _1,b )·exp(-λ ₂ L)+(U _1,b -U _2,b )cosh(λ ₂ (LL ₁ ))+(V _b1 +V _DS + U _2,b )

V _b2,b ＝(V _b1 +U _1,b )·exp(λ ₂ L)-(U _1,b -U _2,b )cosh(λ ₂ (LL ₁ ))-(V _bi +V _DS + U2 _,b )

The effective gate voltage of the doped region near the source end of the front gate: V' _GS11 = V _GS -V _{FB, f1}

The effective gate voltage of the doped region near the drain end of the front gate: V′ _GS12 =V _GS −V _FB,f2 .

In this specific implementation, the parameters of the asymmetric dual-gate MOSFET are selected as follows,

The gate electrodes M1 and M2 are respectively made of metal materials with work functions φ _M1 = 4.77eV and φ _M2 = 4.97eV, the channel doping concentration is lightly doped region N ₁ =10 ¹⁵ cm ^-3 , and heavily doped region N ₂ =5 ×10 ¹⁶ cm ^-3 , source-drain doping concentration _ND = 10 ²⁰ cm ^-3 , both the front gate dielectric layer and the back gate dielectric layer are made of high-k material HfO ₂ with a dielectric constant ε _f = 20, the front gate Gate dielectric layer thickness t ₁ =1nm, back gate dielectric layer thickness t ₂ =2nm, silicon dielectric constant ε _Si =11.9eV, low doped region length L ₁ =10nm, trench length L=40nm.

After selecting the above parameters, Figure 2 and Figure 3 are obtained.

Figure 2 shows the model calculation results and DESSIS simulation results of the front gate and back gate threshold voltages. The threshold voltages of the front gate and back gate calculated according to the model are basically consistent with the results obtained by the DESSIS simulation software. The threshold voltage of the front gate is smaller, which is the threshold voltage of the device.

It can be seen from Figure 3 that for a uniformly doped channel MOSFET device, when the channel length is less than 25nm, the threshold voltage drops significantly with the decrease of the channel length, that is, when the channel length is less than 25nm, the short channel effect More serious. For graded doped channel MOSFET devices, when the channel length is less than 20nm, the threshold voltage drops significantly with the decrease of the channel length. Therefore, the device can better suppress the short channel effect.

The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be It is regarded as the protection scope of the present invention.

Claims (4)

1. The threshold voltage analytical model of the asymmetric double-gate MOSFET is characterized by comprising a front gate threshold voltage model and a back gate threshold voltage model, wherein the analytical formula of the front gate threshold voltage model is as follows:

wherein,

a_f＝2cosh(λ₁L)-2-sinh²(λ₁L)

b_f＝[1-exp(λ₁L)]·V_b1，f+[exp(-λ₁L)-1]·V_b2，f+2sinh²(λ₁L)·(U_1，f+2ψ_F，Si)

c_f＝V_b1，f·V_b2，f-sinh²(λ₁L)·(U_1，f+2ψ_F，Si)²

V_b1，f＝-(V_bi+U_1，f)·exp(-λ₁L)+(U_1，f-U_2，f)cosh(λ₁(L-L₁))+(V_bi+V_DS+U_2，f)

V_b2，f＝(V_bi+U_1，f)·exp(λ₁L)-(U_1，f-U_2，f)cosh(λ₁(L-L₁))-(V_bi+V_DS+U_2，f)

in the formula, epsilon_SiIs the dielectric constant of silicon,. epsilon_fIs the dielectric constant of the gate dielectric, t_SiIs the thickness of the silicon channel, t₁Is the thickness of the front gate dielectric layer, t₂The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N₁Indicating doping near the source channel lowly doped regionConcentration, L₁Is its length; n is a radical of₂Representing the doping concentration of a high-doping area close to a drain terminal channel; v_GSIs a gate-source voltage, V_DSIs the drain-source voltage, V_TIs the thermal voltage and q is the electric quantity of the electron. V_FB，f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; v_FB，f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;

effective gate voltage of a back gate close to a source end doped region: v'_GS21＝V_GS-V_FB，b1；

Effective gate voltage of the back gate close to the drain terminal doped region: v'_GS22＝V_GS-V_FB，b2；

Wherein, V_FB，b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end; v_FB，b2The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;

built-in potential between silicon channel and source:

in the formula, E_gIs the forbidden band width, n, of bulk silicon material_iIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons;

the analytical formula of the back gate threshold voltage model is as follows:

wherein,

a_b＝2cosh(λ₂L)-2-sinh²(λ₂L)

b_b＝[1-exp(λ₂L)]·V_b1，b+[exp(-λ₂L)-1]·V_b2，b+2sinh²(λ₂L)·(U_1，b+2ψ_F，Si)

c_b＝V_b1，b·V_b2，b-sinh²(λ₂L)·(U_1，b+2ψ_F，Si)²

V_b1，b＝-(V_bi+U_1，b)·exp(-λ₂L)+(U_1，b-U_2，b)cosh(λ₂(L-L₁))+(V_bi+V_DS+U_2，b)

V_b2，b＝(V_bi+U_1，b)·exp(λ₂L)-(U_1，b-U_2，b)cosh(λ₂(L-L₁))-(V_bi+V_DS+U_2，b)

in the formula, epsilon_SiIs the dielectric constant of silicon,. epsilon_fIs the dielectric constant of the gate dielectric, t_SiIs the thickness of the silicon channel, t₁Is the thickness of the front gate dielectric layer, t₂The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N₁Represents the doping concentration, L, of the low doped region close to the source channel₁Is its length; n is a radical of₂Representing the doping concentration of a high-doping area close to a drain terminal channel; v_GSIs a gate-source voltage, V_DSIs the drain-source voltage, V_TIs the thermal voltage and q is the electric quantity of the electron. V_FB，b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end;V_FB，b2the flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;

effective grid voltage of the front grid close to the source end doped region: v'_GS11＝V_GS-V_FB，f1；

Effective grid voltage of a doped region of the front grid close to the drain end: v'_GS12＝V_GS-V_FB，f2；

Wherein, V_FB，f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; v_FB，f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;

built-in potential between silicon channel and source:

in the formula, E_gIs the forbidden band width, n, of bulk silicon material_iIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.

2. The analytical model of threshold voltage of the asymmetric double-gate MOSFET in claim 1, wherein in the asymmetric double-gate device, the threshold voltage is the smaller of the threshold voltage of the front gate or the threshold voltage of the back gate:

V_th＝min(V_th，f，V_th，b)

3. the analytical model for threshold voltage of MOSFET with asymmetric double gate structure as claimed in claim 1, wherein the flat band voltage V between the back gate metal gate and the doped region of silicon channel close to the source end is V_FB，b1Calculated by the following formula:

flat band voltage V between back gate metal gate and doped region of silicon channel near drain terminal_FB，b2Calculated by the following formula:

in the formula, phi_M1、φ_M2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, E_gIs the forbidden band width, n, of bulk silicon material_iIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.

4. The analytical model for threshold voltage of MOSFET with asymmetric double gate structure as claimed in claim 1, wherein the flat band voltage V between the front gate metal gate and the doped region of silicon channel near the source end is V_FB，b1Calculated by the following formula:

flat band voltage V between the front gate metal gate and the doped region of the silicon channel near the drain terminal_FB，f2Calculated by the following formula:

in the formula, phi_M1、φ_M2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, E_gIs the forbidden band width, n, of bulk silicon material_iIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.