CN108388697A - A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models - Google Patents
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Abstract
The invention discloses a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models, the characteristics of present invention is according to asymmetric double grid structure and gradient doping raceway groove, certain boundary condition is obtained.It is approximate based on channel surface gesture parabola it is assumed that by two-dimentional Poisson's equation and boundary condition assuming that preceding gate groove and backgate raceway groove are in weak anti-type state, calculate preceding canopy, backgate surface potential.On this basis, according to the definition of threshold voltage, be derived by the threshold voltage analytic modell analytical model of front gate, backgate, wherein front gate, backgate threshold voltage smaller be the threshold voltage analytic modell analytical model of the structure.The model can also be extended to the structures such as asymmetric double grid uniformly doped channel, symmetrical double grid uniformly doped channel, symmetrical double grid gradient doping raceway groove.Model accuracy height, clear physics conception, a kind of quick tool is provided for simulation softward when studying dual gate FET device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an asymmetric double-gate structure MOSFET threshold voltage analytic model.
Background
As the size of Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices continues to decrease, MOSFET devices are subject to physical effects such as mobility degradation, short channel effects, and the like. In some current novel device structures, the double-gate device has more excellent properties, the control capability on a channel electric field is greatly enhanced, the sub-threshold slope is more ideal, and the carrier mobility is greatly improved. In addition, channel doping engineering is also applied to novel device structures. Therefore, the structure of the double-gate gradually-doped channel MOSFET device becomes more important, the asymmetric double-gate structure is a common form of the double-gate structure, and for the structure, an analytical model is established, and theoretical research and circuit simulation are necessary.
The threshold voltage is one of the very important electrical parameters of the MOS device, and the size of the threshold voltage has an important influence on the frequency characteristics, the switching characteristics, and the like of the device. For asymmetric double gate devices, the threshold voltage VthIs defined as: the gate-source voltage when one of the front gate channel or the back gate channel is just turned on and the other channel is not turned on, i.e. one of the front gate channel surface potential or the back gate channel surface potential is equal to 2 phif(φfFermi potential) to the corresponding gate-source voltage. It is necessary to establish an accurate analytical model of the threshold voltage to understand the electrical characteristics of the device.
Disclosure of Invention
In order to solve the problems, the invention provides an analytical model of threshold voltage of an asymmetric double-gate MOSFET.
In order to achieve the purpose, the invention adopts the technical scheme that:
an analytical model of threshold voltage of an asymmetric double-gate MOSFET comprises a front gate threshold voltage model and a back gate threshold voltage model, wherein the analytical formula of the front gate threshold voltage model is as follows:
wherein,
af＝2cosh(λ1L)-2-sinh2(λ1L)
bf＝[1-exp(λ1L)]·Vb1，f+[exp(-λ1L)-1]·Vb2，f+2sinh2(λ1L)·(U1，f+2ψF，Si)
cf＝Vb1，f·Vb2，f-sinh2(λ1L)·(U1，f+2ψF，Si)2
Vb1，f＝-(Vbi+U1，f)·exp(-λ1L)+(U1，f-U2，f)cosh(λ1(L-L1))+(Vbi+VDS+U2，f)
Vb2，f＝(Vbi+U1，f)·exp(λ1L)-(U1，f-U2，f)cosh(λ1(L-L1))-(Vbi+VDS+U2，f)
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1Is its length; n is a radical of2Representing the doping concentration of a high-doping area close to a drain terminal channel; vGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs the thermal voltage and q is the electric quantity of the electron. VFB，f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; vFB，f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;
effective gate voltage of a back gate close to a source end doped region: v'GS21＝VGS-VFB，b1；
Effective gate voltage of the back gate close to the drain terminal doped region: v'GS22＝VGS-VFB，b2；
Wherein, VFB，b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end; vFB，b2The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;
built-in potential between silicon channel and source:
in the formula, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons;
the analytical formula of the back gate threshold voltage model is as follows:
wherein,
ab＝2cosh(λ2L)-2-sinh2(λ2L)
bb＝[1-exp(λ2L)]·Vb1，b+[exp(-λ2L)-1]·Vb2，b+2sinh2(λ2L)·(U1，b+2ψF，Si)
cb＝Vb1，b·Vb2，b-sinh2(λ2L)·(U1，b+2ψF，Si)2
Vb1，b＝-(Vb1+U1，b)·exp(-λ2L)+(U1，b-U2，b)cosh(λ2(L-L1))+(Vb1+VDs+U2，b)
Vb2，b＝(Vbi+U1，b)·exp(λ2L)-(U1，b-U2，b)cosh(λ2(L-L1))-(Vb1+VDS+U2，b)
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1Is its length; n is a radical of2Representing the doping concentration of a high-doping area close to a drain terminal channel; vGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs the thermal voltage and q is the electric quantity of the electron. VFB，b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end; vFB，b2The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;
effective grid voltage of the front grid close to the source end doped region: v'GS11＝VGS-VFB，f1；
Effective grid voltage of a doped region of the front grid close to the drain end: v'GS12＝VGS-VFB，f2；
Wherein, VFB，f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; vFB，f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;
built-in potential between silicon channel and source:
in the formula, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
In the asymmetric double-gate device, the threshold voltage is the smaller of the threshold voltage of the front gate or the back gate:
Vth＝min(Vth，f，Vth，b)
a flat band voltage V between the back gate metal gate and the doped region of the silicon channel close to the source endFB，b1Calculated by the following formula:
flat band voltage V between back gate metal gate and doped region of silicon channel near drain terminalFB，b2Calculated by the following formula:
in the formula, phiM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
Flat band voltage V between the front gate metal gate and the doped region of the silicon channel near the source endFB，b1Calculated by the following formula:
flat band voltage V between the front gate metal gate and the doped region of the silicon channel near the drain terminalFB，f2Calculated by the following formula:
in the formula, phiM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
According to the characteristics of the asymmetric double-gate structure and the gradient doped channel, a certain boundary condition is obtained. And (3) assuming that the front gate channel and the back gate channel are both in a weak inversion state, and calculating the surface potentials of the front gate and the back gate through a two-dimensional Poisson equation and boundary conditions on the basis of the assumption of parabolic approximation of the surface potential of the channel. On the basis, according to the definition of the threshold voltage, the threshold voltage analysis model of the front gate and the back gate is obtained through derivation, wherein the smaller of the threshold voltage of the front gate and the back gate is the threshold voltage analysis model of the structure. The model can also be popularized in structures such as asymmetric double-gate uniformly-doped channels, symmetric double-gate gradient-doped channels and the like. The model has high precision and clear physical concept, and provides a rapid tool for simulation software in researching the double-gate field effect transistor device.
Drawings
Fig. 1 is a diagram of an embodiment of an asymmetric double gate MOSFET according to the present invention.
Fig. 2 is a graph illustrating the variation of the threshold voltage of the front gate and the back gate with the channel length L.
FIG. 3 gradient doped channel (N)1＝1015cm-3，N2＝5×1016cm-3) And a uniformly doped channel (N)1＝N2＝1015cm-3) The threshold voltage comparison of (a) is shown.
Detailed Description
In order that the objects and advantages of the invention will be more clearly understood, the invention is further described in detail below with reference to examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In this embodiment, the conductive channel of the asymmetric dual-gate MOSFET adopts a graded doped silicon channel, the channel is divided into two regions, a portion near the source region is a low-doped region, and a portion near the drain region is a high-doped region. Neglecting the influence of the fixed oxide layer charge on the channel potential, when the front gate channel and the back gate channel are both in weak inversion, the potential distribution of the front gate channel and the potential distribution of the back gate channel can be expressed by a poisson equation:
wherein psi11(x，y1)、ψ12(x，y1) Are respectively N1Region, N2A front gate channel potential of the region; psi21(x，y2)、ψ22(x，y2) Are respectively N1Region, N2Region back gate channel potential. When the drain terminal is biased by VDSWhen the voltage is small, the longitudinal potentials of the front gate channel and the back gate channel are both approximated by a parabolic function,
ψ1j(x，y1)＝ψSj(x)+Cj1(x)y+Cj2(x)y1 2，j＝1，2 (5)
ψ2j(x，y2)＝ψBj(x)+Dj1(x)y+Dj2(x)y2 2，j＝1，2 (6)
ψSj(x)＝ψ1j(x, 0), j ═ 1, 2 are channels N, respectively1、N2Front gate channel surface potential of two doped regions, #Bj(x)＝ψ2j(x, 0), j ═ 1, 2 are channels N, respectively1、N2Back gate channel surface potential, C, of two doped regionsj1(x)、Cj2(x)、Dj1(x)、Dj2(x) Is a function related only to x.
The front gate channel surface potential and the back gate channel surface potential can be obtained by a two-dimensional poisson equation and boundary conditions, and the boundary conditions are as follows:
ψ11(L1，0)＝ψ12(L1，0) (11)
ψ21(L1，0)＝ψ22(L1，0) (13)
ψ11(0，0)＝ψS1(0)＝ψ21(0，0)＝ψB1(0)＝Vb1(15)
ψ12(L，0)＝ψS2(L)＝ψ22(L，0)＝ψB2(L)＝Vb1+VDS(16)
from the boundary conditions (7) to (10), coefficients C of (5) and (6) are obtainedj1(x)、Cj2(x)、Dj1(x)、Dj2(x) Is described in (1). And substituting the equations (5) and (6) into the equations (1) to (4), and enabling y to be 0, so as to obtain second-order equations of the surface potential of the front gate channel and the surface potential of the back gate channel respectively.
From the boundary conditions (11) - (16), the expression psi for the surface potential of the front gate channel and the surface potential of the back gate channel can be obtainedSj(x) And psiBj(x)。
The surface potential of the front gate channel is as follows:
ψSj(x)＝Ajexp(λ1x)+Bjexp(-λ1x)-ηj(17)
wherein, ηj＝β1j/λ1 2
The back gate channel surface potential is:
ψBj(x)＝Ejexp(λ2x)+Fjexp(-λ2x)-γj(18)
wherein,
channel doping concentration N1＜N2With the minimum value of the channel surface potential at low doping N1And (4) a region. Order to
And
minimum psi of surface potential of front gate trenchSminAnd back gate channel surface potential minimum psiBmin。
According to the definition of the threshold voltage:
front gate threshold voltage Vth，fIs defined as psiSminEqual to 2 times the fermi potential of the lowly doped region, i.e.. psiSmin＝2ψF，SiThe gate-source voltage of time;
back gate threshold voltage Vth，bIs defined as psiBminEqual to 2 times the fermi potential of the lowly doped region, i.e.. psiBmin＝2ψF，SiThe gate-source voltage.
Wherein,
and calculating to obtain the threshold voltage of the front gate and the back gate. For an asymmetric double-gate device, the threshold voltage of the asymmetric double-gate device is the smaller of the threshold voltages of a front gate or a back gate, namely: vthmin(Vth，f，Vth，b)。
When N is present1＝N2When the threshold voltage analytical model of the front gate and the back gate is degraded into a threshold voltage model of the front gate and the back gate of the asymmetric double-gate uniformly-doped channel MOSFET, wherein the smaller one is the threshold voltage model of the structure; when M is1＝M2，t1＝t2When the threshold voltage model is generated, the threshold voltage model is transformed into a front gate threshold voltage model and a back gate threshold voltage model of the symmetrical double-gate graded doped channel MOSFET, and the two threshold voltage models are equal and are the structural threshold voltage model; when M is1＝M2，t1＝t2，N1＝N2And when the voltage is reduced, the threshold voltage models of the front gate and the back gate of the symmetrical double-gate uniformly-doped channel MOSFET are obtained, and the two are equal and are the structural threshold voltage model.
The analytical formula of the front gate threshold voltage model is as follows:
wherein,
af＝2cosh(λ1L)-2-sinh2(λ1L)
bf＝[1-exp(λ1L)]·Vb1，f+[exp(-λ1L)-1]·Vb2，f+2sinh2(λ1L)·(U1，f+2ψF，Si)
cf＝Vb1，f·Vb2，f-sinh2(λ1L)·(U1，f+2ψF，Si)2
Vb1，f＝-(Vbi+U1，f)·exp(-λ1L)+(U1，f-U2，f)cosh(λ1(L-L1))+(Vbi+VDS+U2，f)
Vb2，f＝(Vbi+U1，f)·exp(λ1L)-(U1，f-U2，f)cosh(λ1(L-L1))-(Vbi+VDS+U2，f)
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer. The channel length L is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1Is its length; n is a radical of2Indicating the doping concentration of the highly doped region of the channel near the drain end. VGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs a thermal voltage;
effective gate voltage of a back gate close to a source end doped region: v'GS21＝VGS-VFB，b1
Effective gate voltage of the back gate close to the drain terminal doped region: v'GS22＝VGS-VFB，b2
VFB，b1For back gate metal gate and silicon channelA flat band voltage between the doped regions near the source;
VFB，b2the flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal.
VFB，f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end;
VFB，f2the flat band voltage between the front gate metal gate and the doped region of the silicon channel near the drain terminal.
Built-in potential between silicon channel and source:
wherein phi isM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
The analytical formula of the back gate threshold voltage model is as follows:
wherein,
ab＝2cosh(λ2L)-2-sinh2(λ2L)
bb＝[1-exp(λ2L)]·Vb1，b+[exp(-λ2L)-1]·Vb2，b+2sinh2(λ2L)·(U1，b+2ψF，Si)
cb＝Vb1，b·Vb2，b-sinh2(λ2L)·(U1，b+2ψF，Si)2
Vb1，b＝-(Vb1+U1，b)·exp(-λ2L)+(U1，b-U2，b)cosh(λ2(L-L1))+(Vb1+VDS+U2，b)
Vb2，b＝(Vb1+U1，b)·exp(λ2L)-(U1，b-U2，b)cosh(λ2(L-L1))-(Vbi+VDS+U2，b)
effective grid voltage of the front grid close to the source end doped region: v'GS11＝VGS-VFB，f1
Effective grid voltage of a doped region of the front grid close to the drain end: v'GS12＝VGS-VFB，f2。
The parameters of the asymmetric double-gate MOSFET in this embodiment are chosen as follows,
the gate electrodes M1 and M2 respectively adopt work functions phiM1＝4.77eV、φM24.97eV metal material, lightly doped region N with channel doping concentration1＝1015cm-3Heavily doped region N2＝5×1016cm-3Doping concentration N of source and drainD＝1020cm-3The front gate dielectric layer and the back gate dielectric layer both adopt dielectric constant epsilonfHfO as high-k material of 202Thickness t of front gate dielectric layer11nm, back gate dielectric layer thickness t22nm, dielectric constant ε of siliconSi11.9eV, low doped region length L110nm and a channel length L of 40 nm.
The above parameters were chosen, resulting in fig. 2 and 3.
Fig. 2 obtains model calculation results of the threshold voltages of the front gate and the back gate and the DESSIS simulation results. The threshold voltage of the front gate and the back gate calculated according to the model is basically consistent with the result obtained by DESSIS simulation software. The front gate threshold voltage is smaller and is the threshold voltage of the device.
As can be seen from fig. 3, for the uniformly doped channel MOSFET device, the threshold voltage has a significant drop with the decrease of the channel length when the channel length is less than 25nm, i.e., the short channel effect is more severe when the channel length is less than 25 nm. For a graded doped channel MOSFET device, the threshold voltage drops significantly as the channel length decreases when the channel length is less than 20 nm. Therefore, the device can better inhibit the short channel effect.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be construed as the protection scope of the present invention.
Claims (4)
1. The threshold voltage analytical model of the asymmetric double-gate MOSFET is characterized by comprising a front gate threshold voltage model and a back gate threshold voltage model, wherein the analytical formula of the front gate threshold voltage model is as follows:
wherein,
af＝2cosh(λ1L)-2-sinh2(λ1L)
bf＝[1-exp(λ1L)]·Vb1，f+[exp(-λ1L)-1]·Vb2，f+2sinh2(λ1L)·(U1，f+2ψF，Si)
cf＝Vb1，f·Vb2，f-sinh2(λ1L)·(U1，f+2ψF，Si)2
Vb1，f＝-(Vbi+U1，f)·exp(-λ1L)+(U1，f-U2，f)cosh(λ1(L-L1))+(Vbi+VDS+U2，f)
Vb2，f＝(Vbi+U1，f)·exp(λ1L)-(U1，f-U2，f)cosh(λ1(L-L1))-(Vbi+VDS+U2，f)
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N1Indicating doping near the source channel lowly doped regionConcentration, L1Is its length; n is a radical of2Representing the doping concentration of a high-doping area close to a drain terminal channel; vGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs the thermal voltage and q is the electric quantity of the electron. VFB，f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; vFB，f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;
effective gate voltage of a back gate close to a source end doped region: v'GS21＝VGS-VFB，b1；
Effective gate voltage of the back gate close to the drain terminal doped region: v'GS22＝VGS-VFB，b2；
Wherein, VFB，b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end; vFB，b2The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;
built-in potential between silicon channel and source:
in the formula, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons;
the analytical formula of the back gate threshold voltage model is as follows:
wherein,
ab＝2cosh(λ2L)-2-sinh2(λ2L)
bb＝[1-exp(λ2L)]·Vb1，b+[exp(-λ2L)-1]·Vb2，b+2sinh2(λ2L)·(U1，b+2ψF，Si)
cb＝Vb1，b·Vb2，b-sinh2(λ2L)·(U1，b+2ψF，Si)2
Vb1，b＝-(Vbi+U1，b)·exp(-λ2L)+(U1，b-U2，b)cosh(λ2(L-L1))+(Vbi+VDS+U2，b)
Vb2，b＝(Vbi+U1，b)·exp(λ2L)-(U1，b-U2，b)cosh(λ2(L-L1))-(Vbi+VDS+U2，b)
in the formula, epsilonSiIs the dielectric constant of silicon,. epsilonfIs the dielectric constant of the gate dielectric, tSiIs the thickness of the silicon channel, t1Is the thickness of the front gate dielectric layer, t2The thickness of the back gate dielectric layer; l is the length of the channel and is divided into two doped regions, N1Represents the doping concentration, L, of the low doped region close to the source channel1Is its length; n is a radical of2Representing the doping concentration of a high-doping area close to a drain terminal channel; vGSIs a gate-source voltage, VDSIs the drain-source voltage, VTIs the thermal voltage and q is the electric quantity of the electron. VFB，b1The flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the source end;VFB，b2the flat band voltage between the back gate metal gate and the doped region of the silicon channel close to the drain terminal is obtained;
effective grid voltage of the front grid close to the source end doped region: v'GS11＝VGS-VFB，f1；
Effective grid voltage of a doped region of the front grid close to the drain end: v'GS12＝VGS-VFB，f2；
Wherein, VFB，f1Flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the source end; vFB，f2The flat band voltage between the front gate metal gate and the doped region of the silicon channel close to the drain end;
built-in potential between silicon channel and source:
in the formula, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
2. The analytical model of threshold voltage of the asymmetric double-gate MOSFET in claim 1, wherein in the asymmetric double-gate device, the threshold voltage is the smaller of the threshold voltage of the front gate or the threshold voltage of the back gate:
Vth＝min(Vth，f，Vth，b)
3. the analytical model for threshold voltage of MOSFET with asymmetric double gate structure as claimed in claim 1, wherein the flat band voltage V between the back gate metal gate and the doped region of silicon channel close to the source end is VFB，b1Calculated by the following formula:
flat band voltage V between back gate metal gate and doped region of silicon channel near drain terminalFB，b2Calculated by the following formula:
in the formula, phiM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
4. The analytical model for threshold voltage of MOSFET with asymmetric double gate structure as claimed in claim 1, wherein the flat band voltage V between the front gate metal gate and the doped region of silicon channel near the source end is VFB，b1Calculated by the following formula:
flat band voltage V between the front gate metal gate and the doped region of the silicon channel near the drain terminalFB，f2Calculated by the following formula:
in the formula, phiM1、φM2Work functions of a front gate metal gate and a back gate metal gate respectively; chi is the electron affinity of bulk silicon material, EgIs the forbidden band width, n, of bulk silicon materialiIs the doping concentration of intrinsic Si, and q is the electric quantity of electrons.
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| AU2003230418A1 (en) * | 2002-05-15 | 2003-12-02 | Celestry Design Technologies, Inc. | Modeling devices in consideration of process fluctuations |
| WO2008109337A2 (en) * | 2007-03-02 | 2008-09-12 | Rambus Inc. | Noise model method of predicting mismatch effects on transient circuit behaviors |
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| CN108365005A (en) * | 2018-01-23 | 2018-08-03 | 华北水利水电大学 | A kind of asymmetric double grid field effect transistor structure |
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| AU2003230418A1 (en) * | 2002-05-15 | 2003-12-02 | Celestry Design Technologies, Inc. | Modeling devices in consideration of process fluctuations |
| WO2008109337A2 (en) * | 2007-03-02 | 2008-09-12 | Rambus Inc. | Noise model method of predicting mismatch effects on transient circuit behaviors |
| CN102254072A (en) * | 2011-08-02 | 2011-11-23 | 复旦大学 | Analytical model for threshold voltage of fence-structured MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) |
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