CN108388697A - A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models - Google Patents
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Abstract
Description
技术领域technical field
本发明涉及半导体技术领域,具体涉及一种非对称双栅结构MOSFET阈值电压解析模型。The invention relates to the technical field of semiconductors, in particular to an asymmetric double gate structure MOSFET threshold voltage analysis model.
背景技术Background technique
随着金属氧化物半导体场效应晶体管(MOSFET)器件尺寸的持续减小,MOSFET器件面临着迁移率降低、短沟道效应等一些物理效应。在目前的一些新型器件结构中,双栅器件具有更优异的性质,对沟道电场的控制能力大大加强,亚阈值斜率更为理想,载流子迁移率大大提高。另外,沟道掺杂工程也被应用到新型器件结构中。因此,双栅渐变掺杂沟道MOSFET器件结构变得尤为重要,非对称双栅结构是双栅结构的一个普通形式,对于该结构,建立解析模型,进行理论研究和电路模拟,显得十分必要。As the size of metal-oxide-semiconductor field-effect transistor (MOSFET) devices continues to decrease, MOSFET devices face some physical effects such as reduced mobility and short-channel effects. In some of the current new device structures, the double-gate device has more excellent properties, the ability to control the channel electric field is greatly enhanced, the subthreshold slope is more ideal, and the carrier mobility is greatly improved. In addition, channel doping engineering has also been applied to novel device structures. Therefore, the device structure of double-gate gradiently doped channel MOSFET becomes particularly important. Asymmetric double-gate structure is a common form of double-gate structure. For this structure, it is necessary to establish an analytical model, conduct theoretical research and circuit simulation.
阈值电压是MOS器件的一个极为重要的电学参数之一,其大小对器件的频率特性、开关特性等都会带来重要的影响。对于非对称双栅器件,阈值电压Vth定义为:前栅沟道或背栅沟道其中之一刚刚导启而另一沟道尚未开启时的栅源电压,即前栅沟道表面势或背栅沟道表面势之一等于2φf(φf为费米势)时对应的栅源电压。要了解器件的电学特性,建立精确的阈值电压解析模型是十分必要的。Threshold voltage is one of the most important electrical parameters of MOS devices, and its magnitude will have an important impact on the frequency characteristics and switching characteristics of the device. For asymmetric double-gate devices, the threshold voltage Vth is defined as: the gate-source voltage when one of the front gate channel or the back gate channel has just been turned on and the other channel has not been turned on, that is, the surface potential of the front gate channel or The corresponding gate-source voltage when one of the surface potentials of the back gate channel is equal to 2φ f (φ f is the Fermi potential). To understand the electrical characteristics of the device, it is necessary to establish an accurate analytical model of the threshold voltage.
发明内容Contents of the invention
为解决上述问题,本发明提供了一种非对称双栅结构MOSFET阈值电压解析模型。In order to solve the above problems, the present invention provides an asymmetric double gate structure MOSFET threshold voltage analysis model.
为实现上述目的,本发明采取的技术方案为:In order to achieve the above object, the technical scheme that the present invention takes is:
一种非对称双栅结构MOSFET阈值电压解析模型,包括前栅阈值电压模型和背栅阈值电压模型,所述前栅阈值电压模型的解析式为:An asymmetric dual-gate structure MOSFET threshold voltage analytical model, including a front gate threshold voltage model and a back gate threshold voltage model, the analytical formula of the front gate threshold voltage model is:
其中, in,
af=2cosh(λ1L)-2-sinh2(λ1L)a f =2cosh(λ 1 L)-2-sinh 2 (λ 1 L)
bf=[1-exp(λ1L)]·Vb1,f+[exp(-λ1L)-1]·Vb2,f+2sinh2(λ1L)·(U1,f+2ψF,Si)b f =[1-exp(λ 1 L)]·V b1,f +[exp(-λ 1 L)-1]·V b2,f +2 sinh 2 (λ 1 L)·(U 1,f + 2ψ F, Si )
cf=Vb1,f·Vb2,f-sinh2(λ1L)·(U1,f+2ψF,Si)2 c f = V b1, f · V b2, f -sinh 2 (λ 1 L) · (U 1, f +2ψ F, Si ) 2
Vb1,f=-(Vbi+U1,f)·exp(-λ1L)+(U1,f-U2,f)cosh(λ1(L-L1))+(Vbi+VDS+U2,f)V b1,f =-(V bi +U 1,f )·exp(-λ 1 L)+(U 1,f -U 2,f )cosh(λ 1 (LL 1 ))+(V bi +V DS + U 2, f )
Vb2,f=(Vbi+U1,f)·exp(λ1L)-(U1,f-U2,f)cosh(λ1(L-L1))-(Vbi+VDS+U2,f)V b2,f =(V bi +U 1,f )·exp(λ 1 L)-(U 1,f -U 2,f )cosh(λ 1 (LL 1 ))-(V bi +V DS + U2 , f )
式中,εSi为硅的介电常数,εf为栅介质的介电常数,tSi为硅沟道的厚度,t1为前栅栅介质层的厚度,t2为背栅栅介质层的厚度;L为沟道的长度,分为两个掺杂区域,N1表示靠近源端沟道低掺杂区域的掺杂浓度,L1为其长度;N2表示靠近漏端沟道高掺杂区域的掺杂浓度;VGS为栅源电压,VDS为漏源电压,VT为热电压,q为电子的电量。VFB,f1为前栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压;VFB,f2为前栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压;In the formula, ε Si is the dielectric constant of silicon, ε f is the dielectric constant of the gate dielectric, t Si is the thickness of the silicon channel, t 1 is the thickness of the front gate dielectric layer, and t 2 is the back gate dielectric layer The thickness of the channel; L is the length of the channel, divided into two doped regions, N 1 represents the doping concentration of the low-doped region near the source channel, L 1 is its length; N 2 represents the high channel near the drain The doping concentration of the doped region; V GS is the gate-source voltage, V DS is the drain-source voltage, V T is the thermal voltage, and q is the electric quantity of electrons. V FB, f1 is the flat band voltage between the metal gate of the front gate and the doped region near the source end of the silicon channel; V FB, f2 is the flat band voltage between the metal gate of the front gate and the doped region of the silicon channel near the drain end Voltage;
背栅靠近源端掺杂区域的有效栅压:V′GS21=VGS-VFB,b1;The effective gate voltage of the doped region near the source end of the back gate: V′ GS21 = V GS -V FB, b1 ;
背栅靠近漏端掺杂区域的有效栅压:V′GS22=VGS-VFB,b2;The effective gate voltage of the doped region of the back gate close to the drain: V' GS22 = V GS -V FB, b2 ;
其中,VFB,b1为背栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压;VFB,b2为背栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压;Among them, V FB, b1 is the flat-band voltage between the back gate metal gate and the doped region of the silicon channel near the source end; V FB, b2 is the voltage between the back gate metal gate and the doped region of the silicon channel near the drain end flat band voltage;
硅沟道和源端之间的內建电势: Built-in potential between silicon channel and source:
式中,Eg为体硅材料的禁带宽度,ni为本征Si的掺杂浓度,q为电子的电量;In the formula, E g is the bandgap width of bulk silicon material, n i is the doping concentration of intrinsic Si, and q is the charge of electrons;
所述背栅阈值电压模型的解析式为:The analytical formula of the back gate threshold voltage model is:
其中, in,
ab=2cosh(λ2L)-2-sinh2(λ2L)a b =2cosh(λ 2 L)-2-sinh 2 (λ 2 L)
bb=[1-exp(λ2L)]·Vb1,b+[exp(-λ2L)-1]·Vb2,b+2sinh2(λ2L)·(U1,b+2ψF,Si)b b =[1-exp(λ 2 L)]·V b1,b +[exp(-λ 2 L)-1]·V b2,b +2 sinh 2 (λ 2 L)·(U 1,b + 2ψ F, Si )
cb=Vb1,b·Vb2,b-sinh2(λ2L)·(U1,b+2ψF,Si)2 c b =V b1,b ·V b2,b -sinh 2 (λ 2 L)·(U 1,b +2ψ F,Si ) 2
Vb1,b=-(Vb1+U1,b)·exp(-λ2L)+(U1,b-U2,b)cosh(λ2(L-L1))+(Vb1+VDs+U2,b)V b1,b =-(V b1 +U 1,b )·exp(-λ 2 L)+(U 1,b -U 2,b )cosh(λ 2 (LL 1 ))+(V b1 +V Ds + U2,b )
Vb2,b=(Vbi+U1,b)·exp(λ2L)-(U1,b-U2,b)cosh(λ2(L-L1))-(Vb1+VDS+U2,b)V b2,b =(V bi +U 1,b )·exp(λ 2 L)-(U 1,b -U 2,b )cosh(λ 2 (LL 1 ))-(V b1 +V DS + U2 ,b )
式中,εSi为硅的介电常数,εf为栅介质的介电常数,tSi为硅沟道的厚度,t1为前栅栅介质层的厚度,t2为背栅栅介质层的厚度;L为沟道的长度,分为两个掺杂区域,N1表示靠近源端沟道低掺杂区域的掺杂浓度,L1为其长度;N2表示靠近漏端沟道高掺杂区域的掺杂浓度;VGS为栅源电压,VDS为漏源电压,VT为热电压,q为电子的电量。VFB,b1为背栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压;VFB,b2为背栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压;In the formula, ε Si is the dielectric constant of silicon, ε f is the dielectric constant of the gate dielectric, t Si is the thickness of the silicon channel, t 1 is the thickness of the front gate dielectric layer, and t 2 is the back gate dielectric layer The thickness of the channel; L is the length of the channel, divided into two doped regions, N 1 represents the doping concentration of the low-doped region near the source channel, L 1 is its length; N 2 represents the high channel near the drain The doping concentration of the doped region; V GS is the gate-source voltage, V DS is the drain-source voltage, V T is the thermal voltage, and q is the electric quantity of electrons. V FB, b1 is the flat band voltage between the back gate metal gate and the doped region near the source end of the silicon channel; V FB, b2 is the flat band voltage between the back gate metal gate and the doped region near the drain end of the silicon channel Voltage;
前栅靠近源端掺杂区域的有效栅压:V′GS11=VGS-VFB,f1;The effective gate voltage of the doped region near the source end of the front gate: V′ GS11 = V GS -V FB, f1 ;
前栅靠近漏端掺杂区域的有效栅压:V′GS12=VGS-VFB,f2;The effective gate voltage of the doped region near the drain end of the front gate: V′ GS12 = V GS -V FB, f2 ;
其中,VFB,f1为前栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压;VFB,f2为前栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压;Among them, V FB, f1 is the flat-band voltage between the metal gate of the front gate and the doped region near the source end of the silicon channel; V FB, f2 is the voltage between the metal gate of the front gate and the doped region of the silicon channel near the drain end flat band voltage;
硅沟道和源端之间的內建电势: Built-in potential between silicon channel and source:
式中,Eg为体硅材料的禁带宽度,ni为本征Si的掺杂浓度,q为电子的电量。In the formula, E g is the bandgap width of the bulk silicon material, ni is the doping concentration of intrinsic Si, and q is the charge of electrons.
非对称双栅器件中,其阈值电压为前栅或背栅阈值电压中较小者:In an asymmetric dual-gate device, the threshold voltage is the smaller of the front-gate or back-gate threshold voltages:
Vth=min(Vth,f,Vth,b)V th = min(V th, f , V th, b )
所述背栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压VFB,b1通过下式计算所得:The flat-band voltage V FB, b1 between the metal gate of the back gate and the doped region near the source end of the silicon channel is calculated by the following formula:
所述背栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压VFB,b2通过下式计算所得:The flat-band voltage V FB, b2 between the metal gate of the back gate and the doped region near the drain end of the silicon channel is calculated by the following formula:
式中,φM1、φM2分别为前栅金属栅、背栅金属栅的功函数;χ为体硅材料的电子亲和势,Eg为体硅材料的禁带宽度,ni为本征Si的掺杂浓度,q为电子的电量。In the formula, φ M1 and φ M2 are the work functions of the front gate metal gate and the back gate metal gate respectively; χ is the electron affinity of the bulk silicon material, E g is the bandgap width of the bulk silicon material, and n i is the intrinsic The doping concentration of Si, q is the charge of electrons.
所述前栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压VFB,b1通过下式计算所得:The flat-band voltage V FB, b1 between the metal gate of the front gate and the doped region near the source end of the silicon channel is calculated by the following formula:
所述前栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压VFB,f2通过下式计算所得:The flat-band voltage V FB, f2 between the metal gate of the front gate and the doped region near the drain end of the silicon channel is calculated by the following formula:
式中,φM1、φM2分别为前栅金属栅、背栅金属栅的功函数;χ为体硅材料的电子亲和势,Eg为体硅材料的禁带宽度,ni为本征Si的掺杂浓度,q为电子的电量。In the formula, φ M1 and φ M2 are the work functions of the front gate metal gate and the back gate metal gate respectively; χ is the electron affinity of the bulk silicon material, E g is the bandgap width of the bulk silicon material, and n i is the intrinsic The doping concentration of Si, q is the charge of electrons.
本发明根据非对称双栅结构和渐变掺杂沟道的特点,得到一定的边界条件。假设前栅沟道和背栅沟道均处于弱反型状态,基于沟道表面势抛物线近似的假设,通过二维泊松方程和边界条件,计算出前栅、背栅的表面电势。在此基础上,根据阈值电压的定义,推导得到前栅、背栅的阈值电压解析模型,其中前栅、背栅的阈值电压较小者为该结构的阈值电压解析模型。该模型也可以推广于非对称双栅均匀掺杂沟道、对称双栅均匀掺杂沟道、对称双栅渐变掺杂沟道等结构。该模型精度高、物理概念清晰,为模拟软件在研究双栅场效应晶体管器件时提供了一种快速的工具。The invention obtains certain boundary conditions according to the characteristics of the asymmetrical double-gate structure and the gradually doped channel. Assuming that both the front gate channel and the back gate channel are in the weak inversion state, based on the assumption that the surface potential of the channel is approximated by a parabola, the surface potentials of the front gate and the back gate are calculated through the two-dimensional Poisson equation and boundary conditions. On this basis, according to the definition of threshold voltage, an analytical model of the threshold voltage of the front gate and the back gate is derived, and the threshold voltage of the front gate and the back gate is the smaller threshold voltage analytical model of the structure. This model can also be extended to structures such as asymmetric double-gate uniformly doped channel, symmetrical double-gate uniformly doped channel, and symmetrical double-gate gradually doped channel. The model has high accuracy and clear physical concept, which provides a fast tool for simulation software when studying dual-gate field-effect transistor devices.
附图说明Description of drawings
图1为本发明实施例中非对称双栅结构MOSFET的一个具体实施例。FIG. 1 is a specific embodiment of an asymmetric double-gate structure MOSFET in an embodiment of the present invention.
图2前栅和背栅阈值电压随沟长L的变化示意图。Fig. 2 Schematic diagram of the variation of the front gate and back gate threshold voltages with the trench length L.
图3渐变掺杂沟道(N1=1015cm-3,N2=5×1016cm-3)与均匀掺杂沟道(N1=N2=1015cm-3)的阈值电压比较示意图。Figure 3 Threshold voltage of graded doped channel (N 1 =10 15 cm -3 , N 2 =5×10 16 cm -3 ) and uniformly doped channel (N 1 =N 2 =10 15 cm -3 ) Compare schematics.
具体实施方式Detailed ways
为了使本发明的目的及优点更加清楚明白,以下结合实施例对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the objects and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the examples. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.
本实施例中非对称双栅结构MOSFET的导电沟道采用渐变掺杂硅沟道,沟道分为两个区域,靠近源区部分为低掺杂区域,靠近漏区部分为高掺杂区域。忽略固定氧化层电荷对沟道电势的影响,前栅沟道和背栅沟道均处于弱反型时,前栅沟道电势分布和背栅沟道电势分布可以用泊松方程表示:In this embodiment, the conduction channel of the asymmetric double-gate structure MOSFET adopts a graded doped silicon channel, and the channel is divided into two regions, the part near the source region is a low-doped region, and the part near the drain region is a highly doped region. Neglecting the influence of the fixed oxide layer charge on the channel potential, when both the front gate channel and the back gate channel are in weak inversion, the potential distribution of the front gate channel and the back gate channel can be expressed by the Poisson equation:
其中,ψ11(x,y1)、ψ12(x,y1)分别为N1区域、N2区域的前栅沟道电势;ψ21(x,y2)、ψ22(x,y2)分别为N1区域、N2区域背栅沟道电势。当漏端偏压VDS较小时,前栅、背栅沟道的纵向电势均采用抛物线函数近似,Among them, ψ 11 (x, y 1 ), ψ 12 (x, y 1 ) are the front gate channel potentials of N 1 and N 2 regions respectively; ψ 21 (x, y 2 ), ψ 22 (x, y 2 ) are the back gate channel potentials of the N 1 region and the N 2 region respectively. When the drain bias voltage V DS is small, the longitudinal potentials of the front gate and back gate channels are approximated by parabolic functions,
ψ1j(x,y1)=ψSj(x)+Cj1(x)y+Cj2(x)y1 2,j=1,2 (5)ψ 1j (x, y 1 ) = ψ Sj (x) + C j1 (x) y + C j2 (x) y 1 2 , j = 1, 2 (5)
ψ2j(x,y2)=ψBj(x)+Dj1(x)y+Dj2(x)y2 2,j=1,2 (6)ψ 2j (x, y 2 ) = ψ Bj (x) + D j1 (x) y + D j2 (x) y 2 2 , j = 1, 2 (6)
ψSj(x)=ψ1j(x,0),j=1,2分别为沟道N1、N2两个掺杂区域的前栅沟道表面势,ψBj(x)=ψ2j(x,0),j=1,2分别为沟道N1、N2两个掺杂区域的背栅沟道表面势,Cj1(x)、Cj2(x)、Dj1(x)、Dj2(x)是仅与x有关的函数。ψ Sj (x) = ψ 1j (x, 0), j = 1, 2 are the front gate channel surface potentials of the two doped regions of channel N 1 and N 2 respectively, ψ Bj (x) = ψ 2j ( x, 0), j=1, 2 are the back gate channel surface potentials of the two doped regions of the channel N 1 and N 2 respectively, C j1 (x), C j2 (x), D j1 (x), D j2 (x) is a function related only to x.
前栅沟道表面势和背栅沟道表面势可以由二维泊松方程和边界条件得出,边界条件如下:The surface potential of the front-gate channel and the surface potential of the back-gate channel can be obtained from the two-dimensional Poisson equation and boundary conditions, and the boundary conditions are as follows:
ψ11(L1,0)=ψ12(L1,0) (11)ψ 11 (L 1 , 0) = ψ 12 (L 1 , 0) (11)
ψ21(L1,0)=ψ22(L1,0) (13)ψ 21 (L 1 , 0) = ψ 22 (L 1 , 0) (13)
ψ11(0,0)=ψS1(0)=ψ21(0,0)=ψB1(0)=Vb1 (15)ψ 11 (0, 0) = ψ S1 (0) = ψ 21 (0, 0) = ψ B1 (0) = V b1 (15)
ψ12(L,0)=ψS2(L)=ψ22(L,0)=ψB2(L)=Vb1+VDS (16)ψ 12 (L, 0) = ψ S2 (L) = ψ 22 (L, 0) = ψ B2 (L) = V b1 + V DS (16)
由边界条件(7)-(10),得到(5)、(6)的系数Cj1(x)、Cj2(x)、Dj1(x)、Dj2(x)的表达式。再把(5)、(6)代入方程(1)-(4),并令y=0,可分别得到前栅沟道表面势和背栅沟道表面势的二阶方程。From the boundary conditions (7)-(10), the expressions of the coefficients C j1 (x), C j2 (x), D j1 (x), and D j2 (x) of (5) and (6) are obtained. Substituting (5) and (6) into equations (1)-(4), and setting y=0, the second-order equations of the surface potential of the front gate channel and the surface potential of the back gate channel can be obtained respectively.
由边界条件(11)-(16),可解得前栅沟道表面势和背栅沟道表面势表达式ψSj(x)和ψBj(x)。From the boundary conditions (11)-(16), the expressions ψ Sj (x) and ψ Bj (x) of the surface potential of the front gate channel and the surface potential of the back gate channel can be solved.
前栅沟道表面势为:The front gate channel surface potential is:
ψSj(x)=Ajexp(λ1x)+Bjexp(-λ1x)-ηj (17)ψ Sj (x)=A j exp(λ 1 x)+B j exp(-λ 1 x)-η j (17)
其中,ηj=β1j/λ1 2 Among them, η j =β 1j /λ 1 2
背栅沟道表面势为:The surface potential of the back-gate channel is:
ψBj(x)=Ejexp(λ2x)+Fjexp(-λ2x)-γj (18)ψ Bj (x)=E j exp(λ 2 x)+F j exp(-λ 2 x)-γ j (18)
其中, in,
沟道掺杂浓度N1<N2,沟道表面势最小值在低掺杂N1区域。令When the doping concentration of the channel is N 1 <N 2 , the minimum value of the surface potential of the channel is in the region of low doping N 1 . make
及 and
可得前栅沟道表面势最小值ψSmin和背栅沟道表面势最小值ψBmin。The minimum value of the surface potential of the front gate channel ψ Smin and the minimum value of the surface potential of the back gate channel ψ Bmin can be obtained.
根据阈值电压的定义:According to the definition of threshold voltage:
前栅阈值电压Vth,f定义为ψSmin等于低掺杂区域的费米势的2倍,即ψSmin=2ψF,Si时的栅源电压;The front gate threshold voltage V th, f is defined as the gate-source voltage when ψ Smin is equal to twice the Fermi potential of the low-doped region, that is, ψ Smin = 2ψ F, Si ;
背栅阈值电压Vth,b定义为ψBmin等于低掺杂区域的费米势的2倍,即ψBmin=2ψF,Si时的栅源电压。The back-gate threshold voltage V th,b is defined as the gate-source voltage when ψ Bmin is equal to twice the Fermi potential of the low-doped region, that is, ψ Bmin = 2ψ F, Si .
其中, in,
计算得出前栅、背栅阈值电压。对于非对称双栅器件,其阈值电压为前栅或背栅阈值电压中较小者,即:Vthmin(Vth,f,Vth,b)。Calculate the front gate and back gate threshold voltages. For an asymmetric double-gate device, its threshold voltage is the smaller of the threshold voltage of the front gate or the back gate, namely: V th min(V th, f , V th, b ).
当N1=N2时,前栅、背栅阈值电压解析模型就蜕化为非对称双栅均匀掺杂沟道MOSFET的前栅、背栅阈值电压模型,其中较小者,为该结构的阈值电压模型;当M1=M2,t1=t2时,蜕化为对称双栅渐变掺杂沟道MOSFET的前栅、背栅阈值电压模型,且二者相等,为该结构阈值电压模型;当M1=M2,t1=t2,N1=N2时,蜕化为对称双栅均匀掺杂沟道MOSFET的前栅、背栅阈值电压模型,且二者相等,为该结构阈值电压模型。When N 1 =N 2 , the analytical model of the threshold voltage of the front gate and the back gate degenerates into the model of the threshold voltage of the front gate and the back gate of the asymmetric double-gate uniformly doped channel MOSFET, and the smaller one is the threshold value of the structure Voltage model; when M 1 =M 2 , t 1 =t 2 , it degenerates into the front gate and back gate threshold voltage models of the symmetrical double-gate gradient doped channel MOSFET, and the two are equal, which is the threshold voltage model of the structure; When M 1 = M 2 , t 1 = t 2 , N 1 = N 2 , it degenerates into the front gate and back gate threshold voltage model of symmetrical double-gate uniformly doped channel MOSFET, and the two are equal, which is the threshold voltage of the structure voltage model.
所述前栅阈值电压模型的解析式为:The analytical formula of the front gate threshold voltage model is:
其中,in,
af=2cosh(λ1L)-2-sinh2(λ1L)a f =2cosh(λ 1 L)-2-sinh 2 (λ 1 L)
bf=[1-exp(λ1L)]·Vb1,f+[exp(-λ1L)-1]·Vb2,f+2sinh2(λ1L)·(U1,f+2ψF,Si)b f =[1-exp(λ 1 L)]·V b1,f +[exp(-λ 1 L)-1]·V b2,f +2 sinh 2 (λ 1 L)·(U 1,f + 2ψ F, Si )
cf=Vb1,f·Vb2,f-sinh2(λ1L)·(U1,f+2ψF,Si)2 c f = V b1, f · V b2, f -sinh 2 (λ 1 L) · (U 1, f +2ψ F, Si ) 2
Vb1,f=-(Vbi+U1,f)·exp(-λ1L)+(U1,f-U2,f)cosh(λ1(L-L1))+(Vbi+VDS+U2,f)V b1,f =-(V bi +U 1,f )·exp(-λ 1 L)+(U 1,f -U 2,f )cosh(λ 1 (LL 1 ))+(V bi +V DS + U 2, f )
Vb2,f=(Vbi+U1,f)·exp(λ1L)-(U1,f-U2,f)cosh(λ1(L-L1))-(Vbi+VDS+U2,f)V b2,f =(V bi +U 1,f )·exp(λ 1 L)-(U 1,f -U 2,f )cosh(λ 1 (LL 1 ))-(V bi +V DS + U2 , f )
式中,εSi为硅的介电常数,εf为栅介质的介电常数,tSi为硅沟道的厚度,t1为前栅栅介质层的厚度,t2为背栅栅介质层的厚度。沟长L分为两个掺杂区域,N1表示靠近源端沟道低掺杂区域的掺杂浓度,L1为其长度;N2表示靠近漏端沟道高掺杂区域的掺杂浓度。VGS为栅源电压,VDS为漏源电压,VT为热电压;In the formula, ε Si is the dielectric constant of silicon, ε f is the dielectric constant of the gate dielectric, t Si is the thickness of the silicon channel, t 1 is the thickness of the front gate dielectric layer, and t 2 is the back gate dielectric layer thickness of. The channel length L is divided into two doped regions, N 1 represents the doping concentration of the low doped region near the source channel, L 1 is its length; N 2 represents the doping concentration of the highly doped region near the drain channel . V GS is the gate-source voltage, V DS is the drain-source voltage, and V T is the thermal voltage;
背栅靠近源端掺杂区域的有效栅压:V′GS21=VGS-VFB,b1 The effective gate voltage of the doped region near the source end of the back gate: V' GS21 = V GS -V FB, b1
背栅靠近漏端掺杂区域的有效栅压:V′GS22=VGS-VFB,b2 The effective gate voltage of the doped region of the back gate close to the drain: V' GS22 = V GS -V FB, b2
VFB,b1为背栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压;V FB, b1 is the flat-band voltage between the metal gate of the back gate and the doped region of the silicon channel near the source;
VFB,b2为背栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压。V FB, b2 is the flat-band voltage between the metal gate of the back gate and the doped region near the drain end of the silicon channel.
VFB,f1为前栅金属栅和硅沟道靠近源端掺杂区域之间的平带电压;V FB, f1 is the flat-band voltage between the metal gate of the front gate and the doped region near the source end of the silicon channel;
VFB,f2为前栅金属栅和硅沟道靠近漏端掺杂区域之间的平带电压。V FB, f2 is the flat-band voltage between the metal gate of the front gate and the doped region near the drain end of the silicon channel.
硅沟道和源端之间的內建电势: Built-in potential between silicon channel and source:
其中,φM1、φM2分别为前栅金属栅、背栅金属栅的功函数;χ为体硅材料的电子亲和势,Eg为体硅材料的禁带宽度,ni为本征Si的掺杂浓度,q为电子的电量。Among them, φ M1 and φ M2 are the work functions of the front gate metal gate and the back gate metal gate respectively; χ is the electron affinity of the bulk silicon material, E g is the bandgap width of the bulk silicon material, and n i is the intrinsic Si The doping concentration of , q is the charge of electrons.
所述背栅阈值电压模型的解析式为:The analytical formula of the back gate threshold voltage model is:
其中, in,
ab=2cosh(λ2L)-2-sinh2(λ2L)a b =2cosh(λ 2 L)-2-sinh 2 (λ 2 L)
bb=[1-exp(λ2L)]·Vb1,b+[exp(-λ2L)-1]·Vb2,b+2sinh2(λ2L)·(U1,b+2ψF,Si)b b =[1-exp(λ 2 L)]·V b1,b +[exp(-λ 2 L)-1]·V b2,b +2 sinh 2 (λ 2 L)·(U 1,b + 2ψ F, Si )
cb=Vb1,b·Vb2,b-sinh2(λ2L)·(U1,b+2ψF,Si)2 c b =V b1,b ·V b2,b -sinh 2 (λ 2 L)·(U 1,b +2ψ F,Si ) 2
Vb1,b=-(Vb1+U1,b)·exp(-λ2L)+(U1,b-U2,b)cosh(λ2(L-L1))+(Vb1+VDS+U2,b)V b1,b =-(V b1 +U 1,b )·exp(-λ 2 L)+(U 1,b -U 2,b )cosh(λ 2 (LL 1 ))+(V b1 +V DS + U 2,b )
Vb2,b=(Vb1+U1,b)·exp(λ2L)-(U1,b-U2,b)cosh(λ2(L-L1))-(Vbi+VDS+U2,b)V b2,b =(V b1 +U 1,b )·exp(λ 2 L)-(U 1,b -U 2,b )cosh(λ 2 (LL 1 ))-(V bi +V DS + U2 ,b )
前栅靠近源端掺杂区域的有效栅压:V′GS11=VGS-VFB,f1 The effective gate voltage of the doped region near the source end of the front gate: V' GS11 = V GS -V FB, f1
前栅靠近漏端掺杂区域的有效栅压:V′GS12=VGS-VFB,f2。The effective gate voltage of the doped region near the drain end of the front gate: V′ GS12 =V GS −V FB,f2 .
本具体实施中非对称双栅MOSFET参数选择如下,In this specific implementation, the parameters of the asymmetric dual-gate MOSFET are selected as follows,
栅电极M1和M2分别采用功函数φM1=4.77eV、φM2=4.97eV的金属材料,沟道掺杂浓度轻掺杂区域N1=1015cm-3,重掺杂区域N2=5×1016cm-3,源漏掺杂浓度ND=1020cm-3,前栅栅介质层和背栅栅介质层均选用介电常数εf=20的高k材料HfO2,前栅栅介质层厚度t1=1nm,背栅栅介质层厚度t2=2nm,硅的介电常数εSi=11.9eV,低掺杂区域长度L1=10nm,沟长L=40nm。The gate electrodes M1 and M2 are respectively made of metal materials with work functions φ M1 = 4.77eV and φ M2 = 4.97eV, the channel doping concentration is lightly doped region N 1 =10 15 cm -3 , and heavily doped region N 2 =5 ×10 16 cm -3 , source-drain doping concentration ND = 10 20 cm -3 , both the front gate dielectric layer and the back gate dielectric layer are made of high-k material HfO 2 with a dielectric constant ε f = 20, the front gate Gate dielectric layer thickness t 1 =1nm, back gate dielectric layer thickness t 2 =2nm, silicon dielectric constant ε Si =11.9eV, low doped region length L 1 =10nm, trench length L=40nm.
选择以上参数,得到了图2和图3。After selecting the above parameters, Figure 2 and Figure 3 are obtained.
图2得到了前栅和背栅阈值电压的模型计算结果和DESSIS仿真结果。根据该模型计算得到的前栅、背栅阈值电压和DESSIS仿真软件得出的结果基本一致。前栅阈值电压较小,为该器件的阈值电压。Figure 2 shows the model calculation results and DESSIS simulation results of the front gate and back gate threshold voltages. The threshold voltages of the front gate and back gate calculated according to the model are basically consistent with the results obtained by the DESSIS simulation software. The threshold voltage of the front gate is smaller, which is the threshold voltage of the device.
从图3可看出,对于均匀掺杂沟道MOSFET器件,当沟道长度小于25nm后,阈值电压随沟道长度的减小有明显的降落,即当沟道长度小于25nm后短沟道效应比较严重。对于渐变掺杂沟道MOSFET器件,当沟道长度小于20nm后,阈值电压随沟道长度的减小有明显的降落。因此,该器件能较好的抑制短沟道效应。It can be seen from Figure 3 that for a uniformly doped channel MOSFET device, when the channel length is less than 25nm, the threshold voltage drops significantly with the decrease of the channel length, that is, when the channel length is less than 25nm, the short channel effect More serious. For graded doped channel MOSFET devices, when the channel length is less than 20nm, the threshold voltage drops significantly with the decrease of the channel length. Therefore, the device can better suppress the short channel effect.
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。The above is only a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be It is regarded as the protection scope of the present invention.
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