CN108388697A - A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models - Google Patents
A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models Download PDFInfo
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Abstract
The invention discloses a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models, the characteristics of present invention is according to asymmetric double grid structure and gradient doping raceway groove, certain boundary condition is obtained.It is approximate based on channel surface gesture parabola it is assumed that by two-dimentional Poisson's equation and boundary condition assuming that preceding gate groove and backgate raceway groove are in weak anti-type state, calculate preceding canopy, backgate surface potential.On this basis, according to the definition of threshold voltage, be derived by the threshold voltage analytic modell analytical model of front gate, backgate, wherein front gate, backgate threshold voltage smaller be the threshold voltage analytic modell analytical model of the structure.The model can also be extended to the structures such as asymmetric double grid uniformly doped channel, symmetrical double grid uniformly doped channel, symmetrical double grid gradient doping raceway groove.Model accuracy height, clear physics conception, a kind of quick tool is provided for simulation softward when studying dual gate FET device.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to a kind of asymmetric double grid structure MOSFET threshold voltages parsing
Model.
Background technology
With the lasting reduction of mos field effect transistor (MOSFET) device size, MOSFET element
It is faced with some physical effects such as mobility reduction, short-channel effect.In some current new device structures, double-gated devices
With superior property, the control ability of raceway groove electric field is greatly reinforced, sub-threshold slope is even more ideal, carrier mobility
It greatly improves.In addition, channel doping engineering is also applied in new device structure.Therefore, double grid gradient doping raceway groove
MOSFET element structure becomes particularly important, and asymmetric double grid structure is a common form of double-gate structure, for the structure,
Analytic modell analytical model is established, carries out theoretical research and breadboardin, it appears very necessary.
Threshold voltage is particularly important one of the electrical parameter of one of MOS device, size to the frequency characteristic of device,
Switching characteristic etc. can all bring important influence.For asymmetric double gate device, threshold voltage VthIt is defined as：Preceding gate groove or the back of the body
One of gate groove just led open and gate source voltage when another raceway groove is not yet turned on, i.e. front gate channel surface gesture or backgate ditch
One of road surface potential is equal to 2 φf(φfFor Fermi potential) when corresponding gate source voltage.It is to be understood that the electrology characteristic of device, establishes essence
True threshold voltage analytic modell analytical model is very necessary.
Invention content
To solve the above problems, the present invention provides a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models.
To achieve the above object, the technical solution that the present invention takes is：
A kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models, including front gate New Threshold Voltage Model and backgate threshold
The analytic expression of threshold voltage model, the front gate New Threshold Voltage Model is：
Wherein,
af=2cosh (λ1L)-2-sinh2(λ1L)
bf=[1-exp (λ1L)]·VB1, f+[exp(-λ1L)-1]·VB2, f+2sinh2(λ1L)·(U1, f+2ψF, Si)
cf=VB1, f·VB2, f-sinh2(λ1L)·(U1, f+2ψF, Si)2
VB1, f=-(Vbi+U1, f)·exp(-λ1L)+(U1, f-U2, f)cosh(λ1(L-L1))+(Vbi+VDS+U2, f)
VB2, f=(Vbi+U1, f)·exp(λ1L)-(U1, f-U2, f)cosh(λ1(L-L1))-(Vbi+VDS+U2, f)
In formula, εSiFor the dielectric constant of silicon, εfFor the dielectric constant of gate medium, tSiFor the thickness of silicon raceway groove, t1For front gate
The thickness of gate dielectric layer, t2For the thickness of backgate gate dielectric layer；L is the length of raceway groove, is divided into two doped regions, N1Expression is leaned on
The doping concentration of nearly source raceway groove low doped region, L1For its length；N2Indicate dense close to the doping of drain terminal raceway groove highly doped regions
Degree；VGSFor gate source voltage, VDSFor drain-source voltage, VTFor thermal voltage, q is the electricity of electronics.VFB, f1For front gate metal gate and silicon ditch
Flat-band voltage of the road between source doped region；VFB, f2It is front gate metal gate and silicon raceway groove between drain terminal doped region
Flat-band voltage；
Effective grid voltage of the backgate close to source doped region：V′GS21=VGS-VFB, b1；
Effective grid voltage of the backgate close to drain terminal doped region：V′GS22=VGS-VFB, b2；
Wherein, VFB, b1For the flat-band voltage of backgate metal gate and silicon raceway groove between source doped region；VFB, b2For the back of the body
The flat-band voltage of grid metal grid and silicon raceway groove between drain terminal doped region；
Inner between silicon raceway groove and source builds potential：
In formula, EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics；
The analytic expression of the backgate New Threshold Voltage Model is：
Wherein,
ab=2cosh (λ2L)-2-sinh2(λ2L)
bb=[1-exp (λ2L)]·VB1, b+[exp(-λ2L)-1]·VB2, b+2sinh2(λ2L)·(U1, b+2ψF, Si)
cb=VB1, b·VB2, b-sinh2(λ2L)·(U1, b+2ψF, Si)2
VB1, b=-(Vb1+U1, b)·exp(-λ2L)+(U1, b-U2, b)cosh(λ2(L-L1))+(Vb1+VDs+U2, b)
VB2, b=(Vbi+U1, b)·exp(λ2L)-(U1, b-U2, b)cosh(λ2(L-L1))-(Vb1+VDS+U2, b)
In formula, εSiFor the dielectric constant of silicon, εfFor the dielectric constant of gate medium, tSiFor the thickness of silicon raceway groove, t1For front gate
The thickness of gate dielectric layer, t2For the thickness of backgate gate dielectric layer；L is the length of raceway groove, is divided into two doped regions, N1Expression is leaned on
The doping concentration of nearly source raceway groove low doped region, L1For its length；N2Indicate dense close to the doping of drain terminal raceway groove highly doped regions
Degree；VGSFor gate source voltage, VDSFor drain-source voltage, VTFor thermal voltage, q is the electricity of electronics.VFB, b1For backgate metal gate and silicon ditch
Flat-band voltage of the road between source doped region；VFB, b2It is backgate metal gate and silicon raceway groove between drain terminal doped region
Flat-band voltage；
Effective grid voltage of the front gate close to source doped region：V′GS11=VGS-VFB, f1；
Effective grid voltage of the front gate close to drain terminal doped region：V′GS12=VGS-VFB, f2；
Wherein, VFB, f1For the flat-band voltage of front gate metal gate and silicon raceway groove between source doped region；VFB, f2It is preceding
The flat-band voltage of grid metal grid and silicon raceway groove between drain terminal doped region；
Inner between silicon raceway groove and source builds potential：
In formula, EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics.
In asymmetric double gate device, threshold voltage is smaller in front gate or backgate threshold voltage：
VTh=min(VTh, f, VTh, b)
The flat-band voltage V of the backgate metal gate and silicon raceway groove between source doped regionFB, b1It is calculate by the following formula
Gained：
The flat-band voltage V of the backgate metal gate and silicon raceway groove between drain terminal doped regionFB, b2It is calculate by the following formula
Gained：
In formula, φM1、φM2The respectively work function of front gate metal gate, backgate metal gate；χ is the electronics parent of body silicon materials
And gesture, EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics.
The flat-band voltage V of the front gate metal gate and silicon raceway groove between source doped regionFB, b1It is calculate by the following formula
Gained：
The flat-band voltage V of the front gate metal gate and silicon raceway groove between drain terminal doped regionFB, f2It is calculate by the following formula
Gained：
In formula, φM1、φM2The respectively work function of front gate metal gate, backgate metal gate；χ is the electronics parent of body silicon materials
And gesture, EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics.
The characteristics of present invention is according to asymmetric double grid structure and gradient doping raceway groove, obtains certain boundary condition.Assuming that
Preceding gate groove and backgate raceway groove are in weak anti-type state, approximate based on channel surface gesture parabola it is assumed that being moored by two dimension
Loose measure journey and boundary condition calculate the surface potential of front gate, backgate.On this basis, it according to the definition of threshold voltage, derives
The threshold voltage analytic modell analytical model of front gate, backgate is obtained, wherein front gate, the threshold voltage smaller of backgate is electric for the threshold value of the structure
Press analytic modell analytical model.The model can also be extended to asymmetric double grid uniformly doped channel, symmetrical double grid uniformly doped channel, symmetrical
The structures such as double grid gradient doping raceway groove.Model accuracy height, clear physics conception are that simulation softward is brilliant in research dual bar field effect
A kind of quick tool is provided when body tube device.
Description of the drawings
Fig. 1 is a specific embodiment of asymmetric double grid structure MOSFET in the embodiment of the present invention.
Fig. 2 front gates and backgate threshold voltage with the long L of ditch change schematic diagram.
Fig. 3 gradient doping raceway grooves (N1=1015cm-3, N2=5 × 1016cm-3) and uniformly doped channel (N1=N2=
1015cm-3) threshold voltage comparison schematic diagram.
Specific implementation mode
In order to make objects and advantages of the present invention be more clearly understood, the present invention is carried out with reference to embodiments further
It is described in detail.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, it is not used to limit this hair
It is bright.
The conducting channel of asymmetric double grid structure MOSFET uses gradient doping silicon raceway groove, raceway groove to be divided into two in the present embodiment
A region is low doped region close to region portions, is highly doped regions close to drain region part.Ignore fixed Oxide trapped charge pair
When the influence of groove potential, preceding gate groove and backgate raceway groove are in weak transoid, the distribution of front gate groove potential and backgate raceway groove electricity
Gesture distribution can be indicated with Poisson's equation：
Wherein, ψ11(x, y1)、ψ12(x, y1) it is respectively N1Region, N2The front gate groove potential in region；ψ21(x, y2)、ψ22
(x, y2) it is respectively N1Region, N2Region backgate groove potential.As drain terminal bias VDSWhen smaller, front gate, the longitudinal direction of backgate raceway groove are electric
Gesture is all made of parabolic function approximation,
ψ1j(x, y1)=ψSj(x)+Cj1(x)y+Cj2(x)y1 2, j=1,2 (5)
ψ2j(x, y2)=ψBj(x)+Dj1(x)y+Dj2(x)y2 2, j=1,2 (6)
ψSj(x)=ψ1j(x, 0), j=1,2 be respectively raceway groove N1、N2The front gate channel surface gesture of two doped regions, ψBj
(x)=ψ2j(x, 0), j=1,2 be respectively raceway groove N1、N2The backgate channel surface gesture of two doped regions, Cj1(x)、Cj2(x)、
Dj1(x)、Dj2(x) it is function only related with x.
Front gate channel surface gesture and backgate channel surface gesture can obtain by two-dimentional Poisson's equation and boundary condition, perimeter strip
Part is as follows：
ψ11(L1, 0) and=ψ12(L1, 0) and (11)
ψ21(L1, 0) and=ψ22(L1, 0) and (13)
ψ11(0,0)=ψS1(0)=ψ21(0,0)=ψB1(0)=Vb1 (15)
ψ12(L, 0)=ψS2(L)=ψ22(L, 0)=ψB2(L)=Vb1+VDS (16)
By boundary condition (7)-(10), the coefficient C of (5), (6) is obtainedj1(x)、Cj2(x)、Dj1(x)、Dj2(x) expression formula.
(5), (6) are substituted into equation (1)-(4), and enable y=0 again, front gate channel surface gesture and backgate channel surface gesture can be respectively obtained
Second-order equation.
By boundary condition (11)-(16), front gate channel surface gesture and backgate channel surface gesture expression formula ψ can be solvedSj(x) and
ψBj(x)。
Front gate channel surface gesture is：
ψSj(x)=Ajexp(λ1x)+Bjexp(-λ1x)-ηj (17)
Wherein, ηj=β1j/λ1 2
Backgate channel surface gesture is：
ψBj(x)=Ejexp(λ2x)+Fjexp(-λ2x)-γj (18)
Wherein,
Channel dopant concentration N1＜ N2, channel surface gesture minimum value is in low-doped N1Region.It enables
And
Front gate channel surface gesture minimum value ψ can be obtainedSminWith backgate channel surface gesture minimum value ψBmin。
According to the definition of threshold voltage：
Preceding gate threshold voltage VTh, fIt is defined as ψSminEqual to 2 times of the Fermi potential of low doped region, i.e. ψSmin=2 ψF, SiWhen
Gate source voltage；
Backgate threshold voltage VTh, bIt is defined as ψBminEqual to 2 times of the Fermi potential of low doped region, i.e. ψBmin=2 ψF, SiWhen
Gate source voltage.
Wherein,
Front gate, backgate threshold voltage is calculated.For asymmetric double gate device, threshold voltage is front gate or backgate threshold
Smaller in threshold voltage, i.e.,：Vthmin(VTh, f, VTh, b)。
Work as N1=N2When, front gate, backgate threshold voltage analytic modell analytical model just degenerate into asymmetric double grid uniformly doped channel
The front gate of MOSFET, backgate New Threshold Voltage Model, wherein smaller, for the New Threshold Voltage Model of the structure；Work as M1=M2, t1=
t2When, front gate, the backgate New Threshold Voltage Model of symmetrical double grid gradient doping channel mosfet are degenerated into, and the two is equal, for this
Structure New Threshold Voltage Model；Work as M1=M2, t1=t2, N1=N2When, before degenerating into symmetrical double grid uniformly doped channel MOSFET
Grid, backgate New Threshold Voltage Model, and the two is equal, for the structure New Threshold Voltage Model.
The analytic expression of the front gate New Threshold Voltage Model is：
Wherein,
af=2cosh (λ1L)-2-sinh2(λ1L)
bf=[1-exp (λ1L)]·VB1, f+[exp(-λ1L)-1]·VB2, f+2sinh2(λ1L)·(U1, f+2ψF, Si)
cf=VB1, f·VB2, f-sinh2(λ1L)·(U1, f+2ψF, Si)2
VB1, f=-(Vbi+U1, f)·exp(-λ1L)+(U1, f-U2, f)cosh(λ1(L-L1))+(Vbi+VDS+U2, f)
VB2, f=(Vbi+U1, f)·exp(λ1L)-(U1, f-U2, f)cosh(λ1(L-L1))-(Vbi+VDS+U2, f)
In formula, εSiFor the dielectric constant of silicon, εfFor the dielectric constant of gate medium, tSiFor the thickness of silicon raceway groove, t1For front gate
The thickness of gate dielectric layer, t2For the thickness of backgate gate dielectric layer.It is two doped regions, N that the long L of ditch, which is divided to,1It indicates close to source raceway groove
The doping concentration of low doped region, L1For its length；N2Indicate the doping concentration close to drain terminal raceway groove highly doped regions.VGSFor grid
Source voltage, VDSFor drain-source voltage, VTFor thermal voltage；
Effective grid voltage of the backgate close to source doped region：V′GS21=VGS-VFB, b1
Effective grid voltage of the backgate close to drain terminal doped region：V′GS22=VGS-VFB, b2
VFB, b1For the flat-band voltage of backgate metal gate and silicon raceway groove between source doped region；
VFB, b2For the flat-band voltage of backgate metal gate and silicon raceway groove between drain terminal doped region.
VFB, f1For the flat-band voltage of front gate metal gate and silicon raceway groove between source doped region；
VFB, f2For the flat-band voltage of front gate metal gate and silicon raceway groove between drain terminal doped region.
Inner between silicon raceway groove and source builds potential：
Wherein, φM1、φM2The respectively work function of front gate metal gate, backgate metal gate；χ is the electronics parent of body silicon materials
And gesture, EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics.
The analytic expression of the backgate New Threshold Voltage Model is：
Wherein,
ab=2cosh (λ2L)-2-sinh2(λ2L)
bb=[1-exp (λ2L)]·VB1, b+[exp(-λ2L)-1]·VB2, b+2sinh2(λ2L)·(U1, b+2ψF, Si)
cb=VB1, b·VB2, b-sinh2(λ2L)·(U1, b+2ψF, Si)2
VB1, b=-(Vb1+U1, b)·exp(-λ2L)+(U1, b-U2, b)cosh(λ2(L-L1))+(Vb1+VDS+U2, b)
VB2, b=(Vb1+U1, b)·exp(λ2L)-(U1, b-U2, b)cosh(λ2(L-L1))-(Vbi+VDS+U2, b)
Effective grid voltage of the front gate close to source doped region：V′GS11=VGS-VFB, f1
Effective grid voltage of the front gate close to drain terminal doped region：V′GS12=VGS-VFB, f2。
Asymmetric double gate MOSFET parameter selection is as follows in this specific implementation,
Work function φ is respectively adopted in gate electrode M1 and M2M1=4.77eV, φM2The metal material of=4.97eV, channel doping
Concentration lightly doped region N1=1015cm-3, heavily doped region N2=5 × 1016cm-3, source and drain doping concentration ND=1020cm-3, front gate
Gate dielectric layer and backgate gate dielectric layer select permittivity εf=20 high-g value HfO2, front gate gate dielectric layer thickness t1=
1nm, backgate gate dielectric layer thickness t2=2nm, the permittivity ε of siliconSi=11.9eV, doped regions length of field L1=10nm, ditch
Long L=40nm.
The above parameter is selected, Fig. 2 and Fig. 3 have been obtained.
Fig. 2 has obtained the model calculation and DESSIS simulation results of front gate and backgate threshold voltage.According to the model
The result that front gate, backgate threshold voltage and the DESSIS simulation softwares being calculated obtain is almost the same.Preceding gate threshold voltage compared with
It is small, for the threshold voltage of the device.
From figure 3, it can be seen that for uniformly doped channel MOSFET element, after channel length is less than 25nm, threshold voltage
Have an apparent landing with the reduction of channel length, i.e., after channel length is less than 25nm short-channel effect than more serious.For gradually
Varying doping trench MOSFET device, after channel length is less than 20nm, threshold voltage has apparent drop with the reduction of channel length
It falls.Therefore, which can preferably inhibit short-channel effect.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the principle of the present invention, it can also make several improvements and retouch, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (4)
1. a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models, which is characterized in that including preceding gate threshold voltage mould
The analytic expression of type and backgate New Threshold Voltage Model, the front gate New Threshold Voltage Model is：
Wherein,
af=2cosh (λ1L)-2-sinh2(λ1L)
bf=[1-exp (λ1L)]·VB1, f+[exp(-λ1L)-1]·VB2, f+2sinh2(λ1L)·(U1, f+2ψF, Si)
cf=VB1, f·VB2, f-sinh2(λ1L)·(U1, f+2ψF, Si)2
VB1, f=-(Vbi+U1, f)·exp(-λ1L)+(U1, f-U2, f)cosh(λ1(L-L1))+(Vbi+VDS+U2, f)
VB2, f=(Vbi+U1, f)·exp(λ1L)-(U1, f-U2, f)cosh(λ1(L-L1))-(Vbi+VDS+U2, f)
In formula, εSiFor the dielectric constant of silicon, εfFor the dielectric constant of gate medium, tSiFor the thickness of silicon raceway groove, t1It is situated between for front gate grid
The thickness of matter layer, t2For the thickness of backgate gate dielectric layer；L is the length of raceway groove, is divided into two doped regions, N1It indicates close to source
Hold the doping concentration of raceway groove low doped region, L1For its length；N2Indicate the doping concentration close to drain terminal raceway groove highly doped regions；
VGSFor gate source voltage, VDSFor drain-source voltage, VTFor thermal voltage, q is the electricity of electronics.VFB, f1For front gate metal gate and silicon raceway groove
Flat-band voltage between source doped region；VFB, f2It is front gate metal gate and silicon raceway groove between drain terminal doped region
Flat-band voltage；
Effective grid voltage of the backgate close to source doped region：V′GS21=VGS-VFB, b1；
Effective grid voltage of the backgate close to drain terminal doped region：V′GS22=VGS-VFB, b2；
Wherein, VFB, b1For the flat-band voltage of backgate metal gate and silicon raceway groove between source doped region；VFB, b2For backgate gold
Belong to the flat-band voltage of grid and silicon raceway groove between drain terminal doped region；
Inner between silicon raceway groove and source builds potential：
In formula, EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics；
The analytic expression of the backgate New Threshold Voltage Model is：
Wherein,
ab=2cosh (λ2L)-2-sinh2(λ2L)
bb=[1-exp (λ2L)]·VB1, b+[exp(-λ2L)-1]·VB2, b+2sinh2(λ2L)·(U1, b+2ψF, Si)
cb=VB1, b·VB2, b-sinh2(λ2L)·(U1, b+2ψF, Si)2
VB1, b=-(Vbi+U1, b)·exp(-λ2L)+(U1, b-U2, b)cosh(λ2(L-L1))+(Vbi+VDS+U2, b)
VB2, b=(Vbi+U1, b)·exp(λ2L)-(U1, b-U2, b)cosh(λ2(L-L1))-(Vbi+VDS+U2, b)
In formula, εSiFor the dielectric constant of silicon, εfFor the dielectric constant of gate medium, tSiFor the thickness of silicon raceway groove, t1It is situated between for front gate grid
The thickness of matter layer, t2For the thickness of backgate gate dielectric layer；L is the length of raceway groove, is divided into two doped regions, N1It indicates close to source
Hold the doping concentration of raceway groove low doped region, L1For its length；N2Indicate the doping concentration close to drain terminal raceway groove highly doped regions；
VGSFor gate source voltage, VDSFor drain-source voltage, VTFor thermal voltage, q is the electricity of electronics.VFB, b1For backgate metal gate and silicon raceway groove
Flat-band voltage between source doped region；VFB, b2It is backgate metal gate and silicon raceway groove between drain terminal doped region
Flat-band voltage；
Effective grid voltage of the front gate close to source doped region：V′GS11=VGS-VFB, f1；
Effective grid voltage of the front gate close to drain terminal doped region：V′GS12=VGS-VFB, f2；
Wherein, VFB, f1For the flat-band voltage of front gate metal gate and silicon raceway groove between source doped region；VFB, f2For front gate gold
Belong to the flat-band voltage of grid and silicon raceway groove between drain terminal doped region；
Inner between silicon raceway groove and source builds potential：
In formula, EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics.
2. a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models as described in claim 1, which is characterized in that non-
In symmetrical double-gated devices, threshold voltage is smaller in front gate or backgate threshold voltage：
Vth=min (VTh, f, VTh, b)
3. a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models as described in claim 1, which is characterized in that institute
State the flat-band voltage V of backgate metal gate and silicon raceway groove between source doped regionFB, b1It is calculate by the following formula gained：
The flat-band voltage V of the backgate metal gate and silicon raceway groove between drain terminal doped regionFB, b2It is calculate by the following formula gained：
In formula, φM1、φM2The respectively work function of front gate metal gate, backgate metal gate；χ is the electron affinity of body silicon materials,
EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics.
4. a kind of asymmetric double grid structure MOSFET threshold voltage analytic modell analytical models as described in claim 1, which is characterized in that institute
State the flat-band voltage V of front gate metal gate and silicon raceway groove between source doped regionFB, b1It is calculate by the following formula gained：
The flat-band voltage V of the front gate metal gate and silicon raceway groove between drain terminal doped regionFB, f2It is calculate by the following formula gained：
In formula, φM1、φM2The respectively work function of front gate metal gate, backgate metal gate；χ is the electron affinity of body silicon materials,
EgFor the energy gap of body silicon materials, niFor the doping concentration of intrinsic Si, q is the electricity of electronics.
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