CN102253253B - Circuit with external test voltage - Google Patents
Circuit with external test voltage Download PDFInfo
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- CN102253253B CN102253253B CN 201110075651 CN201110075651A CN102253253B CN 102253253 B CN102253253 B CN 102253253B CN 201110075651 CN201110075651 CN 201110075651 CN 201110075651 A CN201110075651 A CN 201110075651A CN 102253253 B CN102253253 B CN 102253253B
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- 229910044991 metal oxide Inorganic materials 0.000 abstract description 7
- 150000004706 metal oxides Chemical class 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 12
- 230000008676 import Effects 0.000 description 2
- 230000010076 replication Effects 0.000 description 2
- 230000009183 running Effects 0.000 description 1
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
- G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
- G01R35/007—Standards or reference devices, e.g. voltage or resistance standards, "golden references"
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
Abstract
The invention discloses a circuit with external test voltage, which comprises an amplifier, a first P-type metal oxide semiconductor transistor, a second P-type metal oxide semiconductor transistor, at least one reference resistor, at least one test resistor, a first upper resistor, a second upper resistor and a lower resistor, wherein the second P-type metal oxide semiconductor transistor is the same as the first P-type metal oxide semiconductor transistor. The current flowing through the first P-type metal oxide semiconductor transistor and the external test voltage fed in from a second end of the second upper resistor are copied through the second P-type metal oxide semiconductor transistor, so that the difference value of the voltage of one test output end of each test resistor and the voltage of one reference output end of a corresponding reference resistor is a preset value.
Description
Technical field
The present invention relates to a kind of circuit with external testing voltage, especially referring to a kind ofly only needs a liner (pad) in order to import external testing voltage, and the test voltage of the output circuit with external testing voltage that can not become geometric series to change together along with external testing voltage.
Background technology
Please refer to Fig. 1, Fig. 1 has the synoptic diagram of the circuit 100 of external testing voltage for DESCRIPTION OF THE PRIOR ART.Circuit 100 comprises an amplifier 102, a P-type mos transistor 104, a reference switch 106, a Test Switchboard 108, a resistance R U, a resistance R D and a plurality of resistance in series R1-Rn.When circuit 100 normal runnings, reference switch 106 opens and Test Switchboard 108 is closed.At this moment, a reference voltage VREF inputs to the negative input end of amplifier 102 by reference switch 106, and the voltage of node A also is reference voltage VREF.Therefore, with reference to output terminal VINTREFN1, VINTREFN2, VINTREFN3..., VINTREFNn output and the proportional voltage of reference voltage VREF.When circuit 100 needed input external testing voltage VT test, reference switch 106 was closed and Test Switchboard 108 is opened.At this moment, an external testing voltage VT inputs to the negative input end of amplifier 102 by Test Switchboard 108, and the voltage of node A also is external testing voltage VT.Therefore, with reference to output terminal VINTREFN1, VINTREFN2, VINTREFN3..., VINTREFNn output and the proportional voltage of external testing voltage VT.
But externally in the circuit 100 of test voltage, the voltage of exporting with reference to output terminal VINTREFN1, VINTREFN2, VINTREFN3..., VINTREFNn can change along with reference voltage VREF become geometric series together.Therefore, some voltage with reference to output terminal output may be too high, damages the circuit of testing.
Please refer to Fig. 2, Fig. 2 has the synoptic diagram of the circuit 200 of external testing voltage for another DESCRIPTION OF THE PRIOR ART.Circuit 200 comprises an amplifier 202, a P-type mos transistor 204, a plurality of reference switch 2061-206n, a plurality of Test Switchboard 2081-208n, a resistance R U, a resistance R D and a plurality of resistance in series R1-Rn.As shown in Figure 2, reference switch 2061 is coupled to reference between output terminal VINTREFN1 and the reference voltage output terminal VINTREF1, and Test Switchboard 2081 is coupled between reference voltage output terminal VINTREF1 and the test output terminal VINTREFT1; Reference switch 2062 is coupled to reference between output terminal VINTREFN2 and the reference voltage output terminal VINTREF2, and Test Switchboard 2082 is coupled between reference voltage output terminal VINTREF2 and the test output terminal VINTREFT2; Remaining the rest may be inferred, do not repeat them here.
Therefore, when each reference voltage output terminal among reference voltage output terminal VINTREF1, VINTREF2, VINTREF3..., the VINTREFn need be exported external testing voltage, the corresponding reference switch can cut out and corresponding Test Switchboard unlatching.In addition, when each reference voltage output terminal among reference voltage output terminal VINTREF1, VINTREF2, VINTREF3..., the VINTREFn need be exported voltage with reference to output terminal, corresponding reference switch open and corresponding Test Switchboard can be closed.For example, when reference voltage output terminal VINTREF1 need export external testing voltage V1, corresponding reference switch 2061 was closed and corresponding Test Switchboard 2081 is opened.Therefore, external testing voltage V1 after tested switch 2081 exported by reference voltage output terminal VINTREF1.The principle of operation of all the other reference voltage output terminal VINTREF2-VINTREFn is all identical with reference voltage output terminal VINTREF1, does not repeat them here.
Though circuit 200 has improved in the circuit 100 shortcoming that can change together along with reference voltage VREF with reference to the voltage of output terminal VINTREFN1, VINTREFN2, VINTREFN3..., VINTREFNn output.But when doing chip testing, but need many liners (pad) in order to import external testing voltage, make on the unlikely chip that is implemented in small size now of circuit 200.
Summary of the invention
One embodiment of the invention provide a kind of circuit with external testing voltage.This circuit comprises on an amplifier, one first P-type mos transistor, one second P-type mos transistor, at least one reference resistance, at least one test resistance, one first resistance on the resistance, one second, once resistance and a Test Switchboard.This amplifier has a first input end, and in order to receive one first voltage, one second input end is in order to receive a reference voltage, one the 3rd input end, and an output terminal; This first P-type mos transistor has one first end, and in order to receiving this first voltage, one second end is coupled to the output terminal of this amplifier and one the 3rd end; This second P-type mos transistor has one first end, and in order to receiving this first voltage, one second end is coupled to the output terminal of this amplifier and one the 3rd end; This at least one reference resistance has one first end, is coupled to transistorized the 3rd end of this first P-type mos, and one second end, and wherein each reference resistance has one with reference to output terminal; This at least one test resistance has one first end, be coupled to transistorized the 3rd end of this second P-type mos, and one second end, wherein each test resistance has a test output terminal, and the resistance of this each test resistance is identical with the resistance of a corresponding reference resistance; This on first resistance have one first end, be coupled to second end of this at least one reference resistance, and one second end, be coupled to second input end of this amplifier, wherein this on first the resistance of resistance can be zero; This on second resistance have one first end, be coupled to second end of this at least one test resistance, and one second end, in order to receive an external testing voltage, wherein this on second the resistance of resistance can be zero; This time resistance has one first end, is coupled to second input end of this amplifier, and one second end, is coupled to a ground end; Wherein this second P-type mos transistor is identical with this first P-type mos transistor.
A kind of circuit with external testing voltage provided by the present invention, utilize one second P-type mos transistor replication stream through the transistorized electric current of one first P-type mos and an external testing voltage of the second end feed-in of resistance on from one second, make that a difference with reference to the voltage of output terminal of the voltage of a test output terminal of each test resistance and a corresponding reference resistance is a predetermined value.The present invention also can improve each voltage with reference to output terminal output and can change along with a reference voltage become geometric series, and needs many shortcomings in order to the liner of importing this external testing voltage.In addition, the present invention can be at the information of voltage of a chip testing storage one fuse programming (fuse-programming).
Description of drawings
Fig. 1 has the synoptic diagram of the circuit of external testing voltage for DESCRIPTION OF THE PRIOR ART;
Fig. 2 has the synoptic diagram of the circuit of external testing voltage for DESCRIPTION OF THE PRIOR ART;
Fig. 3 has the synoptic diagram of the circuit of external testing voltage for one embodiment of the invention explanation;
Fig. 4 has the synoptic diagram of the circuit of external testing voltage for the another embodiment of the present invention explanation;
Fig. 5 has the synoptic diagram of the circuit of external testing voltage for the another embodiment of the present invention explanation;
Fig. 6 adjusts the look-up table of reference voltage output terminal according to first reference switch and first Test Switchboard for explanation;
Fig. 7 has the synoptic diagram of the circuit of external testing voltage for the another embodiment of the present invention explanation.
Wherein, Reference numeral
100,200,300,400,500 circuit 102,202,302 amplifiers
104,204P type metal oxide semiconductor transistor
304 first P-type mos transistors
306 second P-type mos transistors, 308 at least one reference resistances
Resistance on 310 at least one test resistance 312 first
316 times resistance of resistance on 314 second
3081-308n reference resistance 3101-310n test resistance
106,2061-206n, 3181-318n reference switch
108,2081-208n, 3201-320n Test Switchboard
422 province's electric switches
5181,5182,5,183 first reference switches
5201,5202,5,203 first Test Switchboards, 524 second reference switches
526 second Test Switchboard A nodes
I1, I2 electric current RU, RD, R1-Rn resistance
The VDD first voltage VG controls voltage
The VREF reference voltage
VINTREFN、VINTREFN1、VINTREFN2、VINTREFN3、VINTREFNn
With reference to output terminal
VINTREFT、VINTREFT1、VINTREFT2、VINTREFT3、VINTREFTn
Test output terminal
VINTREF1, VINTREF2, VINTREFn, VINTREF reference voltage output terminal
VT external testing voltage
Embodiment
Please refer to Fig. 3, Fig. 3 has the synoptic diagram of the circuit 300 of external testing voltage for one embodiment of the invention explanation.Circuit 300 comprises on an amplifier 302, one first P-type mos transistor 304, one second P-type mos transistor 306, at least one reference resistance 308, at least one test resistance 310, one first on the resistance 312, one second resistance 314 and resistance 316 once, and wherein the second P-type mos transistor 306 is identical with the first P-type mos transistor 304.Amplifier 302 has a first input end, and in order to receive one first voltage VDD, one second input end is in order to receive a reference voltage VREF, one the 3rd input end, and output terminal output one control voltage VG.The first P-type mos transistor 304 has one first end, and in order to receive the first voltage VDD, one second end is coupled to the output terminal of amplifier 302, in order to receive control voltage VG, reaches one the 3rd end.The second P-type mos transistor 306 has one first end, and in order to receive the first voltage VDD, one second end is coupled to the output terminal of amplifier 302, in order to receive control voltage VG, reaches one the 3rd end.At least one reference resistance 308 has one first end, is coupled to the 3rd end of the first P-type mos transistor 304, and one second end.At least one reference resistance 308 comprises reference resistance 3081-308n, and wherein n 〉=1 and each reference resistance have a corresponding reference output terminal.For example reference resistance 3081 has a corresponding reference output terminal VINTREFN1, and reference resistance 3082 has a corresponding reference output terminal VINTREFN2.At least one test resistance 310 has one first end, is coupled to the 3rd end of the second P-type mos transistor 306, and one second end.At least one test resistance 310 comprises test resistance 3101-310n, and wherein n 〉=1 and each test resistance have a corresponding test output terminal.For example test resistance 3101 has a corresponding test output terminal VINTREFT1, and test resistance 3102 has a corresponding test output terminal VINTREFT2.In addition, the resistance of each test resistance is identical with the resistance of a corresponding reference resistance.Resistance 312 has one first end on first, is coupled to second end of at least one reference resistance 308, and one second end, is coupled to the 3rd input end of amplifier 302, and wherein the resistance of resistance 312 can be zero on first.Resistance 314 has one first end on second, is coupled to second end of at least one test resistance 310, and one second end, and in order to receive an external testing voltage VT, wherein the resistance of resistance 314 can be zero on second.Following resistance 316 has one first end, is coupled to the 3rd input end of amplifier 302, and one second end, is coupled to a ground end.
In addition, circuit 300 comprises at least one reference switch 3181-318n and at least one Test Switchboard 3201-320n, wherein n 〉=1 in addition.Each reference switch has one first end, is coupled to corresponding one with reference to output terminal, and one second end, is coupled to a corresponding reference voltage output terminal.Each Test Switchboard has one first end, is coupled to a corresponding test output terminal, and one second end, is coupled to a corresponding reference voltage output terminal.For example, reference switch 3181 has one first end, is coupled to corresponding one with reference to output terminal VINTREFN1, and one second end, is coupled to a corresponding reference voltage output terminal VINTREF1.In like manner, Test Switchboard 3201 has one first end, is coupled to a corresponding test output terminal VINTREFT1, and one second end, is coupled to a corresponding reference voltage output terminal VINTREF1.
As shown in Figure 3, because the second P-type mos transistor 306 is identical with the first P-type mos transistor 304, the electric current I 1 of at least one reference resistance 308 so electric current I 2 of at least one test resistance 310 of flowing through equals to flow through.If the relation of external testing voltage VT and reference voltage VREF as the formula (1), then the relation with reference to the voltage VTi of the voltage VNi of output terminal VINTREFNi and test output terminal VINTREFTi is determined by formula (2), wherein 1≤i≤n.
VT＝VREF±ΔV (1)
VTi＝VNi±ΔV (2)
When circuit 300 was not during chip testing, at least one reference switch was opened, and therefore, reference voltage output terminal output is with reference to the voltage of output terminal.And when circuit 300 was during chip testing, at least one Test Switchboard was opened, therefore, and the voltage of reference voltage output terminal output test output terminal.For example, when circuit 300 was not during chip testing, reference switch 3181 was opened, and therefore, reference voltage output terminal VINTREF1 output is with reference to the voltage VN1 of output terminal VINTREFN1.When circuit 300 was during chip testing, Test Switchboard 3201 was opened, therefore, and the voltage VT1 of reference voltage output terminal VINTREF1 output test output terminal VINTREFT1.
Please refer to Fig. 4, Fig. 4 has the synoptic diagram of the circuit 400 of external testing voltage for the another embodiment of the present invention explanation.The difference of circuit 400 and circuit 300 is that circuit 400 comprises province's electric switch 422 in addition and has one first end, is coupled to second end of resistance 314 on second, and one second end, in order to receive external testing voltage VT.Economize electric switch 422 and only during chip testing, open, and close during the non-chip testing.Therefore, circuit 400 can be saved the power consumption during the non-chip testing.
Please refer to Fig. 5, Fig. 5 has the synoptic diagram of the circuit 500 of external testing voltage for the another embodiment of the present invention explanation.The difference of circuit 500 and circuit 300 is that circuit 500 does not comprise at least one reference switch 318 and at least one Test Switchboard 320, but comprise three first reference switches 5181,5182,5183, three first Test Switchboards 5201,5202,5203,1 second reference switch 524 and one second Test Switchboards 526 in addition.Each first reference switch has one first end, be coupled to the 3rd end of the first P-type mos transistor 304, that is with reference to output terminal VINTREFN, reach one second end, be coupled to second end of corresponding reference resistance, and each first Test Switchboard has one first end, be coupled to the 3rd end of the second P-type mos transistor 306, that is test output terminal VINTREFT, reach one second end, be coupled to second end of corresponding test resistance.For example, first reference switch 5181 has one first end, and first end is coupled to the 3rd end of the first P-type mos transistor 304, and one second end, is coupled to the reference output terminal of corresponding reference resistance 3081.First reference switch 5182 has one first end, and first end is coupled to the 3rd end of the first P-type mos transistor 304, and one second end, is coupled to the reference output terminal of corresponding reference resistance 3082.First Test Switchboard 5201 has one first end, and first end is coupled to the 3rd end of the second P-type mos transistor 306, and one second end, is coupled to the test output terminal of corresponding reference resistance 3101.First Test Switchboard 5202 has one first end, and first end is coupled to the 3rd end of the second P-type mos transistor 306, and one second end, is coupled to the test output terminal of corresponding reference resistance 3102.But the present invention is not limited to three first reference switches and three first Test Switchboards.
Circuit 500 can be at the information of voltage of chip testing storage fuse programming (fuse-programming).Please refer to Fig. 6, Fig. 6 is the look-up table according to first reference switch and first Test Switchboard adjustment reference voltage output terminal VINTREF.As shown in Figure 5 and Figure 6, when first reference switch 5182,5183, first Test Switchboard 5202,5203 are closed and first reference switch 5181, when first Test Switchboard 5201 is opened, be made as preset value with reference to the voltage VN1 of output terminal VINTREFN and the voltage VT1 of test output terminal VINTREFT.At this moment, reference voltage output terminal VINTREF can be by the unlatching of second reference switch 524 or second Test Switchboard 526, output voltage V N1 or voltage VT1.When first reference switch 5181 and first Test Switchboard 5201 are opened or closed, first reference switch 5182 and first Test Switchboard 5202 are opened, and first reference switch 5183 and first Test Switchboard 5203 when closing, reference voltage output terminal VINTREF can be by the unlatching of second reference switch 524 or second Test Switchboard 526, output voltage V N2 or voltage VT2, that is the voltage ratio preset value of reference voltage output terminal VINTREF output is low, and the variation in voltage value of comparing with preset value is-Δ V2 (Δ V2 is the cross-pressure of reference resistance 3082 and test resistance 3102).When first reference switch 5181,5182 and first Test Switchboard 5201,5202 are opened or closed, when first reference switch 5203 and first Test Switchboard 5203 are opened, reference voltage output terminal VINTREF can be by the unlatching of second reference switch 524 or second Test Switchboard 526, output voltage V N3 or voltage VT3, that is the voltage ratio preset value of reference voltage output terminal VINTREF output is low, and the variation in voltage value of comparing with preset value is-(Δ V2+ Δ V3) (Δ V3 is the cross-pressure of reference resistance 3083 and test resistance 3103).When first reference switch 5181, when 5182,5183 and first Test Switchboard 5201,5202,5203 is all closed, reference voltage output terminal VINTREF can be by the unlatching of second reference switch 524 or second Test Switchboard 526, output voltage V N0 or voltage VT0, that is the voltage ratio preset value height of reference voltage output terminal VINTREF output, and the variation in voltage value of comparing with preset value is+Δ V1 (Δ V1 is the cross-pressure of reference resistance 3081 and test resistance 3101).
Therefore, circuit 500 can utilize first reference switch 5181,5182,5183 and first Test Switchboard 5201,5202,5203 during chip testing, and the voltage of reference voltage output terminal VINTREF output is up adjusted by a preset value or down adjusted.
Please refer to Fig. 7, Fig. 7 has the synoptic diagram of the circuit 700 of external testing voltage for the another embodiment of the present invention explanation.The difference of circuit 700 and circuit 500 is that circuit 700 comprises province's electric switch 422 in addition and has one first end, is coupled to second end of resistance 314 on second, and one second end, in order to receive external testing voltage VT.Economize electric switch 422 and only during chip testing, open, and close during the non-chip testing.Therefore, circuit 700 can be saved the power consumption during the non-chip testing.
In sum, circuit with external testing voltage provided by the present invention, utilize the second P-type mos transistor replication stream through the transistorized electric current of first P-type mos and the external testing voltage of the second end feed-in of resistance on from second, make that a difference with reference to the voltage of output terminal of the voltage of a test output terminal of each test resistance and a corresponding reference resistance is a predetermined value.The voltage that the present invention also can improve in the prior art with reference to output terminal output can change along with reference voltage become geometric series, and needs many shortcomings in order to the liner of importing external testing voltage.In addition, the present invention can be at the information of voltage of chip testing storage fuse programming (fuse-programming).
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection domain of the appended claim of the present invention.
Claims (4)
1. the circuit with external testing voltage is characterized in that, comprises:
One amplifier has a first input end, and in order to receive one first voltage, one second input end is in order to receive a reference voltage, one the 3rd input end, and an output terminal;
One first P-type mos transistor has one first end, and in order to receiving this first voltage, one second end is coupled to the output terminal of this amplifier and one the 3rd end;
One second P-type mos transistor has one first end, and in order to receiving this first voltage, one second end is coupled to the output terminal of this amplifier and one the 3rd end;
At least one reference resistance has one first end, is coupled to transistorized the 3rd end of this first P-type mos, and one second end, and wherein each reference resistance has one with reference to output terminal, and this second end is that this is with reference to output terminal;
At least one test resistance, has one first end, be coupled to transistorized the 3rd end of this second P-type mos, and one second end, wherein each test resistance has a test output terminal, this second end is this test output terminal, and the resistance of this each test resistance is identical with the resistance of a corresponding reference resistance;
Resistance on one first has one first end, is coupled to second end of this at least one reference resistance, and one second end, is coupled to the 3rd input end of this amplifier, wherein this on first the resistance of resistance can be zero;
Resistance on one second has one first end, is coupled to second end of this at least one test resistance, and one second end, in order to receive an external testing voltage, wherein this on second the resistance of resistance can be zero; And
Once resistance has one first end, is coupled to the 3rd input end of this amplifier, and one second end, is coupled to a ground end;
Wherein this second P-type mos transistor is identical with this first P-type mos transistor.
2. circuit according to claim 1 is characterized in that, other comprises:
At least one reference switch, wherein each reference switch has one first end, is coupled to corresponding one with reference to output terminal, and one second end, is coupled to a corresponding reference voltage output terminal; And
At least one Test Switchboard, wherein each Test Switchboard has one first end, is coupled to a corresponding test output terminal, and one second end, is coupled to a corresponding reference voltage output terminal.
3. circuit according to claim 1 is characterized in that, other comprises:
At least one first reference switch, wherein each first reference switch has one first end, is coupled to transistorized the 3rd end of this first P-type mos, and one second end, is coupled to the reference output terminal of corresponding reference resistance;
At least one first Test Switchboard, wherein each first Test Switchboard has one first end, is coupled to transistorized the 3rd end of this second P-type mos, and one second end, is coupled to the test output terminal of corresponding test resistance;
One second reference switch has one first end, is coupled to transistorized the 3rd end of this first P-type mos, and one second end, is coupled to a reference voltage output terminal; And
One second Test Switchboard has one first end, is coupled to transistorized the 3rd end of this second P-type mos, and one second end, is coupled to this reference voltage output terminal.
4. according to claim 2 or 3 described circuit, it is characterized in that other comprises:
One province's electric switch has one first end, is coupled to second end of this resistance on second, and one second end, in order to receive this external testing voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100104638 | 2011-02-11 | ||
| TW100104638A TWI400464B (en) | 2011-02-11 | 2011-02-11 | Circuit having an external test voltage |
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| Publication Number | Publication Date |
|---|---|
| CN102253253A CN102253253A (en) | 2011-11-23 |
| CN102253253B true CN102253253B (en) | 2013-07-03 |
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| CN 201110075651 Expired - Fee Related CN102253253B (en) | 2011-02-11 | 2011-03-23 | Circuit with external test voltage |
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| US (1) | US8884642B2 (en) |
| CN (1) | CN102253253B (en) |
| TW (1) | TWI400464B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI520482B (en) | 2012-03-09 | 2016-02-01 | 鈺創科技股份有限公司 | Initial voltage generation circuit and method of generating an initial voltage |
| TWI474149B (en) | 2013-01-25 | 2015-02-21 | Etron Technology Inc | Multi-input low dropout regulator |
| US9429629B1 (en) * | 2013-03-11 | 2016-08-30 | Magna-Power Electronics, Inc. | Electronic loads |
| US9608586B2 (en) * | 2014-09-25 | 2017-03-28 | Qualcomm Incorporated | Voltage-to-current converter |
| US20170052552A1 (en) * | 2015-08-21 | 2017-02-23 | Qualcomm Incorporated | Single ldo for multiple voltage domains |
| TWI727673B (en) * | 2020-02-25 | 2021-05-11 | 瑞昱半導體股份有限公司 | Bias current generation circuit |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3163232B2 (en) * | 1995-04-14 | 2001-05-08 | 松下電工株式会社 | Reference voltage generation circuit |
| US7332924B2 (en) * | 2005-11-15 | 2008-02-19 | Agere Systems, Inc. | Embedded test circuitry and a method for testing a semiconductor device for breakdown, wearout or failure |
| CN101408571A (en) * | 2007-10-11 | 2009-04-15 | 瑞昱半导体股份有限公司 | Inserted detection circuit |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3699358A (en) * | 1971-06-14 | 1972-10-17 | Pioneer Magnetics Inc | Current sharing parallel transistor circuit |
| JPS55130226A (en) * | 1979-03-29 | 1980-10-08 | Fujitsu Ltd | Voltage division circuit |
| US5012178A (en) * | 1990-03-19 | 1991-04-30 | Triquint Semiconductor, Inc. | Low noise DAC current source topology |
| JPH05241671A (en) * | 1992-02-28 | 1993-09-21 | Fuji Electric Co Ltd | Reference voltage generator and semiconductor with function preventing excess current |
| JP2851767B2 (en) * | 1992-10-15 | 1999-01-27 | 三菱電機株式会社 | Voltage supply circuit and internal step-down circuit |
| US6084790A (en) * | 1999-01-07 | 2000-07-04 | Astec International Limited | Circuit to ensure equal current sharing and switching losses between parallel power devices |
| DE60030704T2 (en) * | 2000-07-10 | 2007-10-04 | Stmicroelectronics S.R.L., Agrate Brianza | Voltage switching regulator, with a driver circuit of a MOS circuit breaker |
| JP4313941B2 (en) * | 2000-09-29 | 2009-08-12 | 株式会社東芝 | Semiconductor memory device |
| US7053751B2 (en) * | 2001-05-14 | 2006-05-30 | Ricoh Company, Ltd. | Resistance hybrid, and voltage detection and constant voltage generating circuits incorporating such resistance hybrid |
| US6873146B2 (en) * | 2003-03-12 | 2005-03-29 | Texas Instruments Incorporated | Integrated circuit testing device and a method of use therefor |
| KR100545711B1 (en) * | 2003-07-29 | 2006-01-24 | 주식회사 하이닉스반도체 | Reference voltage generator that can output various levels of reference voltage using fuse trimming |
| JP4150326B2 (en) * | 2003-11-12 | 2008-09-17 | 株式会社リコー | Constant voltage circuit |
| JP4103859B2 (en) * | 2004-07-07 | 2008-06-18 | セイコーエプソン株式会社 | Reference voltage generation circuit |
| KR100670494B1 (en) * | 2005-04-26 | 2007-01-16 | 매그나칩 반도체 유한회사 | Driving circuit and driving method of liquid crystal display divice |
| US20090174392A1 (en) * | 2006-04-25 | 2009-07-09 | Nxp B.V. | Circuit arrangement and corresponding method for voltage reference and/or for current reference |
| TWI332134B (en) * | 2006-12-28 | 2010-10-21 | Ind Tech Res Inst | Adaptive pole and zero & pole zero cancellation control low drop-out voltage regulator |
| TWI376505B (en) * | 2008-06-06 | 2012-11-11 | Univ Nat Central | Oscillating system and assistant measuring circuit for oscillator |
-
2011
- 2011-02-11 TW TW100104638A patent/TWI400464B/en not_active IP Right Cessation
- 2011-03-23 CN CN 201110075651 patent/CN102253253B/en not_active Expired - Fee Related
-
2012
- 2012-01-03 US US13/342,207 patent/US8884642B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3163232B2 (en) * | 1995-04-14 | 2001-05-08 | 松下電工株式会社 | Reference voltage generation circuit |
| US7332924B2 (en) * | 2005-11-15 | 2008-02-19 | Agere Systems, Inc. | Embedded test circuitry and a method for testing a semiconductor device for breakdown, wearout or failure |
| CN101408571A (en) * | 2007-10-11 | 2009-04-15 | 瑞昱半导体股份有限公司 | Inserted detection circuit |
Non-Patent Citations (3)
| Title |
|---|
| JP昭55-130226A 1980.10.08 |
| JP特开平5-241671A 1993.09.21 |
| JP特许第3163232号B2 2001.02.23 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102253253A (en) | 2011-11-23 |
| US20120206161A1 (en) | 2012-08-16 |
| US8884642B2 (en) | 2014-11-11 |
| TW201234027A (en) | 2012-08-16 |
| TWI400464B (en) | 2013-07-01 |
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