CN102244743B - Analog device of external synchronous time-delayed-integration charge coupled device - Google Patents
Analog device of external synchronous time-delayed-integration charge coupled device Download PDFInfo
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- CN102244743B CN102244743B CN2011101563236A CN201110156323A CN102244743B CN 102244743 B CN102244743 B CN 102244743B CN 2011101563236 A CN2011101563236 A CN 2011101563236A CN 201110156323 A CN201110156323 A CN 201110156323A CN 102244743 B CN102244743 B CN 102244743B
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Abstract
The invention discloses an analog device of an external synchronous time-delayed-integration charge coupled device (TDI CCD), which belongs to the field of TDI CCDs. The device comprises a pin electrical characteristic analog circuit, a drive characteristic extraction circuit, an OS (Operating System) signal synthesis circuit, a delay characteristic control circuit, a light sensitivity control circuit and an integration series control circuit. By adopting the analog device, the analog of actual TDI CCD contour dimension, input/output pin electrical characteristics, output video signals and light sensitivity characteristics are realized. The analog of a TDI CCD signal is realized by applying the external synchronous theory, thus the actual contour size of the device is equivalent to the contour size of the TDI CCD, and the analog device has the characteristics of simple structure and low cost and can completely replace the actual TDI CCD to finish various experiment works.
Description
Technical field
The invention belongs to TDI CCD (Time Delay and Intergration Charge-Couple Device, integration time-delay charge coupled device) field, the particularly analogue means of a kind of outer synchronous mode TDI CCD.
Background technology
TDI CCD has in the situation that can not sacrifice spatial resolution and operating rate this outstanding feature of the high sensitivity of acquisition, make its at a high speed, the low-light field is with a wide range of applications.in scientific research mission, demand for performance and index, often need to customize novel TDI CCD, this just needs certain lead time and delivery cycle, sometimes even reach one to two year, this can have a strong impact on the progress of research and production task, in addition, the cost of TDI CCD is often very high, complex process, the driving of some novel TDI CCD requires very complicated, often adopt multiple power sources to power together, and the power-on and power-off of power supply order will satisfy certain precedence relationship, in case do not meet the demands, perhaps protect bad words and easily cause the damage of device, cause huge loss, this debug phase at circuit can often occur.
At present, industry has begun to design the waveform generator of various TDI CCD to solve the problem of test substitute, but are all the simulations fully for the electrical property of TDI CCD, because its complex structure, the problem such as cost is high, volume is large and be not suitable for actual applied environment.
Summary of the invention
In order to solve the problems of the technologies described above, the present invention has realized the simulation to the overall dimension of actual TDI CCD, input and output pin electrical characteristic, outputting video signal, integration stages numerical control system and photobehavior.
Outer synchronous mode TDI CCD analogue means, this device comprises: pin electrical characteristic analog circuit, driving characteristic extracting circuit, OS signal synthesis circuit, lag characteristic control circuit, photosensitivity control circuit and integration stages numerical control circuit processed; Pin electrical characteristic analog circuit receives external signal, and transfers signals to the driving characteristic extracting circuit; The lag characteristic control circuit sends a signal to the driving characteristic extracting circuit; Drive the signal that characteristic extracting circuit receives pin electrical characteristic analog circuit and the transmission of lag characteristic control circuit circuit, and transfer signals to the OS signal synthesis circuit; Photosensitivity control circuit and integration stages numerical control circuit sending signal processed are to the OS signal synthesis circuit; The OS signal synthesis circuit receives and drives the signal that characteristic extracting circuit, photosensitivity control circuit and integration stages numerical control circuit processed sends, and transfers signals to the outside;
Described pin electrical characteristic analog circuit is used for the capacitance-resistance characteristic of all pins of simulating TDI CCD and the input voltage and input current of each power pins; The function of described driving characteristic extracting circuit is to extract TDICCD to drive pixel transfering clock in signal and the mutual sequential relationship between reset pulse, as the input foundation of follow-up OS signal synthesis circuit; Described OS signal synthesis circuit synthesizes and exports and input the outer synchronous mode TDI CCD analogue means vision signal of driving timing synchronization; Described lag characteristic control circuit is controlled and synthesize and inputs delay time between driving sequential and outer synchronous mode TDI CCD analogue means output signal OS; Described photosensitivity control circuit is controlled and is adjusted outer synchronous mode TDI CCD analogue means output signal sensitization level; Described integration stages numerical control circuit processed is controlled the storage effect of outer synchronous mode TDI CCD analogue means output OS signal.
The principle of outer synchronous mode that adopted this device has realized the simulation of TDI ccd signal, therefore the overall dimension of the overall dimension of this device reality and TDI CCD is suitable, and have characteristics simple in structure, that cost is low, can replace actual TDI CCD fully and complete various experiment works.
Description of drawings
The outer synchronous mode integration time-delay of Fig. 1 the present invention charge coupled device analogue means block diagram.
The horizontal transfer of Fig. 2 integration time-delay charge coupled device drives sequential chart.
The outer synchronous mode integration time-delay of Fig. 3 the present invention charge coupled device analogue means pin capacitance-resistance simulated behavior circuit diagram.
The outer synchronous mode integration time-delay of Fig. 4 the present invention charge coupled device analogue means power pins Absorption Current analog circuit figure.
Fig. 5 integration time-delay charge coupled device output signal (OS) structure chart.
The outer synchronous mode integration time-delay of Fig. 6 the present invention charge coupled device analogue means drives the characteristic extracting circuit block diagram.
The outer synchronous mode integration time-delay of Fig. 7 the present invention charge coupled device analogue means waveform shaping circuit schematic diagram.
The outer synchronous mode integration time-delay of Fig. 8 the present invention charge coupled device analogue means time-delay and phase-adjusting circuit schematic diagram.
The outer synchronous mode integration time-delay of Fig. 9 the present invention charge coupled device analogue means OS signal synthesis circuit theory diagram.
The outer synchronous mode integration time-delay of Figure 10 the present invention charge coupled device analogue means OS signal waveform is synthetic, photosensitivity control signal and integration stages numerical control circuit theory diagrams processed.
The outer synchronous mode integration time-delay of Figure 11 the present invention charge coupled device analogue means reference level Overlap restoration timing chart.
The outer synchronous mode integration time-delay charge coupled device analogue means reference level of Figure 12 the present invention and reset pulse synthetic waveform and CR signal subtract each other synthetic TDI ccd signal oscillogram.
Embodiment
By shown in Figure 1, outer synchronous mode integration time-delay charge coupled device analogue means, this device comprises: pin electrical characteristic analog circuit, driving characteristic extracting circuit, OS signal synthesis circuit, lag characteristic control circuit, photosensitivity control circuit and integration stages numerical control circuit processed; Pin electrical characteristic analog circuit receives external signal, and transfers signals to the driving characteristic extracting circuit; The lag characteristic control circuit sends a signal to the driving characteristic extracting circuit; Drive the signal that characteristic extracting circuit receives pin electrical characteristic analog circuit and the transmission of lag characteristic control circuit, and transfer signals to the OS signal synthesis circuit; Photosensitivity control circuit and integration stages numerical control circuit sending signal processed are to the OS signal synthesis circuit; The OS signal synthesis circuit receives and drives the signal that characteristic extracting circuit, photosensitivity control circuit and integration stages numerical control circuit processed sends, and transfers signals to the outside;
Described pin electrical characteristic analog circuit is used for the capacitance-resistance characteristic of all pins of simulating TDI CCD and the input voltage and input current of each power pins; The function of described driving characteristic extracting circuit is to extract TDICCD to drive pixel transfering clock in signal and the mutual sequential relationship between reset pulse, as the input foundation of follow-up OS signal synthesis circuit; Described OS signal synthesis circuit synthesizes and exports and input the outer synchronous mode TDI CCD analogue means vision signal of driving timing synchronization; Described lag characteristic control circuit is controlled and synthesize and inputs delay time between driving sequential and outer synchronous mode TDI CCD analogue means output signal OS; Described photosensitivity control circuit is controlled and is adjusted outer synchronous mode TDI CCD analogue means output signal sensitization level; Described integration stages numerical control circuit processed is controlled the storage effect of outer synchronous mode TDI CCD analogue means output OS signal.
All of existing certain model TDI CCD that need to simulate drive capacitance-resistance characteristic such as the following table 1 of signals.Power supply pin VDD, supply current are 120mA, and supply power voltage is 18V.Horizontal drive sequential relationship such as accompanying drawing 2.Integration stages numerical control circuit pin processed is CSS16, CSS24, CSS32, CSS64, CSS96, realized respectively the control of 24,32,64,96 grades of integrations by them, when actual needs is realized certain one-level integration, corresponding control end is set to the level of 12V, and other control end keeps the 0V level.It is 25MHz that the pixel clock of this TDI CCD device drives highest frequency.
Simulation for the capacitance-resistance characteristic in pin electrical characteristic analog circuit, adopt the described capacitance-resistance analogy method of accompanying drawing 3, table 1 is the driving signal capacitance-resistance characteristic of the TDI CCD of certain model, pin capacitance-resistance characterisitic parameter according to this model of table 1, table 2 is the value of capacitance-resistance analog circuit capacitor C and resistance R, for the capacitor C in different pin accompanying drawings and value such as the table 2 of resistance R.
Table 1
Table 2
For the simulation of the power pins in pin electrical characteristic analog circuit, adopt the method for the grounding through resistance in accompanying drawing 4 to simulate.The supply current of this model TDI CCD power pins VDD is 120mA, and supply power voltage is 18V, so the resistance of R is 150 Ω, and power is 2W.
Effectively the composition structure of TDI CCD video output signals OS comprises 3 sections as shown in Figure 5, is respectively reset pulse section, reference level section and sensitization level section.The horizontal drive sequential relationship is seen accompanying drawing 2, and all kinds of CR signals are the horizontal transfer clock of outer synchronous mode TDI CCD, and all kinds of RST signals are reseting pulse signal, and OS is this model TDI CCD video output signals.RST signal visible according to this sequential chart be with the OS signal in the reset level section sequential one to one.The sequential of the effective feeling light level of CR signal and OS signal has fixing sequential relationship, and the temporal aspect that therefore extracts RST signal and CR signal can synthesize the OS vision signal.What drive characteristic extracting circuit realizes theory diagram such as accompanying drawing 6.
Waveform shaping circuit schematic diagram in accompanying drawing 6 such as accompanying drawing 7, the standard Transistor-Transistor Logic level that the mode that adopts electric resistance partial pressure and zener diode clamper is converted to 0～5V with RST and the CR signal of 0～12V in table 1.Time-delay in accompanying drawing 6 and phase-adjusting circuit schematic diagram such as accompanying drawing 8, employing DS1023 time delay device is realized the position adjusting function mutually for RST and CR signal.DS1023 is the waveform time delay device of being produced by MAXIM company, has at a high speed, the function of long delay or even the time-delay of whole cycle, and table 3 is functions of each pin of DS1023.DS1023 in accompanying drawing 8 is connected to the mode of operation of parallel deployment, homophase, is controlled the time-delay adjusting range 5～20ns of RST and CR signal by band switch for the phase place adjustment of input signal.
Table 3
The theory diagram of OS signal synthesis circuit as shown in Figure 9.Photosensitivity control circuit wherein and integration stages numerical control circuit theory diagrams processed are as shown in Figure 10.Wherein PHOTO_R and R3 have realized the photosensitivity photo-electric control, adjust the sensitization level of outer synchronous mode TDI CCD analog output signal, adjusting range 0～1.5V.RW variable resistance and R3 have realized the conditioning function of the outer synchronous mode TDI CCD sensitization level of manual adjustment, adjusting range 0～1.5V.The CR signal amplitude value simulation that these two Circuit tunings are inputted by adjustment has light conditions, and the CR amplitude becomes comes greatly illumination simulation to strengthen, otherwise illumination simulation reduces.PHOTO_R selects the G1273 photo resistance, and during illumination, light resistance is 20k Ω, and the dark resistance during dark situation is 500k Ω.U1A selects high speed amplifier LMH6715, consists of the control that the photosensitivity combiner circuit accepts to come from photosensitivity control circuit and integration stages numerical control circuit processed.U2 is integration stages numerical control circuit processed, selects four path analoging switch MAX4601 to realize, when the IN of certain passage end is high level, and the respective channel gating.IN1～IN4 of MAX4601 has been connected respectively on CSS24, CSS32, CSS64, the CSS96 pin of the outer synchronous mode TDI ccd sensor of simulated target as shown in Figure 10, controlled respectively the access of RF1～RF4, change the multiplication factor of U1A, thereby simulated the characteristic of the integration stages numerical control system of outer synchronous mode TDI CCD device.
U3A and U3B (LMH6715) and peripheral circuit thereof have been completed reset pulse and the synthetic function of reference level in accompanying drawing 9.U3A has completed the stack of RST and reference level, and U3B has realized the paraphase function, and final output waveform as shown in Figure 11.
U1B (LMH6715) completes the subtraction function in accompanying drawing 9, has realized the subtraction of the CR signal after the reset pulse shown in accompanying drawing 12 and reference level and photosensitivity are controlled, and exports the OS vision signal after synthesizing.
Outside adopting above-mentioned synchronous mode circuit, this device adopts a 3.7V lithium battery power supply, and all devices adopt the little packaging of Surface Mount, whole outer synchronous mode TDI CCD analogue means is suitable with actual TDICCD size, contour length is less than 90mm, and width is less than 40mm, and thickness is less than 30mm.
Claims (6)
1. outer synchronous mode integration time-delay charge coupled device analogue means, it is characterized in that, this device comprises: pin electrical characteristic analog circuit, driving characteristic extracting circuit, OS signal synthesis circuit, lag characteristic control circuit, photosensitivity control circuit and integration stages numerical control circuit processed; Pin electrical characteristic analog circuit receives external signal, and transfers signals to the driving characteristic extracting circuit; The lag characteristic control circuit sends a signal to the driving characteristic extracting circuit; Drive the signal that characteristic extracting circuit receives pin electrical characteristic analog circuit and the transmission of lag characteristic control circuit, and transfer signals to the OS signal synthesis circuit; Photosensitivity control circuit and integration stages numerical control circuit sending signal processed are to the OS signal synthesis circuit; The OS signal synthesis circuit receives and drives the signal that characteristic extracting circuit, photosensitivity control circuit and integration stages numerical control circuit processed sends, and transfers signals to the outside;
Described pin electrical characteristic analog circuit is for the capacitance-resistance characteristic of all pins of simulating TDI CCD and the input voltage and input current of each power pins;
Described driving characteristic extracting circuit is used for extracting TDI CCD and drives the pixel transfering clock of signal and the mutual sequential relationship between reset pulse, as the input foundation of follow-up OS signal synthesis circuit;
Described OS signal synthesis circuit for the synthesis of and output and input drive the outer synchronous mode integration time-delay charge coupled device analogue means vision signal of timing synchronization;
Described lag characteristic control circuit is used for controlling the synthetic of outer synchronous mode integration time-delay charge coupled device analogue means output signal OS, and control inputs drives the delay time between sequential and outer synchronous mode integration time-delay charge coupled device analogue means output signal OS;
Described photosensitivity control circuit is used for controlling the outer synchronous mode integration time-delay of adjustment charge coupled device analogue means output signal sensitization level;
Described integration stages numerical control circuit processed is used for controlling the storage effect of outer synchronous mode integration time-delay charge coupled device analogue means output OS signal.
2. outer synchronous mode integration time-delay charge coupled device analogue means according to claim 1, is characterized in that, described OS signal synthesis circuit is controlled the vision signal that drives timing synchronization, and it is 25MHz that its pixel drives the clock highest frequency.
3. outer synchronous mode integration time-delay charge coupled device analogue means according to claim 1, is characterized in that, described lag characteristic control circuit is controlled the reference time delay of the vision signal that drives timing synchronization at 5～20ns.
4. outer synchronous mode integration time-delay charge coupled device analogue means according to claim 1, is characterized in that, described lag characteristic control circuit has band switch and digital control two kinds of means.
5. outer synchronous mode integration time-delay charge coupled device analogue means according to claim 1, is characterized in that, described photosensitivity control circuit has two kinds of patterns, a kind of artificial adjustment, and a kind of sensitization adjustment, excursion is at 0～1.5V.
6. outer synchronous mode integration time-delay charge coupled device analogue means according to claim 1, is characterized in that, described integration stages numerical control circuit processed is the integration progression adjustment function of 24,32,64,96 grades for simulation progression.
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| CN102545841A (en) * | 2012-02-28 | 2012-07-04 | 北京工业大学 | Analogue signal generator for TDI (Transport Driver Interface) CCD (Charge Coupled Device) |
| CN108259794A (en) * | 2017-12-28 | 2018-07-06 | 中国科学院西安光学精密机械研究所 | A kind of ccd output signal simulates source generating method |
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|---|---|---|---|---|
| US6782334B1 (en) * | 2003-04-01 | 2004-08-24 | Lockheed Martin Corporation | Method and system for calibration of time delay integration imaging devices |
| CN101146181A (en) * | 2007-10-25 | 2008-03-19 | 中国科学院长春光学精密机械与物理研究所 | A simulated device for TDI CCD part |
| CN101309370A (en) * | 2008-07-09 | 2008-11-19 | 中国科学院长春光学精密机械与物理研究所 | Photoelectric conversion simulating device of TDI CCD apparatus and method thereof |
| CN101854489A (en) * | 2010-04-12 | 2010-10-06 | 中国科学院长春光学精密机械与物理研究所 | Device for reazliing time delay integral of area array CMOS image sensor |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6782334B1 (en) * | 2003-04-01 | 2004-08-24 | Lockheed Martin Corporation | Method and system for calibration of time delay integration imaging devices |
| CN101146181A (en) * | 2007-10-25 | 2008-03-19 | 中国科学院长春光学精密机械与物理研究所 | A simulated device for TDI CCD part |
| CN101309370A (en) * | 2008-07-09 | 2008-11-19 | 中国科学院长春光学精密机械与物理研究所 | Photoelectric conversion simulating device of TDI CCD apparatus and method thereof |
| CN101854489A (en) * | 2010-04-12 | 2010-10-06 | 中国科学院长春光学精密机械与物理研究所 | Device for reazliing time delay integral of area array CMOS image sensor |
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