CN102239552A - RF device and method with trench under bond pad feature - Google Patents

RF device and method with trench under bond pad feature Download PDF

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Publication number
CN102239552A
CN102239552A CN2009801488787A CN200980148878A CN102239552A CN 102239552 A CN102239552 A CN 102239552A CN 2009801488787 A CN2009801488787 A CN 2009801488787A CN 200980148878 A CN200980148878 A CN 200980148878A CN 102239552 A CN102239552 A CN 102239552A
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China
Prior art keywords
zone
joint sheet
inclusion
substrate
active device
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CN2009801488787A
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CN102239552B (en
Inventor
杰弗里·K·琼斯
玛格丽特·A·希马诺夫斯基
米歇尔·L·米耶拉
任小伟
韦恩·R·布格尔
马克·A·贝内特
科林·克尔
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NXP USA Inc
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Freescale Semiconductor Inc
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Abstract

Electronic elements (44, 44', 44'') having an active device region (46) and bonding pad (BP) region (60) on a common substrate (45) desirably include a dielectric region underlying the BP (35) to reduce the parasitic impedance of the BP (35) and its interconnection (41) as the electronic elements (44, 44', 44'') are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (36') can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (62, 62', 62'') having electrically isolated inclusions (65, 65', 65'') of a thermal expansion coefficient (TEC) less than that of the dielectric material (78, 78', 78'') in which they are embedded and/or closer to the substrate (45) TEC. For silicon substrates (45), poly or amorphous silicon is suitable for the inclusions (65, 65', 65'') and silicon oxide for the dielectric material (78, 78', 78''). The inclusions (65, 65', 65'') preferably have a blade-like shape separated by and enclosed within the dielectric material (78, 78', 78'').

Description

The RF Apparatus and method for of feature with groove of joint sheet below
Technical field
The present invention relates generally to semiconductor (SC) device and integrated circuit (IC) and manufacture method thereof, and more specifically, relate to be used to provide the filling that comprises joint sheet below RF (radio frequency) power supply apparatus of feature of groove of insulator and structure and the method for IC.
Background technology
The performance of radio frequency (RF) power supply apparatus and integrated circuit (IC) pair is responsive especially with the terminal impedance to the join dependency connection of device or IC.For wherein usually using the low-resistivity substrate (for example,＜0.1Ohm-cm) to strengthen metal-oxide semiconductor (MOS) (MOS) field-effect transistor (MOSFET) of active device performance and Laterally Diffused Metal Oxide Semiconductor (LDMOS) field-effect transistor (FET) and the describing love affairs condition is especially true.Coupling may make the impedance matching that is difficult to or expectation can not be provided at input-output (I/O) the terminal place of such device to the electromagnetism (E-M) of such low-resistivity substrate, and keeps the power output and the efficient of expectation.In addition, such E-M coupling may cause the eddy current losses in the substrate, and this may further reduce device and IC performance.These problems in high peripheral components and higher frequency (for example, become more serious under the situation of the device of＞～1GHz), because intrinsic device resistance descends along with the frequency of periphery that increases and increase, and the E-M loss increases along with the increase of the size of terminal connection (for example, joint sheet).
Fig. 1 (for example shows field-effect transistor (FET) 24, MOSFET) simplification electrical schematic block diagram 10, the grid 14 of field-effect transistor (FET) 24 is coupled to input joint sheet (IP-BP) 12 by input interconnection 13, and its drain electrode 16 is coupled to output joint sheet (OP-BP) 35 by output interconnection 41.Under the RF frequency, interconnection 13 and 41 can be used as transmission line, and therefore is also referred to as input transmission line (IP-TL) 13 and output transmission line (OP-TL) 41.Outside connection 11 (for example, wire bond or other interconnection) are seen input impedance Z ' at input joint sheet (IP-BP) 12 places In, and outside connection 19 (for example, wire bond or other interconnection) are seen output impedance Z ' at output joint sheet (OP-BP) 35 places OutInput interconnection (for example, transmission line (IP-TL)) 13 will be imported joint sheet (IN-BP) 12 and be coupled at grid 14 places and have intrinsic input impedance Z InMOSFET 24, and output interconnection (for example, transmission line (OP-TL)) 41 will have intrinsic output impedance Z at drain electrode 16 places OutThe drain electrode output 16 of FET 24 be coupled to output joint sheet (OP-BP) 35.Fig. 2 shows simple equivalent circuit Figure 10 ' of the block diagram 10 of Fig. 1.Electricity is led G1, G2, capacitor C 1, C2, inductance L 1 and resistance R 1 expression IN-BP 12.Electricity is led G3, G4, capacitor C 3, C4, inductance L 2 and resistance R 2 expression IN-TL 13.Use intrinsic impedance Z InAnd Z OutAnd amplifier A represents transistor 24.Electricity is led G5, G6, capacitor C 5, C6, inductance L 3 and resistance R 3 expression OP-TL 41.Electricity is led G7, G8, capacitor C 7, C8, inductance L 4 and resistance R 4 expression OP-BP 35.
Because intrinsic transistor terminal impedance Z in and Zout be along with frequency and grid periphery and convergent-divergent, so along with the frequency of operation of transistor 24 and/or the increase of grid periphery, intrinsic transistor terminal impedance Z InAnd Z OutDiminish.Ignore the Light Difference that between grid length and channel length, may exist, the grid periphery be grid width add grid length and twice.Because effectively, increasing FET operates concurrently, so the grid periphery increases along with the power handling capability that increases.This is at a plurality of " finger pieces " by the use Parallel coupled---and among the various FET of each finger piece formation independent F ET is visible.Therefore, reducing of intrinsic impedance is to make device operate needed direct result under higher-wattage and/or upper frequency, especially in approximately 1GHz or above operation.Along with intrinsic impedance Z InAnd Z OutDiminish, interconnection as shown in Fig. 1-2 (for example, IP-TL 13, OP-TL 41) and joint sheet (for example, IP-BP 12 and OP-BP 35) spurious impedance may become leading, making becomes be difficult to or can not efficiently energy be coupled in the device 24 and device 24 outside.These spurious impedances can be served as signal and be stolen (stealing) voltage divider.For example, with reference now to Fig. 2, Z InDivided by Z InAdd Z (IN-BP)+ Z (IP_TL)With recently provide and appear at the mark that grid 14 places are used for the input signal that exists at terminal 11 places of driving transistors 24, wherein, Z (IN_BP)Be the series impedance that exists owing to input joint sheet (IN-BP) 12, and Z (IP_TL)It is the series impedance that exists owing to input transmission line (IN-TL) 13.Be intended to be used for (thereby having less Z at upper frequency and/or higher-wattage In) operation, by the electronic component of block diagram 10 expression and equivalent electric circuit 10 ' situation under, a Z (IN-BP)+ Z (IP-TL)Begin to become to take as the leading factor, and this voltage divider action has reduced the driving amount that arrives transistor 24.In the drain electrode 16 of transistor 24 and the output generation similar effects between the lead-out terminal 19.Come convergent-divergent joint sheet and transmission line impedance when the impedance of intrinsic input and output device is with frequency and/or power handling capability convergent-divergent unless take steps, otherwise can't reasonably realize overall higher frequencies of operation and higher-wattage disposal ability.
Therefore, exist for the needs of improved device architecture and manufacture method, therefore it reduced the parasitic E-M coupling that is associated with the terminal of such high-frequency device and IC and coupling element, is generally joint sheet and is used for interconnection that such high-frequency element and/or IC are coupled to such joint sheet and outside lead and/or other assembly.
Description of drawings
Hereinafter will describe the present invention in conjunction with the following drawings, wherein, identical Reference numeral is represented components identical, and in the accompanying drawings:
Fig. 1 is that its grid is coupled to the simplification electrical schematic block diagram that input joint sheet and its drain electrode are coupled to the field-effect transistor (FET) of output joint sheet;
Fig. 2 is the simple equivalent circuit figure of the block diagram of Fig. 1;
Fig. 3 is the simplified schematic plane graph that comprises the electronic device of field-effect transistor in the active device area and the coupling joint sheet in the joint sheet zone;
Fig. 4 be according to prior art with comprise active device area in field-effect transistor and the simplified schematic cross-sectional view of the consistent electronic device of the Fig. 3 of the coupling joint sheet in the joint sheet zone;
Fig. 5 be with comprise active device area in field-effect transistor and the simplified schematic cross-sectional view of consistent another electronic device of the Fig. 3 of the coupling joint sheet in the joint sheet zone;
Fig. 6 is the simplified schematic cross-sectional view that comprises the electronic device of field-effect transistor in the active device area and the coupling joint sheet in the joint sheet zone according to an embodiment of the invention;
Fig. 7-the 8th is according to the simplified schematic plane graph of the electronic device of Fig. 6 that comprises field-effect transistor in the active device area and the coupling joint sheet in the joint sheet zone of other embodiments of the invention;
Fig. 9-the 14th is according to the simplified schematic plane graph of the various dielectric area below the joint sheet zone of the device of Fig. 6-8 of other embodiments of the invention;
Figure 15-23 shows according to the Fig. 6 that passes through to be applicable to the support engages pad-8 of other embodiments of the invention and the simplified schematic cross-sectional view of the Semiconductor substrate of the different fabrication stages of the dielectric area of Fig. 9-14;
Figure 24-26 shows the simplified schematic cross-sectional view according to the Semiconductor substrate of the different fabrication stages of the dielectric area of Fig. 6 that passes through to be applicable to the support engages pad-14 of other embodiments of the invention; And
Figure 27-31 shows the simplified schematic cross-sectional view according to the Semiconductor substrate of the different fabrication stages of the dielectric area of Fig. 6 that passes through to be applicable to the support engages pad-14 of other embodiments of the invention.
Embodiment
It in fact only is exemplary below describing in detail, and and is not intended to restriction the present invention or application of the present invention and use.In addition, do not wish to be subjected to the restriction of any express or implied theory of presenting in formerly technical field, background technology or the following detailed description.
For illustrated simple and clear, accompanying drawing illustrates the general fashion of structure or fabrication stage, and can omit the description and the details of well-known characteristic and technology, to avoid unnecessarily obscuring the present invention.In addition, the element among the figure is not necessarily described in proportion.For example, the size of some elements in the accompanying drawing or zone or layer can be amplified to help lend some impetus to the understanding to embodiments of the invention with respect to other element or zone or layer.
(if any) such as term in specification and claim " first ", " second ", " the 3rd ", " the 4 " can be used for distinguishing between similar elements, and not necessarily is used to describe specific continuous or time sequencing.The term that should be appreciated that such use is interchangeable in appropriate circumstances, make embodiments of the invention described herein for example can with except this paper diagram or otherwise describe those order operate or make.In addition, term " comprises ", " having " and any variant thereof and be not intended to and contain nonexcludability and comprise, make to comprise that process, method, object or the equipment of a row element or step not necessarily are confined to those elements or step, but can comprise clearly do not list or such process, method, object or equipment intrinsic other element or step.Term as used herein " coupling " is defined as the direct or indirect connection with electricity or non-electric mode.
Term as used herein " semiconductor " is intended to comprise any semiconductor usually, no matter be monocrystalline, polycrystalline or amorphous, and comprises IV N-type semiconductor N, non-IV N-type semiconductor N, compound semiconductor and organic and inorganic semiconductor.In addition, term " substrate " and " Semiconductor substrate " are intended to comprise mono-crystalline structures, polycrystalline and non crystalline structure, membrane structure, stepped construction (for example but do not wish it is restrictively, semiconductor-on-insulator (SOI) structure) and combination thereof.Term " semiconductor " is abbreviated as " SC ".The term " wafer " of odd number or plural number is intended to refer to compare relative thin and supporting construction that combine and use with the batch manufacturing of electronic device with its lateral surfaces area with " substrate ".The such wafer and the non-limiting example of substrate comprise: the supporting construction of semiconductor crystal wafer, SOI wafer and other type, make active therein or in the above and/or passive electronic components, perhaps the manufacturing of itself and such element is used in combination.
For the ease of explaining and being not intended to is restrictive, the electronic structure that this paper has described various embodiment of the present invention at Si semiconductor with by the dielectric that silica forms (for example, active and passive device and element and combination thereof) and manufacture method, but it will be understood by those of skill in the art that and to use other semiconductor and dielectric substance.And, for the ease of explaining, can illustrate or describe the active device of MOSFET device and/or ldmos transistor form, but this and to be not intended to be restrictive, and those skilled in the art is to be understood that, in the active device area of various embodiment of the present invention, can use the active device of any kind, and the term metal-oxide semiconductor (MOS) that combines with any such device (with abbreviation MOS) not only is confined to oxide gate dielectric and/or metal gates or source electrode-drain conductor, and the insulation dielectric (organic or inorganic) that also comprises any kind replaces the conductor (organic or inorganic) of " oxide " and any kind to replace " metal " in such device.
In the following description, described and be coupled to active device (for example, the various examples of the joint sheet of lead-out terminal MOSFET) (for example, drain electrode), but this only is that to be not intended to for convenience of description be restrictive.It will be understood by those of skill in the art that this paper also is applicable to device input terminal and related input joint sheet and interconnection with the discussion that interconnection provides with example about device output end and related output joint sheet.In addition, be used to provide performance, the cost of improvement to reduce and the structure of efficient and method is applicable to the electronic structure that forms that is not connected to substrate on Semiconductor substrate all terminals, that is, be applicable to that its E-M substrate coupling may cause all devices and the element terminal of ill-effect.
Fig. 3 is the simplified schematic plane graph, and Fig. 4 is the simplified schematic cross-sectional view that comprises the electronic device 20 of the MOS field-effect transistor (FET) in the active device area 22 that interconnection 41 by coupling regime 38 is coupled to the joint sheet 35 in the joint sheet zone 34.Fig. 4 is according to prior art.Electronic device 20 comprises Semiconductor substrate 21 (for example, silicon), has wherein formed the doped well region 23 that forms MOSFET 24 therein.Suppose that substrate 21 is low resistivity materials, for example have sheet resistance, but can also use higher or lower value less than about 0.1Ohm-cm.What be arranged in well area 23 is isolated element: (i) have the source region 25 of source contact 26, and the drain region 27 that (ii) has drain contact 28.The channel region of being put by gate oxide 31 and grid 30 29 is between source electrode-drain region 25,27.When device 24 was energized, electric current flowed between source electrode 25 and drain electrode 27 by an induced channel zone 29, and the polarity of electric current depends on that transistor 24 is N raceway groove or P channel-type FET.Though it is MOSFET that transistor or device 24 are illustrated as, and can replace the active device of any kind, for example but and to be not intended to be restrictive, JFET device, LDMOS device, bipolar device etc.No matter be identified as mosfet transistor or device 24, device 24 is intended to also represent other such type of device, and drain electrode 28 also is intended to represent the main terminal of other such type of device.
Joint sheet 35 41 is coupled to drain electrode 28 by interconnecting.For FET, joint sheet 35 has the width 351 in about 3 to 7 millimeters scopes usually under the situation of total grid periphery of about 80mm, and the length 352 in about 75 to 200 millimeters scopes, perhaps about 0.225 to 1.4mm 2Area in the scope, but greater or lesser value can also be used.Interconnection 41 has usually according to the width 411 in about 7 to 60 micrometer ranges of the millimeter of grid periphery, but can also use bigger and littler value, and 41 the length 412,412 of interconnecting ' can change within a large range according to designer's needs.Interconnection 41 is by 21 insulation of dielectric area 32 (for example, silica) and substrate, and joint or connection gasket 35 are by the dielectric area 36 (for example, silica) and substrate 21 insulation of thickness 361.The I/O of effective area that term " joint sheet " and " pad " of employed odd number of this paper or plural number is intended to refer to be used for any kind of electronic device as herein described is connected.In Fig. 4, between active device area 22 and joint sheet zone 34, there is the coupling regime 38 of the length 39 of the length 412 that is similar to Fig. 3.Though (for example in Fig. 3-4, only show a joint sheet, pad 35) (and in subsequent figure similarly), but it will be understood by those of skill in the art that common existence is coupled to grid 30 or other similar substantially joint sheet that source terminal is arranged of transistor 24.
When the device 20 with transistor 24 is energized, form around the joint sheet 35 of electromagnetism (E-M) field 33 in joint sheet zone 34.Owing to compare relative large-area joint sheet 35 and short relatively interconnection 41 with drain contact 28, can dominate with the pad 35 E-M fields 33 that are associated and high frequency (for example, the RF) ghost effect that is associated of the character of device 20.Penetrate in E-M field 33 on the degree of low-resistivity substrate 21, parasitic couplings may take place, it for example makes by matching terminal I/O impedance and cannot or hardly realize suitable input-output (I/O) impedance matching and be coupled in the transistor 24 and outer, reduce the performance of device 20, discussed as mentioned.Under these circumstances, the power handling capability of device 20 and maximum frequency of operation may seriously be reduced.
Fig. 5 be comprise be coupled to joint sheet zone 34 ' in the active device region 22 of joint sheet 35 in field-effect transistor (FET) 24 electronic device 20 ' the simplified schematic cross-sectional view.The electronic device 20 of Fig. 5 ' since provide pad below 35 (for example, silica) dark relatively dielectric area (DDR) 36 ' (that is, have in fact thickness 361 ') and be different from the electronic device 20 of Fig. 4 greater than the thickness 361 of the field oxidation dielectric area 36 of Fig. 4.The degree of depth 361 ' practicably be equal to or greater than about 5 microns is equal to or greater than about 10 microns more easily, and preferably is equal to or greater than about 15 microns, but can also use bigger and littler value.Because the existence of DDR 36 ', E-M field 33 is mutual with substrate 21 no longer so significantly.Though interconnect 41 ' and substrate 21 between the E-M coupling can according to interconnection 41 ' length 39 ', 412 ' (with width 411) and below the thickness of dielectric 32 and greater or lesser, fill up 35 and substrate 21 between E-M be coupled and reduced widely.Therefore, be easier to coupling, and eddy current losses and other ghost effect of otherwise being present in the layout of Fig. 4 can be not too remarkable with pad 35 impedances that are associated.Therefore, compare with the layout of Fig. 4, the layout of Fig. 5 can reduce total device performance and reduce.
Yet, found to occur to make less-than-ideal another problem of layout of Fig. 5.This is relevant with the mechanical stress that produces in substrate 21 owing to the existence of DDR 36 '.For example, can be used for forming the thermal coefficient of expansion (TEC) of silica of DDR 36 ' greater than the TEC of the substrate 21 of for example silicon.This produces significant stress in substrate 21, because device 2 experiences various thermal cycles during manufacture and afterwards.This stress may influence the character of any active device 24 that is arranged in active device area (ADR) 22 negatively.It is near more apart from active device area (ADR) 22 that DDR 36 ' is placed, that is, coupling regime 38 ' length 39 ' and interconnection 41 ' length 412 ' more little, the mechanical stress that is produced by DDR 36 ' may be big more to the illeffects that active device 24 has.No matter use the active device 24 of what type in active device area (ADR) 22, situation is like this usually, and is not limited only to the exemplary MOSFET24 shown in the figure.Therefore, the minimizing of the parasitic E-M effect that provides for the structure of under the situation of the harmful stress induction effect during near ADR 22, utilizing by Fig. 5 without undergoing DDR 36 ', must increase usually coupling regime 38 ' length 39 ' and interconnection 41 ' length 412 '.This has caused device 20 ' take bigger area (being called " area expansion "), this so that reduce can on single wafer, make simultaneously incorporate into device 20 ' device and the number of IC.This causes higher manufacturing cost.In addition, by increase coupling regime 38 ' length 39 ' caused interconnection 41 ' length 412 ' increase may increase the series impedance of not expecting, as explaining in conjunction with Fig. 1-2, thus go back limiting device 20 ' overall performance.
Fig. 6 is by the mode of example, shows according to an embodiment of the invention the simplified schematic cross-sectional view by the electronic component 44 that comprises MOSFET 24 in the active device area (ADR) 46 on the common semiconductor substrate 21 and the joint sheet 35 in the joint sheet zone 60.Fig. 7-the 8th is according to the simplified schematic plane graph of the electronic device of Fig. 6 of other embodiments of the invention.Consider Fig. 6-8 together, ADR 46 separates with joint sheet zone 60 by the coupling regime 63 of length 64.ADR 46 and exemplary active device 24 basically with in conjunction with shown in the ADR22 of Fig. 3-5 and the device 24 and described identical, and incorporated description wherein in this article by reference into.MOSFET 24 is conventional, and the active device of expression any kind.Joint sheet 35 in the joint sheet zone 60 covers on the composite dielectrics zone (CDR) 62 of the degree of depth 624 and lateral dimension 621,622 (referring to Fig. 6～8).The lateral dimension 621,622 of being selected CDR 62 by the designer is to hold the width 351 that is placed on the composite dielectrics zone (CDR) 62 and the joint sheet 35 (referring to Fig. 7-8) of length 352.The degree of depth 624 of CDR 62 should be enough to reduce basically during device operation the mutual of the E-M field 33 that generated by joint sheet 35 and substrate 21.In most of the cases, the degree of depth 624 is generally equal to or greater than about 5 microns, is equal to or greater than about 10 microns more easily, and preferably is equal to or greater than about 15 microns.
Have been found that can by the composite dielectrics zone (CDR) 62 below joint sheet 35 that Fig. 6-8 is provided improve or avoid may with influence of dark dielectric area 36 ' negative circuit loss that is associated of Fig. 3, negative manufacturing qualification rate and negative layout density influence (area expansion), wherein zone 62 comprises floating column of a plurality of electricity or foliaceous polycrystalline or amorphous (promptly, on-monocrystalline) zone or inclusion (inclusion) 65, it is separated from one another by dielectric (for example, oxide) part 78.Substrate 21 is in the preferred embodiment of silicon therein, and inclusion 65 is polysilicons, but can also use other material with suitable thermal coefficient of expansion (TEC).Inclusion 65 has width 80, spacer 89 and center distance 66.Have been found that the structure shown in Fig. 6 does not produce the stress of not expecting that the layout as Fig. 5 may occur in substrate 21, thereby and minimize or avoid owing to such stress cause to making the negative effect that qualification rate, device property and area expand.With incorporate into dark dielectric region 36 ' and do not have the element 20 of Fig. 5 of inclusion 65 ' ADR 22 in the stress that may exist compare, reduced greatly at adjacent active device region (ADR) 46 of the electronic component 44 of the Fig. 6-8 that incorporates composite dielectrics zone (CDR) 62 into and the stress in the substrate 21.Therefore, the element 44 of substrate 21 that comprises the CDR 62 that has below joint sheet zone 60 and have the adjacent ADR 46 of Fig. 5-8 not only is coupled by means of the E-M that reduces that is coupled to substrate 21 from joint sheet 35 and presents superior performance characteristics, but also loss of excessive manufacturing qualification rate and the area having avoided being associated with the layout of Fig. 5 expand.Had been found that with the manufacturing qualification rate of the structurally associated connection of the element 44 of Fig. 6 obviously greater than with the manufacturing qualification rate of another similar elements 20 of Fig. 5 ' be associated.Also finding can not have to make the length 64 of coupling regime 63 be made less about CDR 62 under the situation of negative effect usually, and bigger basically coupled zone 38 ' possibility of Fig. 5 must be provided at the pad area 34 of the element 20 among Fig. 5 ' and active device area 22 between so that reduce by the influence of the stress of dark oxide areas 36 ' generation to active device area 22.For example but and to be not intended to be restrictive, can be so that the coupling regime length 64 that joint sheet zone 60 is separated with active device region 46 in the device 44 be little of 20 microns, and with the structure of Fig. 3, device 20 ' pad area 34 and the coupling regime length 39 between the active device area 22 must be generally about 100 to 200 microns so that avoid negative stress effect.Therefore, avoided to dark oxide areas 36 ' the negative effect of circuit package density.Generally speaking, by using the structure of Fig. 6: (i) reduced to joint sheet and interconnection impedance and to the negative parasitic E-M coupling influence of substrate loss, (ii) improved overall circuit efficient, (iii) minimize or avoid substrate stress and to the negative effect of active device character, and (iv) can place joint sheet zone 60 to such an extent that more approach active device area 46, thereby avoided otherwise the loss (being that area expands) of the circuit package density that layout ran into of Fig. 5 and long interconnection 41 ' the impedance of increase.These beneficial effects are high expectations, and than prior art obvious improvement are arranged.
Fig. 7-8 illustrates the various geometrical arrangements of the inclusion 65 of being separated by the dielectric area among the CDR 62 78 with plane graph, CDR 62 be identified as for convenience's sake Fig. 7 have inclusion 65-1 and the CDR 62-1 that separates dielectric area 78-1 and Fig. 8 have inclusion 65-2 and a CDR 62-2 that separates dielectric area 78-2.These are referred to as CDR 62, inclusion 65 and intermediate dielectric (for example, oxide) zone 78.Inclusion 65-1 and 65-2 stride CDR 62-1,62-2 and extend, and about the orientation of device 24 each other in oriented at right angles.In Fig. 7, the longer size of inclusion 65 is not to point to the direction orientation (for example, meeting at right angles with device area 46) of active device area 46.In Fig. 8, the longer size of inclusion 65 is to point to the direction orientation of active device area 46.The orientation of the inclusion 65 among Fig. 8 is preferred.Yet, this and to be not intended to be restrictive, and can use any angular orientation of inclusion 65 about the device in the device area 46 24.
Fig. 9-14 shows the simplified plan view of various dielectric area (CDR) 62-3 to 62-8 (general designation 62), various dielectric area 62-3 to 62-8 comprise the electricity that is laterally separated by dielectric area 78-3 to 78-8 (general designation 78) respectively and (for example float, polycrystalline or amorphous semiconductor) inclusion 65-3 to 65-8 (general designation 65), and be suitable in the improvement joint sheet zone 60 of the integrated electronics 44 of Fig. 6-8, using.As in conjunction with Figure 15-23 explain that inclusion 65 preferably forms in groove, and any one in the illustrated layout in-14 that in plane graph, can have Fig. 7.Inclusion 65 can be arranged to the substantially parallel row as shown in for example Fig. 7-8, perhaps as staggered row for example shown in Figure 9, perhaps " L " as shown in for example Figure 10 or "T"-shaped layout, perhaps arrange, perhaps the concentric rectangles as shown in for example Figure 12-14, concentric circles or concentric polygon by dielectric area 78 separation as opening in the wherein grid for example shown in Figure 11 and dielectric region 78 corresponding lattice-shapeds.During these are arranged any one all is suitable, and provides by the mode of example rather than in the mode that limits.Can also use other 2 d plane picture of inclusion 65 to arrange.Have at joint sheet 35 under the situation of circle or polygon plane figure design, arrange it is useful especially as the circle or the polygon of illustrated CDR 62 and inclusion 65 in Figure 13～14.
Figure 15-23 shows and passes through to be applicable to the simplified schematic cross-sectional view in the Semiconductor substrate 45 of the different fabrication stage 115-123 of the CDR 62 of the junction pad area 60 of Fig. 6 that supports one or more joint sheets 35 according to other embodiments of the invention.In Figure 15-23, illustrate the formation of CDR 62, and omitted the conventional steps that relates in the manufacturing of the active device in contiguous ARD 46 widely.Therefore, not shown ADR 46 in Figure 15-22, and only be included among Figure 23.Can before the manufacturing step 115-122 of Figure 15-22, during or (for example in ADR 46, make one or more active devices afterwards, referring to Fig. 6), and only in the mode of example and to be not intended be restrictive, such manufacturing was included in the fabrication stage 123 of Figure 23.The substrate 45 of Figure 15-23 is similar to the substrate 21 of Fig. 6, but is illustrated as the epitaxial loayer 48 that has specific conductivity-type and comprise the upper surface 57 that extends to substrate 45.This only is intended to the various substrates of illustration, because such doping type and epitaxial loayer are particularly useful to the LDMOS device, and to be not intended be restrictive.The existence of the doping type of substrate 45 and epitaxial loayer 48 or do not exist formation to have no significant effect to CDR 62, and in various embodiment of the present invention, can be comprised or omit.
With reference now to the fabrication stage 115 of Figure 15,, in a preferred embodiment, provides the P+ silicon substrate 45 of the upper area 48 of thickness 481 with surface 57 and for example doped with P type extension.In other embodiments, the light dope well area can be replaced the epi region 48 in the active device area 46.Thickness 481 is practical in about 1 to 15 micron scope, more easily in about 5 to 13 microns scope, and preferably in about 9 to 13 microns scope, but can also use thicker and thinner layer in other embodiments, can omit upper area 48 or provide upper area 48 by injection or other doping means.Whether need thickness 481 and will depend on that with the upper area 48 of substrate 45 identical or different doping the designer is desirably in the type of the device that forms in the ADR zone 46, and in those skilled in the art's the ability.Those skilled in the art also will understand, and be intended to example as preferred embodiment about the description of the silicon substrate of Figure 15-23 and silicon oxide dielectric, and not get rid of the semiconductor and the dielectric substance of other type in the mode of restriction.
The initial bed course 68 of the thickness of selecting at itself and the compatibility and the different etching of SC substrate 45 69 desirably is provided on SC surface 57.Silica is the suitable material that is used for initial bed course 68, but can also use other material.Thickness 69 is practical in about 0.02 to 0.2 micron scope, more easily in about 0.04 to 0.17 micron scope, and preferably in about 0.1 to 0.17 micron scope, but can also use thicker and thinner layer.Another joint sheet layer 70 of thickness 71 is provided on initial bed course 68.At the ability of the chemical reaction of its opposing such as oxidation of following SC substrate 45, it selects another joint sheet layer 70 with respect to the different etchings of following initial bed course 68 and as the practicality of complanation etch stop layer or polishing stop layer.Silicon nitride is the suitable material that is used for another bed course 70, but can also use other material.Thickness 71 is practical in about 0.02 to 0.2 micron scope, more easily in about 0.04 to 0.17 micron scope, and preferably in about 0.1 to 0.15 micron scope, but can also use thicker and thinner layer.On another bed course 70, provide hard mask layer 72.For example using tetraethoxysilane (TEOS) reactant is the non-limiting example that is used for the suitable material of hard mask 72 by the silica that chemical vapor deposition (CVD) forms, but can also use other durable mask material.Provide opening 73 by hard mask layer 72, another bed course 70 and initial bed course 68, thereby the zone 571 on SC surface 57 is exposed.The result obtains structure 215.
With reference now to the fabrication stage 116 of Figure 16,, guide preferentially and non-isotropy ground corrodes the etchant 90 of Semiconductor substrate 45 by mask open 73, extend in the epitaxial loayer 48 and/or by epitaxial loayer 48 and extend in the substrate 45 groove 74 to the degree of depth 741 with formation.The degree of depth 741 is practical in about 2 to 20 microns scope, more easily in about 9 to 20 microns scope, and preferably in about 15 to 20 microns scope, but can also use the bigger and littler degree of depth.The selection of the material that is used for SC substrate 45 is depended in the selection of etchant 90, and in those skilled in the art's the limit of power.For silicon substrate 45, HBr and SiF in the preferred helium oxygen mixture 4Be used for etchant 90, but can also use other non-isotropy etchant.Select the width and the spacing of opening 73, so that the groove 74 of the width 75 that the cylinder 76 by the width 77 of the SC material of substrate 45 separates is provided.Obtain structure 216.
With reference now to the fabrication stage 117 of Figure 17,, removed the hard mask layer 72 shown in Figure 16, and the semi-conducting material that exposes preferably is converted to dielectric in groove 74.For silicon substrate 45, the dielectric that obtains is silicon dioxide preferably.The high pressure of silicon substrate 45 or steam oxidation (stream oxidation) method is the preferred means that is used for being formed by the SC material that exposes at groove 74 oxide areas 78.Carry out oxidation in this embodiment, all the SC materials basically in SC substrate post or cylinder 76 all are converted into silica.The silicon dioxide that oxidation produced by silicon post or cylinder 76 has taken than the bigger volume of silicon that is consumed between the heat of oxidation.Therefore, groove 74 narrows down along with the carrying out of oxidation.Select groove width 75 and cylinder width 77 (by the suitable selection of initial mask open 73 and spacing), make not closedly, but between adjacent oxide columns 78, stay the empty groove or space (void) 79 of width 80 by the formed oxide areas of the oxidation of cylinder 76.Width 80 is practical in about 0.2 to 5.0 micron scope, more easily in about 0.2 to 3.0 micron scope, and preferably in about 0.3 to 0.7 micron scope, but can also use wideer or narrower space.For instance and to be not intended to be restrictive, suppose that SC cylinder 76 is converted to oxide fully in the fabrication stage 117, for the gap groove 79 that obtains about 0.5 micron width 80, about 4.5 microns initial trench width 75 (referring to Figure 16) that use is separated by about 2.7 microns initial substrate cylinder width 77, thus provide between about 7.2 microns initial trench center line to separate 67.The centreline spacing 66 of inclusion 65 will approximate the centreline spacing 67 of groove 74.By adjusting initial trench width 75 and cylinder width 77, can be obtained the residual clearance groove 79 of different in width 80 after converting oxide to fully at SC substrate cylinder 76.In other words, desired width 75 is about 8-10 a times of width 80, and expectation centreline spacing 66 is about 13-16 times of width 80.Obtain structure 217.
With reference now to the fabrication stage 118 of Figure 18,, non-single-crystal material (for example, polycrystalline or amorphous silicon) layer 82 forms the thickness 81 that is enough to inclusion 83 filled chambers 79 will (for example, to pass through CVD) on joint sheet zone 60.For the ease of explaining, hypothetical layer 82 and inclusion 83 are polycrystalline or amorphous silicon (that is, non-monocrystalline silicon) hereinafter, but can also use have littler and/or more approach other material of the thermal coefficient of expansion (TEC) of substrate 45 than dielectric 78.The combination of amorphous and/or polycrystalline (for example, on-monocrystalline) silicon or germanium or silicon and germanium is the non-limiting example that is suitable for silicon or germanium or silicon-other material that germanium substrate 45 uses.Obtain wherein in groove 79, forming the structure 218 of polycrystalline for example or amorphous silicon inclusion 83.By considering Fig. 6-18, with what recognize is that inclusion 83 can have column or bar shape or foliaceous structure, promptly, its width 80 is usually significantly less than its height 791, and significantly less than its with Fig. 6 direction vertical with the plane of Figure 15-23 on the degree of depth, as what in the plane graph of Fig. 7-14, can see.
With reference now to the fabrication stage 119 of Figure 19,, be positioned at that part of layer 82 shown in Figure 18 of another bed course 70 tops and be removed, polycrystalline or amorphous silicon inclusion 83 are uninfluenced.Can use any plane technology.Etching (so-called resist back of the body etching technique) photoresist coating before at photoresist (not shown) and polycrystalline or amorphous silicon layer 82 is the non-limiting example of suitable planarization technology, but can also use the redundance that removes the layer 82 of layer 70 top such as other planarization technique of chemico-mechanical polishing (CMP).In addition, bed course 70 can be used as complanation etch stop layer or polishing stop layer, and promotes planarization technology.Obtain structure 219.
With reference now to the fabrication stage 120 of Figure 20,, removes part 84 at the top of polycrystalline or amorphous silicon inclusion 83 by of short duration (for example, silicon) etching.Removed part 84 is included in the groove 79 (referring to Figure 19) and more preferably is positioned at the top of the inclusion 83 of 57 tops, SC surface, but can also use darker or more shallow etching.Employed special etch agent will be depended on the selection of the material of inclusion 83, and in those skilled in the art's the limit of power.In inclusion 83 is under the situation of polycrystalline or amorphous silicon, and HBr and/or HCl are suitable etchants.Obtain structure 220.
With reference now to the fabrication stage 121 of Figure 21,, in the fabrication stage 120, expose that part of (for example, polycrystalline or amorphous silicon) inclusion 83 is for example oxidized with at dielectric (for example, silica) regional 78 electricity that are embedded in (are for example isolated, polycrystalline or amorphous silicon) form dielectric region 85 on the inclusion 65, thereby form and to incorporate electricity into and isolate regional (CDR) 62 of illustrated composite dielectrics (isolations) among Fig. 6 of the width 622 of (for example, polycrystalline or amorphous silicon) inclusion 65 and the degree of depth 624 (referring to Fig. 6) or 781 (referring to Figure 21) and Figure 21.Obtain structure 221.With reference now to the fabrication stage 122 of Figure 22,, on composite dielectrics zone (CDR) 62, forms another dielectric layer 86 that is preferably silicon nitride and has thickness 87.Obtain structure 222.With reference now to the fabrication stage 123 of Figure 23,, use means well known in the art to come in ADR 46, to form easily active device 24.In this example, active device 24 is to have source electrode-drain electrode (or drain electrode-source electrode) zone 25,27 of contact 26,28 and the MOSFET that has the gate-dielectric 31 of grid 30 above raceway groove 29 respectively, but this only is the mode with example, and it is restrictive being not intended to, and before any fabrication stage 115-123 of Figure 15-23 or during, can be equal in ADR 60, form the active device of any other type.Though layer 86 is illustrated as being merged in the top of CDR 62 of Figure 23, usually and the preparation of active device 24 bed course 68,70 and layers 86 is incorporated in the field oxide region or with field oxide region replaced relatively, and in Figure 23, be left in the basket usually. Contact 26,28 with active device 24 above the CDR 62 in joint sheet zone 60 forms joint sheet 35 simultaneously easily, but in other embodiments, can earlier or more lately form joint sheet 35 in manufacturing process.Any sequence is practical.Be with or without under the situation of various stabilisation dopants, the expectation tool is for example and and to be not intended to be that the passivation layer 40 of restrictive silica, silicon nitride or its combination is applied on joint sheet zone 60 and the ADR 46.Obtain structure 223.Then, electronic component 44 is done basically.Indicated for example interconnection 41 between the drain metallization zone 28 and junction pad area 35.Because CDR 62 can be placed to such an extent that be in close proximity to ADR46, for example in about 20 microns of ADR 46, so can be so that the coupling regime 38 of the length 39 between junction pad area territory 60 and the ADR 46 is very short.
Inclusion 65 can have in about scope of 2 to 200, more easily about 15 to 50 and preferably about aspect ratio of 20 to 30, it is defined as its vertical height divided by its horizontal width 80 (referring to Fig. 6 and 21-23), but can also use bigger and littler value.Its with Fig. 6 direction vertical with the plane of Figure 20-23 on length can be big doubly more a lot of than width 80, and will depend on the lateral dimension of the joint sheet 35 that covers CDR 62, can recognize as the plane graph that in Fig. 7-14, presents by inspection.
Figure 24-26 shows and passes through to be applicable to the cross-sectional view in the Semiconductor substrate 45 at the different fabrication stage 124-126 place of the CDR 62 of Fig. 6 and Fig. 7-14 that supports one or more joint sheets 35 according to other embodiments of the invention.With Figure 24-26 relatively, adopt to identify with those similar various zones of Figure 15-23 and by using and cast aside with symbol that same reference numerals that (') replenish identifies and those various regional agreements similar but may be different in some aspects of Figure 15-23 with identical Reference numeral.For example, substrate 45 can be identical, and therefore in accompanying drawing 24-26, use and identify with Reference numeral 45 identical in Figure 15-23, though and the groove 74 of Figure 24-26 ' and cylinder 76 ' be similar to groove 74 and the cylinder 76 of Figure 15-23, but may be slightly different, therefore identify with same reference numerals with additional (').The fabrication stage 124 that produces Figure 24 of structure 224 is similar to the fabrication stage 116 of the Figure 16 that produces structure 216, and has incorporated into by reference in this article its discussion and last fabrication stage 115 thereof.Differently aspect fabrication stage 124 and structure 224 be, select groove width 75 ' and cylinder width 77 ' (by means of adjust mask open 73 '), make in the subsequent stage of fabrication 125 of Figure 25, SC substrate cylinder 76 ' do not have to finish as in the fabrication stage 117 of Figure 17, being oxidizing to, but not oxidation SC substrate cylinder 92 (referring to Figure 25) of width 93 are stayed original position moving (undisturbed), embed comprise width 80 ' gap groove 79 ' oxide areas 78 '.Width 80 ' can be identical or different with the width 80 of Figure 17-23.As the situation of fabrication stage 117 of Figure 17, in the fabrication stage 125 of Figure 25, groove 74 ' narrow down along with the carrying out of oxidation.Select groove width 75 ' and cylinder width 77 ' (by initial mask open 73 ' and the suitable selection of spacing), make by cylinder 76 ' the oxide areas that forms of partial oxidation do not have closure, but adjacent oxide columns 78 ' between stay width 80 ' empty groove or space 79 '.Width 80 ' in about 0.2 to 5.0 micron scope, be practical, more easily in about 0.2 to 3.0 micron scope, and preferably in about 0.3 to 0.7 micron scope, but can also use wideer or narrower space.For instance and to be not intended be restrictive, for when staying the moving SC substrate cylinder 92 of width 93, obtain about 0.5 micron width 80 ' gap groove 79 ', use by the initial trench width 75 of about 3.7 microns initial substrate cylinder width 77 ' separation about 4.5 microns (referring to Figure 24) ', suppose SC substrate cylinder 76 ' oxidation before converting oxide to fully, be terminated in the fabrication stage 125 at it.By adjusting initial trench width 75 ' and cylinder width 77 ' and oxidization time, SC substrate cylinder 76 ' be embedded in dielectric area 78 ' in partly converted to oxide when staying the SC substrate cylinder 92 of width 93 after, can obtain residual clearance groove 79 ' different in width 80 '.Obtain structure 225 from the fabrication stage 125 of Figure 25.Then, structure 225 experiences the substantially the same fabrication stage that is associated with Figure 18-23, and its discussion is incorporated into herein by reference.Fabrication stage 126 of Figure 26 is similar with the fabrication stage 123 of Figure 23, difference be the residual SC substrate cylinder 92 of width 93 and spacing 94 be merged in electronic component 44 ' CDR 62 ' in.Can before the formation of CDR 62 ' and joint sheet 35, during or form active device 24 afterwards.
Figure 27-31 shows and passes through to be applicable to the cross-sectional view in the Semiconductor substrate 45 of the different fabrication stage 127-131 of the CDR 62 of Fig. 6 and Fig. 7-14 that supports one or more joint sheets 35 according to other embodiments of the invention.With Figure 27-31 relatively, adopt with same reference numerals to identify with those similar various zones of Figure 15-23 and by using with double quotation marks (") additional same reference numerals identifies and the similar but agreement in various zones that may be different in some aspects of those of Figure 15-23.For example, substrate 45 can be identical, and therefore in Figure 27-31, use and identify with Reference numeral 45 identical in Figure 15-23, and the groove 74 of Figure 27-31 " and cylinder 76 " is though be similar to groove 74 and the cylinder 76 of Figure 15-23, but may be slightly different, and therefore with having additional (") same reference numerals identify.The fabrication stage 127 that produces Figure 27 of structure 227 is similar to the fabrication stage 116 of the Figure 16 that produces structure 216, and incorporates into by reference herein its discussion and last fabrication stage 115.The fabrication stage 127 of Figure 27 and the difference in the structure 227 are, select groove width 75 " and cylinder width 77 " (by means of adjusting mask open 73 "); make in the subsequent stage of fabrication 128 of Figure 28, can be by deposition rather than substrate cylinder 76 " oxidation produce dielectric area 78 " and space 79 ".In the fabrication stage 127 of Figure 27, in substrate 45 with the part of the bed course 68,78 on the top of substrate cylinder 76 " (comprise cover cylinder 76 ") width 75 that separated " groove 74 " be etched to the degree of depth 741 ".Obtain structure 227.With reference now to the fabrication stage 128 of Figure 28,, preferably conformally on structure 227, forms the dielectric layer 96 of thickness 97.The CVD silica is the suitable material that is used for layer 96.Can use any CVD technology, but adopting the deposition of TEOS is easily.Select thickness 97, make layer 96 a coating groove 74 " sidewall, stay the not filling space 79 that is positioned at groove 74 " width 80 " basically in the center ".Obtain structure 228.
With reference now to the fabrication stage 129 of Figure 29,, on structure 228, form the thickness 81 " layer 82 " of the layer 82 be similar to Figure 18, thereby coming filling gap groove 74 and to produce inclusion 83 with gap groove 74 and inclusion 83 described roughly the same modes at fabrication stage 118 of Figure 18, its discussion is incorporated into herein by reference.Obtain structure 229.Though the fabrication stage 129 of Figure 29 illustrates at layer 82 " depositional stage between mask 72 is stayed the situation of original position, in other embodiments, can before such deposition, remove mask layer 72.Any one layout or sequence are practical.With reference now to the fabrication stage 130 of Figure 30,, with structure 229 complanations, its discussion is incorporated into herein by reference in the roughly the same mode described with the fabrication stage 119 that had before combined Figure 19.Obtain structure 230.Also utilize the advantage that has another joint sheet layer 70, complanation polishing stop layer and/or etch stop layer that another joint sheet layer 70 is provided convenience.Then, make the similar fabrication stage of fabrication stage 120-123 of structure 230 experience and Figure 20-23, its discussion is incorporated into herein by reference, arrive fabrication stage 131 at last with fabrication stage 123 similar Figure 31 of Figure 23, difference is, the CDR 62 that the residual SC substrate cylinder 92 of width 93 " and spacing 94 " " is merged in electronic component 44 " " in.Have therein basically width 80 " and separating 89 " and center distance 66 " polycrystalline or amorphous inclusion 65 " are provided in the oxidation substrate cylinder 92 not " deposition dielectric region 78 ".Polycrystalline or amorphous inclusion 65 " be that electricity is floating; and residual substrate cylinder 92 " by at least a portion 70 of bed course 70,68 " and 68 " separates with joint sheet 35 with layer 86 or its equivalent that forms subsequently, is coupled to the E-M field that is produced by joint sheet 35 thereby limit it.Can be at CDR 62 " and before the formation of joint sheet 35, during or form active device 24 afterwards.
According to first embodiment, provide electronic component (44,44 ', 44 "), comprise semiconductor (SC) substrate (45), this semiconductor (SC) substrate (45) has first thermal coefficient of expansion (TEC) and active device area (46) and joint sheet zone (60); Be arranged in the joint sheet (35) of joint sheet zone (60); Be located at below the joint sheet (35) in the joint sheet zone (60) and comprise insulating material with TEC (78,78 ', the composite dielectrics zone of 78 ") (62,62 ', 62 "); In the composite dielectrics zone (62,62 ', another material in 62 ") (82,82 "; 83, the inclusion of 83 ") (65,65 ', 65 "), another material (82,82 "; 83,83 ") have the 3rd TEC less than the 2nd TEC, wherein, inclusion (65,65 ', 65 ") and substrate (45) and the isolation of joint sheet (35) electricity; And be arranged in active device region (46) and near the composite dielectrics zone (62,62 ', the active device (24) of 62 "), have by interconnection (41,41 ', 41 ") are electrically coupled to the first terminal of joint sheet (35).According to another embodiment, substrate (45) comprises silicon or germanium or its combination, and inclusion (65,65 ', 65 ") comprise the non-monocrystalline silicon form of silicon or germanium or its combination.According to another embodiment, inclusion (65,65 ', 65 ') has the width (80) in about 0.2 to 5.0 micrometer range.According to another embodiment, inclusion (65,65 ', 65 ") have width (80) with and about 13-16 of width (80) center line doubly to centreline spacing (66).According to another embodiment, inclusion (65,65 ', 65 ") have the aspect ratio in about scope of 2 to 200.According to another embodiment, inclusion (65,65 ', 65 ") have the aspect ratio in about scope of 15 to 50.According to another embodiment, inclusion (65,65 ', 65 ") have the aspect ratio in about scope of 20 to 30.According to another embodiment, inclusion (65,65 ', 65 ") comprise a plurality of substantially parallel foliaceous shapes (65-1,65-2,65-3) in plane graph.According to another embodiment, inclusion (65-2) has in plane graph towards the long size of active device orientation.According to another embodiment, inclusion (65-1) has the long size that is not orientated towards active device in plane graph.According to another embodiment, inclusion (65-6,65-7,65-8) forms substantially concentric shape in plane graph.According to additional embodiment, the composite dielectrics zone (62,62 ', 62 ") are positioned at about 20 microns or littler of active device area (46).
According to second embodiment, a kind of electronic component (44 that is used to form is provided, 44 ', 44 " method) (151-131); this electronic component incorporate in the below of the joint sheet that is coupled to active device (24) (35) composite dielectrics zone (CDR) (62; 62 '; 62 "), this method comprises: provide (115,124,127) has first thermal coefficient of expansion (TEC) and have the Semiconductor substrate (45) of first material of first surface (57), wherein, substrate (45) has the second area (60) that is applicable to the first area (46) of admitting active device (24) and is applicable to admittance joint sheet (35) therein; Go up to form (115,124,127) masks (72) at second area (60), this mask have first width (75,75 ', the isolated opening of 75 ") (73,73 ', 73 "); Will be basically in substrate (45) first width (75,75 ', the isolated groove of 75 ") (74,74 ', 74 ") etching (116,124,127) to first degree of depth (741,741 "), groove (74,74 ', stay between the other parts of substrate (45) material below 74 ") and the groove (74,74 ', 74 ") substrate (45) material that does not move basically cylinder (76,76 ', 76 "); Groove (74,74 ', form the dielectric that (117,125,128) have the 2nd TEC (78,78 ', 78 ") in 74 "), make dielectric (78,78 ', exist in 78 ") extend to from first surface (57) the groove (74,74 ', 74 ") but do not extend to groove (74,74 ', the space of locating in the center basically of the other parts of substrate (45) material below 74 ") (79,79 ', 79 "); Use with respect to substrate (45) electricity floating and have inclusion material less than the 3rd TEC of the 2nd TEC (83,83 "; 65,65 ', 65 ") fill (118,129) groove (74,74 ', 74 "), wherein, dielectric (78,78 ', 78 ") and the floating inclusion material of electricity (83,83 "; 65,65 ', being combined in of 65 ") wherein form the composite dielectrics zone that is suitable for support engages pad (35) (62,62 ', 62 "); Near the composite dielectrics zone (62,62 ', form (123,126,131) active devices (24) in the active device area (46) of 62 "), wherein, active device (24) has the first terminal (28); With the inclusion material (83,83 "; 65,65 ', 65 ") electricity isolator dielectric (78,78 ', 78 ") and inclusion material (83,83 "; 65,65 ', 65 ") top goes up in dielectric area (62,62 ', 62 ") and forms (123,126,131) joint sheets (35); And the first terminal (28) that joint sheet (35) is electrically coupled to active device.According to another embodiment, the inclusion material (82,82 "; 83,83 "; 65,65 ', 65 ") comprise silicon or germanium or its combination.According to another embodiment, first material comprises silicon or germanium or its combination.According to another embodiment, the inclusion material (82,82 "; 83,83 "; 65,65 ', 65 ") have following shape in plane graph, this shape comprises the X-Y shape array of the row (65-4,65-5) of one or more parallel continuously basically a plurality of row (65-1,65-2) or a plurality of substantially parallel row (65-3) that interrupts or a plurality of " L " or " T " shape or a plurality of row (65-5) or concentric rectangles, concentric circles or polygon (65-6,65-7,65-8) with one heart.
According to the 3rd embodiment, provide a kind of electronic device (44,44 ', 44 "), be included in the Semiconductor substrate (45) that wherein has joint sheet zone (60) and active device area (46); Joint sheet (35) with the isolation of substrate (45) electricity; In the joint sheet zone (60) on substrate (45) and the composite dielectrics zone below joint sheet (35) (62,62 ', 62 "); wherein; the composite dielectrics zone (62,62 ', 62 ") comprise the insulation dielectric zone (78,78 ', 78 ", 85,68,70,86) and non-single crystal semiconductor inclusion zone (65,65 ', 65 "), the inclusion zone (65,65 ', 65 ") by the insulation dielectric zone (78,78 ', 78 ", 85,68,70,86) a part and joint sheet (35) and the electric isolation of substrate (45); And by interconnection (41,41 ', 41 ") are electrically coupled to the active device (24) in the active device area (46) of joint sheet (35).According to another embodiment, substrate (45) has the resistivity less than about 0.1Ohm-cm.According to another embodiment, separate with active device area (46) by the coupling regime (38) that is less than or equal to about 20 microns length (39) joint sheet zone (60).According to another embodiment, the inclusion zone (65,65 ', comprise a plurality of substantially parallel row (65-2) in the plane graph of the semi-conducting material (82) that on the direction of pointing to active device area (46), is orientated of 65 ").
Though in aforementioned detailed description of the present invention, proposed at least one exemplary embodiment, will be appreciated that to have many modifications.It is also recognized that exemplary embodiment only is an example, and and be not intended to by any way limit the scope of the invention, applicability or structure.On the contrary, aforementioned detailed description will be provided for realizing the route map that makes things convenient for of exemplary embodiment of the present invention for those skilled in the art, should be appreciated that under the situation of the scope of in not breaking away from appended claims and legal equivalents thereof, setting forth of the present invention the function and the layout of the element described are in the exemplary embodiment carried out various modifications.

Claims (20)

1. electronic component comprises:
Semiconductor (SC) substrate, described semiconductor (SC) substrate has first thermal coefficient of expansion (TEC) and active device area and joint sheet zone;
Joint sheet, described joint sheet are arranged in described joint sheet zone;
Composite dielectrics zone, described composite dielectrics zone below described joint sheet, and comprise the insulating material with the 2nd TEC at described joint sheet zone meta;
The inclusion of another material in the described composite dielectrics zone, described another material has the 3rd TEC less than described the 2nd TEC, and wherein, described inclusion and described substrate and described joint sheet electricity are isolated; And
Active device is arranged in described active device area and near described composite dielectrics zone, has the first terminal that is electrically coupled to described joint sheet by interconnection.
2. electronic component according to claim 1, wherein, described substrate comprises silicon or germanium or its combination, and described inclusion comprises the on-monocrystalline form of silicon or germanium or its combination.
3. electronic component according to claim 1, wherein, described inclusion has the width in about 0.2 to 5.0 micrometer range.
4. electronic component according to claim 3, wherein, described inclusion have width with and about 13～16 times center line of width to centreline spacing.
5. electronic component according to claim 1, wherein, described inclusion has the aspect ratio in about 2 to 200 scopes.
6. electronic component according to claim 5, wherein, described inclusion has the aspect ratio in about 15 to 50 scopes.
7. electronic component according to claim 6, wherein, described inclusion has the aspect ratio in about 20 to 30 scopes.
8. electronic component according to claim 1, wherein, described inclusion comprises a plurality of substantially parallel foliaceous shapes in plane graph.
9. electronic component according to claim 8, wherein, described inclusion has the long size that is orientated towards described active device in plane graph.
10. electronic component according to claim 8, wherein, described inclusion has the long size that is not orientated towards described active device in plane graph.
11. electronic component according to claim 1, wherein, described inclusion forms substantially concentric shape in plane graph.
12. electronic component according to claim 1, wherein, described composite dielectrics zone is positioned at about 20 microns or littler of described active device area.
13. a method that is used to form electronic component, described electronic component is incorporated composite dielectrics zone (CDR) into below being coupled to the joint sheet of active device, and described method comprises:
The Semiconductor substrate that has first thermal coefficient of expansion (TEC) and have first material of first surface is provided, and wherein, described substrate has the second area that is applicable to the first area of admitting described active device and is applicable to the described joint sheet of admittance therein;
Form mask on described second area, described mask has the isolated opening of first width;
Basically the isolated groove of described first width is etched to first degree of depth in described substrate, stays basically the not cylinder of moving backing material between the other parts of the backing material below described groove and described groove;
In described groove, form dielectric with the 2nd TEC, make in described dielectric, exist from described first surface extend to the described groove and do not extend in the other parts of the described backing material below the described groove basically in the space of centralized positioning;
Use that floating and inclusion material that have less than the 3rd TEC of described the 2nd TEC comes filling groove with respect to described substrate electricity, wherein, being combined in of the floating inclusion material of described dielectric and described electricity wherein forms the described composite dielectrics zone that is applicable to the described joint sheet of support;
Forming active device near in the active device area in described composite dielectrics zone, wherein, described active device has the first terminal;
On described composite dielectrics zone, forming described joint sheet above described dielectric and the inclusion material isolator with described inclusion material electricity; And
Described joint sheet is electrically coupled to the described the first terminal of described active device.
14. method according to claim 13, wherein, described inclusion material comprises silicon or germanium or its combination.
15. method according to claim 14, wherein, described first material comprises silicon or germanium or its combination.
16. method according to claim 13, wherein, described inclusion material has plan view shape, and described plan view shape comprises the one or more parallel continuously basically a plurality of row or a plurality of substantially parallel row or the row of a plurality of " L " or " T " shape or X-Y shape array or concentric rectangles, concentric circles or the concentric polygon of a plurality of row of interruption.
17. an electronic device comprises:
Semiconductor substrate, described Semiconductor substrate has joint sheet zone and active device area therein;
Joint sheet, described joint sheet and described substrate electricity are isolated;
The composite dielectrics zone, in the described joint sheet zone of described composite dielectrics zone on described substrate and below described joint sheet, wherein, described composite dielectrics zone comprises insulation dielectric zone and non-single crystal semiconductor inclusion zone, and described inclusion zone isolates with described joint sheet and described substrate electricity by a plurality of parts in described insulation dielectric zone; And
Active device in the described active device area is electrically coupled to described joint sheet by interconnection.
18. device according to claim 17, wherein, described substrate has the resistivity less than about 0.1Ohm-cm.
19. device according to claim 18, wherein, described joint sheet zone is less than or equal to about 20 microns coupling regime by length and separates with described active device area.
20. device according to claim 18, wherein, described inclusion zone is included in a plurality of substantially parallel row in the plane graph of the semi-conducting material that is orientated on the direction of pointing to described active device area.
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US7998852B2 (en) 2011-08-16

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