CN102231607B - Micropower consumption direct-current inverter - Google Patents
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Abstract
The invention discloses a micropower consumption direct-current inverter which realizes the inversion of a direct-current voltage through a simple capacitance network. The biggest characteristic of the direct-current inverter is as follows: all of output powers can be obtained only through the power conversion of a small part of an input power, namely, a big part of the input power can reach an output end to become an output power instead of being carried out actual power conversion and transmitted via a magnetic core transformer or an inductor. All devices work at a working frequency and do not produce EMI (Electro-Magnetic Interference), therefore, the invention has very small power consumption and long service life and is safe and reliable, energy-saving and environment-friendly, low in cost and easy for fabrication and assembly.
Description
Technical field
The present invention relates to a kind of little power consumption direct-flow inverter.
Background technology
The tradition direct-flow inverter adopts the method for PWM pulse-width modulation, circuit topography has bridge-type, semibridge system, push-pull type, positive activation type, inverse-excitation type etc., its method of work is, at first without forethought, a kind of direct voltage of input is all become the high-frequency square wave to be said again, use inductance, capacitor filtering then, become alternating voltage, this method has following defect:
1) method of employing pulse-width modulation, the production process of high-frequency, high-power square wave, just strong EMI disturbs the process that produces, and the high power DC inverter is equivalent to a high frequency power transmitting station, can infer, and the interference that produces is what serious.
2) in the power conversion process, the whole of input power must carry out actual power conversion, and the power of all conversion must could arrive output by core transformers or inductance transmission, and loss is big, and efficient is low.
Summary of the invention
Little power consumption direct-flow inverter principle
Fig. 1 is little power consumption direct-flow inverter operation principle schematic diagram, and the course of work is as follows:
1) sinusoidal wave preceding 10ms area is along Y-axis N five equilibrium, and this sentences 4 and is divided into example;
2) every five equilibrium serves as to make 4 rectangles on one side to go to the bottom, and heap tires out into turriform as shown;
3) utilize capacitance network to produce the pagoda ripple by input direct voltage, this is the first step of implementing dc inversion;
4) cut this turriform internally with sine wave, sinusoidal wave amplitude selection principle is to make sinusoidal wave just tangent with the right-angle side of pagoda ripple in inside;
5) the pagoda ripple is cut the entity after the unnecessary part, is the sine voltage Va of output just;
6) the unnecessary part that scales off of pagoda ripple is broken up, is integrated, and is transformed into sine voltage Vb, exports simultaneously with aforementioned Va, produces the preceding 10ms waveform of output voltage V o;
7) sine wave back 10ms processing method is the same, produces the back 10ms waveform of output voltage V o.
Little power consumption direct-flow inverter is made up of a voltage cutting circuit and a N rank capacitance network, the input of the output termination voltage cutting circuit of N rank capacitance network.The voltage cutting circuit is made up of field effect transistor Q9, Q12, their source electrode is connected together, by resistance R 1 ground connection, capacitor C 8 and resistance R 1 parallel connection, the drain electrode of field effect transistor Q9 connects the positive pole of capacitance network, the drain electrode of field effect transistor Q12 connects the negative pole of capacitance network, and the driving signal V12 of field effect transistor Q9, Q12 is the sine wave signal of amplitude 310V.N rank capacitance network is by just, negative both arms are formed, the positive arm of capacitance network is by capacitor C 1, C3, C5, C7 and field effect transistor Q2, Q6, Q8, Q11 forms, the positive pole of capacitor C 1 connects the source electrode of field effect transistor Q2, the drain electrode of field effect transistor Q2 connects the negative electrode of diode D1, the positive pole of capacitor C 3 connects the source electrode of field effect transistor Q6, the drain electrode of field effect transistor Q6 connects the anode of diode D3 and the negative pole of capacitor C 1, the positive pole of capacitor C 5 connects the source electrode of field effect transistor Q8, the drain electrode of field effect transistor Q8 connects the anode of diode D5 and the negative pole of capacitor C 3, the positive pole of capacitor C 7 connects the source electrode of field effect transistor Q11, the drain electrode of field effect transistor Q11 connects the anode of diode D7 and the negative pole of capacitor C 5, the minus earth of capacitor C 7, diode D1, D3, the negative electrode of D5 connects the positive pole of capacitance network simultaneously, i.e. the drain electrode of field effect pipe Q9;
The negative arm of capacitance network is by capacitor C 2, C4, C6, C9 and field effect transistor Q1, Q5, Q7, Q10 forms, the negative pole of capacitor C 2 connects the source electrode of field effect transistor Q1, the drain electrode of field effect transistor Q1 connects the anode of diode D2, the negative pole of capacitor C 4 connects the source electrode of field effect transistor Q5, the drain electrode of field effect transistor Q5 connects the negative electrode of diode D4 and the positive pole of capacitor C 2, the negative pole of capacitor C 6 connects the source electrode of field effect transistor Q7, the drain electrode of field effect transistor Q7 connects the negative electrode of diode D6 and the positive pole of capacitor C 4, the negative pole of capacitor C 9 connects the source electrode of field effect transistor Q10, the drain electrode of field effect transistor Q10 connects the negative electrode of diode D8 and the positive pole of capacitor C 6, the plus earth of capacitor C 9, diode D2, D4, the anode of D6 connects the negative pole of capacitance network simultaneously, i.e. the drain electrode of field effect pipe Q12;
Its positive pole of minus earth of input positive direct-current voltages V7 connects the drain electrode of field effect transistor Q4, the source electrode of field effect transistor Q4 connects the drain electrode of field effect transistor Q9, the plus earth of input negative dc voltage V8, its negative pole connects the drain electrode of field effect transistor Q3, and the source electrode of field effect transistor Q3 connects the drain electrode of field effect transistor Q12;
Gate drive signal V1, V3 are the civil power synchronous square-wave signals, positive arm driving signal V13, V10, V6, V4 and negative arm driving signal V11, V9, V5, V2 also are the civil power synchronous square-wave signals, but pulsewidth is successively decreased with every 2ms, time-delay increases progressively with every 1ms, and the driving signal V12 of field effect transistor Q9, Q12 is the sine wave signal of amplitude 310V.
Description of drawings
Fig. 1 is pagoda ripple incision principle;
Fig. 2 is the pagoda wave generation circuit;
The simulation waveform of Fig. 3 pagoda ripple
Fig. 4 is the voltage cutting circuit;
The process simulation of the sinusoidal wave cutting of Fig. 5 pagoda ripple;
Fig. 6 is the sine voltage that the pagoda ripple is cut into;
Fig. 7 is the voltage compensating circuit of introducing the UC1825 control chip;
Fig. 8 is that the emulation of introducing UC1825 control chip bucking voltage there is not shape;
Fig. 9 is quadravalence pagoda wave generation circuit;
Figure 10 is 16 rank pagoda ripple drive signal generation circuits;
Figure 11 is that 16 rank pagoda ripples drive the signal simulation waveform;
Figure 12 is eight rank pagoda ripple simulation waveforms;
Figure 13 is the emulation of sinusoidal wave cutting pagoda wave process;
Figure 14 is 16 rank pagoda ripple simulation waveforms;
Figure 15 is quadravalence pagoda wave generation circuit;
Figure 16 is eight rank pagoda wave generation circuits;
Figure 17 is eight rank pagoda wave generation circuits (A);
Figure 18 is eight rank pagoda wave generation circuits (B);
Figure 19 is 16 rank pagoda wave generation circuits;
Figure 20 is 16 rank pagoda wave generation circuits (A);
Figure 21 is 16 rank pagoda wave generation circuits (B);
Figure 22 is 16 rank pagoda wave generation circuits (C);
Fig. 2 is 4 rank pagoda wave generation circuits, the pagoda wave generation circuit is actually a capacitance boost network, this simplified illustration, represent voltage on the network capacitance with power supply V3, V5, V7, V9, V11, V13, V15, V17, among Fig. 2, metal-oxide-semiconductor Q4, Q6, Q8, Q10 etc. form the positive arm of 4 rank capacitance networks, and metal-oxide-semiconductor Q2, Q5, Q7, Q9 etc. form the negative arm of 4 rank capacitance networks, wherein Q6, Q5, V7, V9, D3, D4 have formed the single order of capacitance network, and exponent number increases progressively from top to bottom.
Preceding 10ms, the positive arm of capacitance network starts, each rank metal-oxide-semiconductor gate drive signal ON time increases with exponent number and successively decreases by each 2ms, each rank metal-oxide-semiconductor gate drive signal delay time increases progressively by each 1ms, the ON time of the driving signal V16 of the first rank metal-oxide-semiconductor Q10 is 10ms, delay time is 0ms, and the rest may be inferred.It is the constant amplitude square voltage of cycle 20ms that Q1, Q3 grid add the driving signal, during the preceding 10ms, and the Q1 saturation conduction.Between the V16 high period (pulsewidth 10ms, time-delay 0ms), Q10 saturation conduction, the voltage on the V15 are the square voltage S1 of V15 by the drain-source utmost point of Q10, the drain-source utmost point of D2, Q1 in load resistance R1 generation duration 10ms, amplitude; (pulsewidth 8ms between the V12 high period, time-delay 1ms), the Q8 saturation conduction, the voltage on the V11 is by the drain-source utmost point of Q8, the drain-source utmost point of D6, Q1, produce duration 8ms at load resistance R1, amplitude is the square voltage S2 of V11, pile up on the S1 about S2 with claiming; Between the V8 high period (pulsewidth 6ms, time-delay 2ms), Q6 saturation conduction, the voltage on the V7 are the square voltage S3 of V7 by the drain-source utmost point of Q6, the drain-source utmost point of D3, Q1 in load resistance R1 generation duration 6ms, amplitude, S3
Left and right symmetrically piles up on the S2; (pulsewidth 4ms between the V4 high period, time-delay 3ms), the Q4 saturation conduction, the voltage on the V3 is by the drain-source utmost point of Q4, the drain-source utmost point of D1, Q1, produce duration 4ms at load resistance R1, amplitude is the square voltage S4 of V3, the S left and right symmetrically piles up on the S3; In the last moment that preceding 10ms arrives, load resistance R1 form S1 down, S4 is at the pagoda wave voltage last, that the duration successively decreases.
During the back 10ms, the negative arm of capacitance network starts, and as a same reason, forms S1 at negative direction pagoda wave voltage last, that S4 successively decreased in following, duration at load resistance R1.The last moment that 20ms arrives has formed a complete pagoda wave voltage in resistance R 1, and Fig. 3 is the simulation waveform of the pagoda wave voltage that produces.
Fig. 4 is the side circuit of sinusoidal wave cutting pagoda ripple, metal-oxide-semiconductor Q5, Q6, TX1 etc. have formed the voltage cutting circuit, being added between the former limit of transformer TX1 and the ground is pagoda wave voltage V1, and Q5, Q6 grid add square wave driving signal V4, the V5 that envelope is the steamed bun ripple, V5 hysteresis V4 half period.The selection principle of V4, V5 amplitude is: make sinusoidal wave V4, V5 just tangent with the inside right-angle side of pagoda ripple V1, preceding 10ms, positive pagoda wave voltage V1 that drain electrode adds is by diode D1, the Q5 drain-source utmost point, be added on the load resistance R3, because source voltage is followed the tracks of grid potential, so form the positive steamed bun wave voltage identical with the envelope of gate waveform in resistance R 3, be equivalent to grid voltage and scale off a positive steamed bun wave voltage identical with the grid voltage envelope shape at drain electrode pagoda wave voltage; As a same reason, back 10ms, grid voltage scales off a negative steamed bun wave voltage identical with the grid voltage envelope shape at drain electrode pagoda wave voltage, after the one-period, has formed a complete sine voltage Voa in resistance R 3.Fig. 5 is the simulation waveform of signal voltage cutting drain electrode pagoda wave voltage real process, and the simulation waveform of Fig. 6 is the sine voltage Voa after load resistance R3 has obtained, cut the unnecessary part of pagoda ripple.
Pagoda wave voltage V1 downcuts sinusoidal wave back residue partly, and its waveform is 8 little right-angled triangles (please refer to Fig. 1), and the hypotenuse of these right-angled triangles all overlaps with time shaft, and leg-of-mutton height is exactly the height on the hypotenuse.These triangular voltage are carried out the power conversion by TX1, select suitable no-load voltage ratio, TX1 pays double-side band square-wave voltage that the limit produces by dynamically whole voltage, becomes positive and negative symmetrical voltage Vob, in parallel with the input direct voltage in the pagoda wave generation circuit, carry out the electric energy feedback.
The sine voltage that the clipper circuit of Fig. 4 produces because of a variety of causes, when its amplitude does not reach specified the requirement, adopt voltage compensating circuit, and this voltage is compensated, and the principle of compensating circuit is as follows.
Fig. 7 is voltage compensating circuit, power MOS pipe Q5, Q6 and core transformers TX1 have formed main circuit, modulation signal OUT_A, the OUT_B of UC1825 control chip output is added to the grid of Q5, Q6 by transformer TX2, and V2 is input sine wave voltage Vi, the source ground of Q6.
Under the control of modulation signal OUT_A, OUT_B, the former limit of TX1 and pair limit all produce envelope and are sinusoidal wave double-side band square-wave voltage, suitably select the no-load voltage ratio of TX1, can make that paying limit square wave amplitude is the bucking voltage that needs.Q1-Q4 is connected into the active rectification circuit, transformer is paid envelope and is added between the common ground of the drain electrode of Q1 and load resistance R9, R10 for sinusoidal wave double-side band square-wave voltage, output voltage one end of active rectification links at Vf point and input voltage V2, and the other end is exported at the Vo point.The amplitude of output voltage V o equals input voltage V2 and active rectification output voltage sum.
Transformer TX1 pays edge joint by the active rectification circuit of being made up of Q1-Q4 [1], the envelope that the TX1 felling can be produced is sine voltage for sinusoidal wave double-side band square-wave voltage rectification, suitably select the no-load voltage ratio of TX1, can make that the sine voltage of active rectification circuit output is the difference Vc (bucking voltage Vc takes out from the source electrode of Q3, Q4) of rated output voltage and input voltage, this voltage and input voltage are with frequency, homophase, synchronous, after input voltage Vi stack, form rated output voltage Vo.
Fig. 8 is the simulation waveform of each point voltage of compensating circuit, is input voltage Vi above, is after TX1 pays bucking voltage Vc that the limit produces by active rectification and adds input voltage Vi below, the output voltage V o of formation.
Embodiment
1, little power consumption direct-flow inverter (4 rank) side circuit
Fig. 9 is little power consumption direct-flow inverter (4 rank) side circuit, C1-C7, C9 totally eight electric capacity have replaced 8 voltage source V 3, V5, V7, V9, V11, V13, V15, the V17 among Fig. 2, positive and negative symmetrical direct voltage V7, the V8 of amplitude 310V charges to the positive and negative arm of capacitance network respectively by Q4, Q3, metal-oxide-semiconductor in each rank conducting successively from right to left on the positive and negative arm then forms the pagoda wave voltage.
Preceding 10ms, metal-oxide-semiconductor Q4 conducting, direct-flow positive voltage V7 is by diode pair network capacitance C1, C3, C5, C7 charging in the body of Q2, Q6, Q8, Q11, back 10ms, metal-oxide-semiconductor Q3 conducting, negative DC voltage V8 is by diode pair network capacitance C2, C4, C6, C9 charging in the body of Q1, Q5, Q7, Q10, after network capacitance is full of voltage, process and Fig. 2 circuit of its discharge and generation pagoda wave voltage are identical, no longer repeat.
The making alive V12 of institute is that amplitude 308V, envelope are sinusoidal wave square wave driving signal between the grid of Q9, Q12 and the ground, constitutes the voltage cutting circuit.When the pagoda wave voltage is added in the drain electrode of Q9, Q12, obtain the standard sine wave voltage in source load resistance R 1, simulation waveform is as shown in Figure 6.
TX1 in Fig. 4 circuit pays double-side band square-wave voltage that the limit produces by dynamically whole voltage, become positive and negative symmetrical voltage Vob, the correct no-load voltage ratio of selecting TX1, regulate the pulsewidth that drives signal V4, V5, can make the output amplitude of Vob equate that with herein positive and negative symmetrical voltage V7, V8 amplitude Vob and V7, V8 provide the voltage of pagoda wave generation circuit simultaneously.
Figure 15 is the side circuit on little power consumption direct-flow inverter (4 rank), also is to form after the circuit of Fig. 9 connects the gate drive signal of field effect transistor.Circuit divides two partly, the left side is the control part, the comparison circuit of being made up of two LM339 (8 comparators) determines to form the conducting machine of the field effect transistor of capacitance network, in order to produce the pagoda wave voltage, the right is the pagoda wave generation circuit, the acquisition of pagoda wave voltage and cutting method, preceding having a detailed description now do not repeated herein.
2, pagoda ripple (16 rank) drive signal generation circuit
Figure 10 is that the little power consumption in 16 rank divides inverter to drive the side circuit of signal, circuit is made up of 4 16 LM339 comparators, reference voltage V2 is direct voltage, 16 resistance series connection backs that resistance is identical are in parallel with V2, the end of oppisite phase of 16 comparators order, be connected on the series resistance successively, the 1st comparator connects 1 resistance, and the 2nd comparator connects 2 resistance, and the rest may be inferred by analogy as Fig. 8.Other has the reference voltage of interchange V1, directly receives the in-phase input end of each comparator after the full-wave rectification, and the amplitude of establishing AC and DC reference voltage V1, V2 simultaneously all is 16V.
Preceding 10ms, when the amplitude that exchanges reference voltage V1 during less than 1V, the in-phase end voltage of neither one comparator is greater than end of oppisite phase voltage, and all comparators are output low level all, when the amplitude of V1 during more than or equal to 1V, the in-phase end voltage of the 1st comparator is greater than its end of oppisite phase voltage, the output high level, when the amplitude of V1 during more than or equal to 2V, the in-phase end voltage of the 2nd comparator is greater than its end of oppisite phase voltage, the output high level, the rest may be inferred by analogy for it.When last, namely the 16th comparator exported after the high level, exchanges reference voltage V1 and will arrive extreme value, and As time goes on, V1 will descend.When the amplitude that exchanges reference voltage V1 drops to less than 16V, the in-phase end voltage of the 16th comparator is less than its end of oppisite phase voltage, its output end voltage produces negative saltus step, voltage is by high step-down, produced the 1st, also be the shortest pulse signal of duration, when the amplitude that exchanges reference voltage V1 drops to less than 15V, the in-phase end voltage of the 15th comparator is less than its end of oppisite phase voltage, its output end voltage produces negative saltus step, voltage is by high step-down, produced the 2nd pulse signal, the rest may be inferred by analogy for it.When the amplitude that exchanges reference voltage V1 drops to less than 1V, the in-phase end voltage of the 1st comparator is less than its end of oppisite phase voltage, its output end voltage produces negative saltus step, voltage is by high step-down, produced the 16th, also be last 1, be the longest pulse signal of duration simultaneously, when second 10ms arrives, repeat the above-mentioned course of work.16 duration pulse drive signals from short to long that produce just form each differential voltage of pagoda voltage, please refer to the simulation waveform of Figure 11.
Obviously, the frequency that exchanges reference voltage V1 has determined the duration of the pulse signal that produces, namely determined the frequency of differential inverter output AC voltage, and the amplitude of reference voltage V1, V2 has determined the height of the pulse signal that produces, namely determined the amplitude of differential inverter output AC voltage, the frequency of V1 and V1, V2 amplitude can be regulated arbitrarily, so frequency and the amplitude of differential inverter output AC voltage also can be regulated arbitrarily.
Figure 12 is little power consumption direct-flow inverter (8 rank) output voltage simulation waveform, and Figure 13 is the simulation waveform of the cutting process of pagoda ripple, can see from figure, when the exponent number N of pagoda ripple increases, N=8 for example, the pagoda ripple that produces approach sinusoidal wave very much, can save this link of voltage cutting.
From the simulation waveform of Figure 12 as can be seen, the leftover pieces that cut down from the pagoda ripple, increase along with exponent number N, the gross area is more and more littler, and this is because the pagoda ripple can be regarded N differential superimposed forming on the longitudinal axis as, when N is tending towards infinite, it is sinusoidal wave that the pagoda ripple is tending towards, at this time, with sinusoidal wave cutting pagoda ripple, the leftover pieces gross area that scales off equals zero.
3, little power consumption direct-flow inverter (8 rank) side circuit
Figure 16 is little power consumption direct-flow inverter (8 rank) side circuit, circuit is divided into A, B two partly, A partly is control circuit, determine the conducting opportunity of main circuit field effect transistor, B partly is the pagoda wave generation circuit, and the exponent number N=8 of capacitance network has here been Duoed four network capacitances than Fig. 2, but the principle of accumulation pagoda ripple is identical, no longer repeats herein.
Figure 17 is the A part of little power consumption direct-flow inverter (8 rank) side circuit, and Figure 18 is the B part of little power consumption direct-flow inverter (8 rank) side circuit.
4, little power consumption direct-flow inverter (16 rank) side circuit
Figure 16 is little power consumption direct-flow inverter (16 rank) side circuit, circuit is divided into A, B, C three partly, A partly is the control circuit on the main circuit left side, determines the conducting opportunity of left noisy circuit field effect transistor, and C partly is the control circuit on main circuit the right, determine the conducting opportunity of the right main circuit field effect transistor, B partly is the pagoda wave generation circuit, and the exponent number N=16 of capacitance network has here been Duoed 12 network capacitances than Fig. 2, but the principle of accumulation pagoda ripple is identical, no longer repeats herein.
Figure 21 is the A part of little power consumption direct-flow inverter (16 rank) side circuit, and Figure 22 is the B part of little power consumption direct-flow inverter (16 rank) side circuit, and Figure 23 is the C part of little power consumption direct-flow inverter (16 rank) side circuit.
General many level FBI inverter, for example tri-level inversion, five level inverse conversions, seven level inverse conversions etc., increase the purpose that output-voltage levels is counted N, be in order to reduce the harmonic content in the output voltage waveforms, but power demand device and circuit complexity are shown off index increase, N isolate, voltage source independently must be arranged, and among each FBI the driving signal of power device also be isolation, independently.The three-phase two-level inversion, 6 of power devices, three-phase tri-level inversion, 12 of power devices, three-phase five level inverse conversions, 24 of power devices.If realize 16 level inverse conversions, power demand device P=2
N=2
16=65536, need to isolate, independently drive 65536 of signals, the inverter circuit of this empty talk is can not realize fully actually, can only be to feed on fancies.The textbook of all relevant inverters is all mentioned multi-level inverse conversion, but does not have can the draw side circuit of the above inverter of five level of which textbook, because too complicated, draws also that picture does not come out, and how can actually work it out.
SPWM full bridge inverter (FBI) is not only that power device is shown off the problem that index increases, and what more kill is, when carrying out many level stacks, also will carry out the SPWM pulse-width modulation in each level, the SPWM control of a FBI is enough complicated, now will be to reaching 2
N=65536 SPWM drive signal and control, and the complexity of its space vector is not imaginable.
Little merit direct current consumption inverter power demand device and circuit complexity are shown off linear increasing, i.e. power demand device P=2N, and wherein N is level number.Fig. 4 is the side circuit of the little power consumption direct-flow inverter of 4 level, power demand device P=2N=2*4=8, realize 16 electrical level inverters, power demand device P=2N=2*16=32, Figure 14 is little power consumption direct-flow inverter (16 rank) pagoda wave voltage simulation waveform, curve can be seen among the figure, and the pagoda ripple of N=16 is the convergence sine wave, does not need to carry out voltage cutting at all.
Little merit direct current consumption inverter circuit is simple, realize easily, failure rate is low, and is safe and reliable, and topmost characteristics are, all devices are operated in power frequency, do not produce EMI and disturb, also do not produce high-frequency loss, efficient is up to more than 99%, energy-conserving and environment-protective, cost, volume, weight, power consumption all are 1/10th of conventional inverter.
Claims (1)
1. little power consumption direct-flow inverter, it is characterized in that: little power consumption direct-flow inverter is made up of a voltage cutting circuit and a N rank capacitance network, the input of the output termination voltage cutting circuit of N rank capacitance network:
1) the voltage cutting circuit is made up of field effect transistor Q9, Q12, their source electrode is connected together, by resistance R 1 ground connection, capacitor C 8 and resistance R 1 parallel connection, the drain electrode of field effect transistor Q9 connects the positive pole of capacitance network, the drain electrode of field effect transistor Q12 connects the negative pole of capacitance network, and the driving signal V12 of field effect transistor Q9, Q12 is the sine wave signal of amplitude 310V;
2) N rank capacitance network is made up of positive and negative both arms:
1. the positive arm of capacitance network is by capacitor C 1, C3, C5, C7 and field effect transistor Q2, Q6, Q8, Q11 forms, the positive pole of capacitor C 1 connects the source electrode of field effect transistor Q2, the drain electrode of field effect transistor Q2 connects the anode of diode D1, the positive pole of capacitor C 3 connects the source electrode of field effect transistor Q6, the drain electrode of field effect transistor Q6 connects the anode of diode D3 and the negative pole of capacitor C 1, the positive pole of capacitor C 5 connects the source electrode of field effect transistor Q8, the drain electrode of field effect transistor Q8 connects the anode of diode D5 and the negative pole of capacitor C 3, the positive pole of capacitor C 7 connects the source electrode of field effect transistor Q11, the drain electrode of field effect transistor Q11 connects the anode of diode D7 and the negative pole of capacitor C 5, the minus earth of capacitor C 7, diode D1, D3, the negative electrode of D5 connects the positive pole of capacitance network simultaneously, i.e. the drain electrode of field effect pipe Q9;
2. the negative arm of capacitance network is by capacitor C 2, C4, C6, C9 and field effect transistor Q1, Q5, Q7, Q10 forms, the negative pole of capacitor C 2 connects the source electrode of field effect transistor Q1, the drain electrode of field effect transistor Q1 connects the negative electrode of diode D2, the negative pole of capacitor C 4 connects the source electrode of field effect transistor Q5, the drain electrode of field effect transistor Q5 connects the negative electrode of diode D4 and the positive pole of capacitor C 2, the negative pole of capacitor C 6 connects the source electrode of field effect transistor Q7, the drain electrode of field effect transistor Q7 connects the negative electrode of diode D6 and the positive pole of capacitor C 4, the negative pole of capacitor C 9 connects the source electrode of field effect transistor Q10, the drain electrode of field effect transistor Q10 connects the negative electrode of diode D8 and the positive pole of capacitor C 6, the plus earth of capacitor C 9, diode D2, D4, the anode of D6 connects the negative pole of capacitance network simultaneously, i.e. the drain electrode of field effect pipe Q12;
3. its positive pole of minus earth of importing positive direct-current voltages V7 connects the drain electrode of field effect transistor Q4, the source electrode of field effect transistor Q4 connects the drain electrode of field effect transistor Q9, the plus earth of input negative dc voltage V8, its negative pole connects the drain electrode of field effect transistor Q3, and the source electrode of field effect transistor Q3 connects the drain electrode of field effect transistor Q12;
4. gate drive signal V1, V3 are the civil power synchronous square-wave signals, positive arm driving signal V13, V10, V6, V4 and negative arm driving signal V11, V9, V5, V2 also are the civil power synchronous square-wave signals, but pulsewidth is successively decreased with every 2ms, time-delay increases progressively with every 1ms, and the driving signal V12 of field effect transistor Q9, Q12 is the sine wave signal of amplitude 310V.
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| CN101944853A (en) * | 2010-03-19 | 2011-01-12 | 郁百超 | Green power inverter |
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