CN102226999A - Substrate structure and manufacturing method thereof - Google Patents

Substrate structure and manufacturing method thereof Download PDF

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Publication number
CN102226999A
CN102226999A CN2011101214767A CN201110121476A CN102226999A CN 102226999 A CN102226999 A CN 102226999A CN 2011101214767 A CN2011101214767 A CN 2011101214767A CN 201110121476 A CN201110121476 A CN 201110121476A CN 102226999 A CN102226999 A CN 102226999A
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substrate
layer
interconnection layer
conductor interconnection
cavity
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CN2011101214767A
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CN102226999B (en
Inventor
柳连俊
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MYERSON ELECTRONIC (TIANJIN) CO Ltd
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MYERSON ELECTRONIC (TIANJIN) CO Ltd
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Priority to CN201110121476.7A priority Critical patent/CN102226999B/en
Publication of CN102226999A publication Critical patent/CN102226999A/en
Priority to US14/111,093 priority patent/US9633952B2/en
Priority to PCT/CN2012/071489 priority patent/WO2012152104A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/00182—Arrangements of deformable or non-deformable structures, e.g. membrane and cavity for use in a transducer
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349—Creating layers of material on a substrate
    • B81C1/00365—Creating layers of material on a substrate having low tensile stress between layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019—Bonding or gluing multiple substrate layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention provides a substrate structure, comprising a first substrate and a second substrate in opposite arrangement, wherein a first surface of the first substrate faces to a second surface of the second substrate; the first surface is provided with a conductor interconnection layer and a bonding layer in sequence; and the bonding layer is used for connecting the first substrate and the conductor interconnection layer with the second substrate. According to the substrate structure and the manufacturing method thereof, the second substrate is taken as a substrate with a supporting function; the first substrate is taken as a substrate for manufacturing a device directly; and the first substrate is formed by crystal growth, so the problems of thickness and self-stress are avoided, thus avoiding the unnecessary stress, thereby improving the performances of the devices formed in the first substrate.

Description

Substrat structure and preparation method thereof
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of substrat structure and preparation method thereof.
Background technology
Continuous development along with integrated circuit technique, at MEMS (Micro Electromechanical System, microelectromechanical systems), aspect such as power device and circuit has also obtained using widely, by micro mechanical technology or other technologies are combined with integrated circuit fabrication process, on the substrate of semi-conducting material, make microdevice, microsystem or power device, power circuit etc.
Traditionally, adopt monocrystalline substrate and SOI (Silicon On Insulator, silicon-on-insulator) substrate to carry out the making of device more.
For the SOI substrate, the price of SOI itself is just high, and the manufacture craft of micro mechanical device and circuit is also more complicated than traditional handicraft, can improve the cost of product greatly.For monocrystalline substrate, main passing through forms device by etching behind deposit polycrystalline material on the monocrystalline substrate and other insulating material, but because the defective of polycrystalline material depositing technics and material itself, this makes its deposition thickness be restricted, and also has influence on the performance of device.
Concrete, the problem that above-mentioned monocrystalline substrate forms device is, the polycrystalline material of deposit itself has bigger stress on substrate, this stress can influence the deposition thickness that polysilicon can realize and the performance of device, especially can influence the device of counter stress sensitivity, for example, for MEMS inertial sensor or capacitance pressure transducer,, they are to utilize polysilicon structure to discharge the principle that the back changes electric capacity under the effect of inertia or pressure, when making this transducer, the stress of polysilicon can badly influence the performance of device.
Summary of the invention
The problem that the present invention solves provides a kind of Semiconductor substrate and preparation method thereof, can avoid forming the stress in the device, and then improves the performance of the function element that forms in substrate.
For addressing the above problem, the invention provides a kind of substrat structure, comprising:
First substrate that is oppositely arranged and second substrate;
The first surface of described first substrate is towards the second surface of second substrate, and described first surface is disposed with conductor interconnection layer and bonded layer;
Described bonded layer is connected first substrate and conductor interconnection layer with second substrate.
Alternatively, described first substrate comprises single crystal semiconductor or monocrystalline semiconductor compounds.
Alternatively, described conductor interconnection layer comprises one deck conductive layer at least.
Alternatively, described bonded layer is insulating barrier or conductive layer.
Alternatively, described bonded layer is a conductive layer, and described conductive layer is the function of shielding layer.
Alternatively, described bonded layer is an insulating barrier, and described conductor interconnection layer comprises two conductive layers at least.
Alternatively, also comprise: connect the isolated area of first substrate, a plurality of isolated areas are separated into first substrate in the zone of mutually insulated.
Alternatively, also comprise: be arranged in first cavity described second substrate, that form by second substrate and bonded layer.
Alternatively, also comprise: second cavity between described first surface and described second surface.
Alternatively, also comprise: connect the 3rd cavity that second cavity is formed by first cavity.
Alternatively, the described first substrate lower surface has epitaxial loayer or doped layer, and described epitaxial loayer or doped layer are used to form the partial function layer of device.
Alternatively, also comprise: run through the through hole of drawing of described first substrate, the described through hole outer wall of drawing has dielectric isolation layer, and the described through hole of drawing is used for to dispatch from foreign news agency electricity conductor introduction interconnection layer.
A kind of manufacture method of substrat structure accordingly, also is provided, comprises:
First substrate is provided;
On the first surface of described first substrate, form conductor interconnection layer and bonded layer successively;
Second substrate is provided;
By bonded layer described first substrate and conductor interconnection layer are connected to the second surface of second substrate, so that first substrate and conductor interconnection layer are fixed in second substrate.
Alternatively, the step that forms described conductor interconnection layer comprises: form the conductor interconnection layer that comprises one deck conductive layer at least on described first surface.
Alternatively, described bonded layer is insulating barrier or conductive layer.
Alternatively, described bonded layer is a conductive layer, and described conductive layer is the function of shielding layer.
Alternatively, described bonded layer is an insulating barrier, and the step that forms described conductor interconnection layer is: form the conductor interconnection layer that comprises two conductive layers at least on described first surface.
Alternatively, after connecting second substrate, also comprise step: from first surface facing surfaces attenuate and polish described first substrate.
Alternatively, when first substrate is provided, also comprise: in first substrate, form isolated area from the first surface of first substrate; And after connecting second substrate, also comprise: from first surface facing surfaces attenuate and polish first substrate, expose described isolated area, so that isolated area connects first substrate, a plurality of isolated areas are separated into first substrate in the zone of mutually insulated.
Alternatively, when second substrate is provided, also comprise: in described second substrate, form first opening from the second surface of second substrate; The step that connects second substrate is specially: by bonded layer described first substrate and conductor interconnection layer are connected to second surface, so that first opening and bonded layer form first cavity, and first substrate and conductor interconnection layer are fixed in second substrate.
Alternatively, after forming conductor interconnection layer and bonded layer, also comprise: described bonded layer of etching and conductor interconnection layer form second opening that exposes first surface; The step that connects second substrate is specially: the second surface that first substrate and conductor interconnection layer is connected to second substrate by bonded layer, so that second opening forms second cavity with second surface, and described first substrate and conductor interconnection layer be fixed in second substrate;
Perhaps, the step that connects second substrate is specially: by bonded layer first substrate and conductor interconnection layer are connected to second surface, so that first opening forms first cavity, and second opening forms second cavity, and described first substrate and conductor interconnection layer are fixed in second substrate.
Alternatively, when first substrate is provided, comprising: first substrate is provided, has doped layer or epitaxial loayer on the first surface of described first substrate, be used to form the partial function layer of device.
Alternatively, when first substrate is provided, also comprise: in first substrate, form the through hole of drawing with dielectric isolation layer from first surface; And after connecting second substrate, also comprise: from first surface facing surfaces attenuate and polish first substrate, expose the described through hole of drawing, connect first substrate so that draw through hole, the described through hole of drawing is used for to dispatch from foreign news agency conductor introduction interconnection layer.
Compared with prior art, technique scheme has the following advantages:
Substrat structure that the embodiment of the invention provides and preparation method thereof comprises two substrates, first substrate and conductor interconnection layer integrate by the connection of bonded layer bonding with second substrate, like this, second substrate can be used as the substrate of support function, first substrate is as the substrate of directly making device, and first substrate is to form by crystal growth, does not have the problem of thickness and the stress of self, avoid unnecessary stress, and then improved the performance of the device that in first substrate, forms.
In addition, in the described conductor interconnection layer or bonded layer can have function of shielding, when this substrat structure is used for having the device of special requirement to make to the signal of telecommunication, in the time of as conductive layer and/or bonded layer, also be used to shield the unwanted signal of telecommunication.
In addition, can also comprise isolated area in first substrate, a plurality of isolated areas are separated into the zone of a plurality of mutually insulateds with first substrate, make first substrate isolated electrically, and substrat structure mechanically are still connection.
In addition, can also have in second substrate between first cavity and/or first substrate and second substrate second cavity can also be arranged, described first cavity can be used as the part of device, also can be the alignment patterns on second substrate, the combination of described second cavity or first and second cavity can be used for device or the structure that follow-up formation needs cavity, for example is used for the reference pressure chamber of pressure sensor.
In addition, can also have the through hole of drawing in first substrate, the described through hole of drawing is used for to dispatch from foreign news agency conductor introduction interconnection layer, the conductor interconnection layer that is equivalent to be embedded under first substrate is drawn out on first substrate, and then be convenient to carry out subsequent device and be electrically connected, simplify follow-up manufacturing process on the one hand, saved the area of follow-up integrated device on the other hand.
Description of drawings
Shown in accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1,2 is the structural representation of substrat structure among the embodiment one;
Fig. 3 is the flow chart of the manufacture method of substrat structure among the embodiment one;
Fig. 4-Fig. 6 is the structural representation of each fabrication stage of the substrat structure among the embodiment one;
Fig. 7, Fig. 8 are the structural representation of substrat structure among the embodiment two;
Fig. 9, Figure 10 are the structural representation of substrat structure among the embodiment three;
Figure 11, Figure 12 are the structural representation of substrat structure among the embodiment four.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
A lot of details have been set forth in the following description so that fully understand the present invention, but the present invention can also adopt other to be different from alternate manner described here and implement, those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public specific embodiment.
Secondly, the present invention is described in detail in conjunction with schematic diagram, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
For fear of the stress that is used to form in the device process, the invention provides a kind of substrat structure, with reference to figure 2, described structure comprises:
First substrate 100 that is oppositely arranged and second substrate 200;
The first surface 100-1 of described first substrate 100 is towards the second surface 200-1 of second substrate 200, and described first surface 100-1 is disposed with conductor interconnection layer 110 and bonded layer 130;
Described bonded layer 130 is connected first substrate 100 and conductor interconnection layer 110 with second substrate 200.
In the present invention, described conductor interconnection layer 110 comprises one deck conductive layer 110a at least, and described conductive layer can be one deck or laminated construction.
In the present invention, described conductor interconnection layer 110 can also comprise conductive through hole 110b, can realize being electrically connected by conductive through hole 110b between the conductive layer 110a and/or between same first substrate 110 of conductive layer 110a, described conductive layer 110a, conductive through hole 110b can be semi-conducting material or other suitable electric conducting materials, for example Al, Cu, AlSi, Ti, W or the polysilicon etc. of metal or doping.
In the present invention, described conductor interconnection layer 110 can be arranged in dielectric layer 120 between conductor.
In the present invention, described bonded layer 130 is insulating barrier or conductive layer, has the bonding linkage function, described bonded layer is used for first substrate is connected with second substrate with conductor interconnection layer, can be polysilicon, poly-SiGe (SiGe), aluminium (Al), copper (Cu), silica, silicon oxynitride or amorphous silicon or other suitable materials.
In the present invention, described first substrate 100 can be single crystal semiconductor or monocrystalline semiconductor compounds or other suitable materials, for example monocrystalline silicon, monocrystalline germanium, monocrystalline germanium silicon or other monocrystal materials, preferably, first substrate can be monocrystalline silicon, can be used for further forming required device or circuit thereon; Described second substrate 200 can be monocrystalline, polycrystalline or amorphous semiconductor material or other suitable materials, for example monocrystalline silicon, polysilicon, quartz, glass etc., described second substrate 200 can also be the lamination that is formed by different materials, and for example the surface has the monocrystalline of oxide layer or other materials layer or the lamination of polysilicon.Can be used for mechanical support or other effects.For the material and the application of described first substrate, second substrate, be example only herein, the present invention is not limited to this.
The present invention connects first substrate and conductor interconnection layer and second substrate by bonded layer and forms substrat structure, like this, second substrate can be used as the substrate of support function, first substrate is as the substrate of directly making device, and first substrate is to form by crystal growth, do not have the problem of thickness and self stress, avoided unnecessary stress in the substrate, and then improve the performance of the device that on first substrate, forms.
Based on above-mentioned thought, below will be described in detail specific embodiment.
Embodiment one
With reference to figure 1, Fig. 2, for bonded layer in the present embodiment is respectively the embodiment of the substrat structure of insulating barrier and conductive layer, as shown in the figure, this substrat structure comprises:
First substrate 100 that is oppositely arranged and second substrate 200;
The first surface 100-1 of described first substrate 100 is towards the second surface 200-1 of second substrate 200, and described first surface 100-1 is disposed with conductor interconnection layer 110 and bonded layer 130;
Described bonded layer 130 is connected first substrate 100 and conductor interconnection layer 110 with second substrate 200.
Wherein, as shown in Figure 1, described bonded layer 130 can be insulating barrier, can be non-conducting material, for example silica, silicon oxynitride or unadulterated amorphous silicon or other suitable materials.At bonded layer 130 is among the embodiment of insulating barrier, described conductor interconnection layer 110 comprises one deck conductive layer 110a at least, can be used as electrode or electrical wiring, preferably, when being used for having the device of special requirement to make to the signal of telecommunication, described conductor interconnection layer 110 can comprise two conductive layers 110a at least, ground floor conductive layer (near the conductive layer of first substrate) can be used as electrode or electrical wiring, second layer conductive layer (near the conductive layer of second substrate) can be used as the function of shielding layer, shield the unwanted signal of telecommunication, described bonded layer 130 is used for first substrate 100 and conductor interconnection layer 110 fixedly connected with second substrate 200.
Wherein, as shown in Figure 2, described bonded layer 130 can be conductive layer, at bonded layer 130 is among the embodiment of conductive layer, described conductor interconnection layer 110 comprises one deck conductive layer 110a at least, be electrically connected with conductive layer 110a by conductive through hole 110b, the bonded layer 130 of this conductive layer has the function that conducting function and bonding connect first substrate 100 and second substrate.Described bonded layer 130 can be semi-conducting material, metal material or other the suitable electric conducting materials that mixes, for example polysilicon, poly-SiGe, amorphous silicon, aluminium (Al) or copper (Cu) or other suitable materials.Preferably, when this substrat structure was used for having the device of special requirement to make to the signal of telecommunication, the bonded layer 130 of described conductive layer can also be the function of shielding layer, when having conducting function and key function, shields the unwanted signal of telecommunication.
In the present embodiment, described conductor interconnection layer 110 is formed between conductor in the dielectric layer 120.
In the present embodiment, described conductive layer 110a also comprises conductive through hole 110b, realize being electrically connected by conductive through hole 110b between the conductive layer 110a and/or between same first substrate 110 of conductive layer 110a, described conductive layer 110a, conductive through hole 110b can be semi-conducting material or other suitable electric conducting materials, for example Al, Cu, AlSi, Ti, W or the polysilicon etc. of metal or doping.
In the present embodiment, described first substrate 100 is a monocrystalline silicon, described second substrate 200 is monocrystalline or polysilicon, in other embodiments, described first substrate can also be other single crystal semiconductors, monocrystalline semiconductor compounds or other suitable materials, can be used for further forming required device or circuit thereon; In other embodiments, described second substrate can also be other monocrystalline or polycrystalline or amorphous semiconductor material or other suitable materials, for example monocrystalline silicon, glass, quartz etc., can be used for mechanical support or other effects, described second substrate 200 can also be the lamination that is formed by different materials, and for example the surface has the layer that falls of the monocrystalline of oxide layer or other materials layer or polysilicon.Be example only, the present invention is not limited to this herein.
Among this embodiment, first substrate 100 that will have conductor interconnection layer 110 by the bonded layer 130 for insulating barrier or conductive layer couples together with second substrate 200, second substrate can be used as the substrate of support function, first substrate is as the substrate of directly making device, and first substrate is to form by crystal growth, do not have the problem of thickness and self stress, avoided unnecessary stress, and then improve the performance of the device that in first substrate, forms.In addition, in a preferred embodiment, described conductor interconnection layer or bonded layer have function of shielding, are used to shield the unwanted signal of telecommunication.
Describe the manufacture method of above-mentioned substrat structure in detail below in conjunction with accompanying drawing.Fig. 3 is the flow chart of the manufacture method of substrat structure described in the embodiment of the invention, and Fig. 4 to Fig. 6 is the schematic diagram of the manufacture method of described substrat structure.As shown in the figure, described manufacture method comprises:
At step S11, provide first substrate 100.
With reference to figure 4, described first substrate 100 have first surface 100-1 and with first surface 100-1 facing surfaces 100-2.In the present embodiment, described first substrate is a monocrystalline substrate, and in other embodiments, first substrate can also be other single crystal semiconductors, monocrystalline semiconductor compounds or other suitable materials.
At step S12,, on the first surface 100-1 of described first substrate 100, form conductor interconnection layer 110 and bonded layer 130 successively with reference to figure 4.
Particularly, can be by traditional interconnection process or dual damascene interconnection process, form between conductor dielectric layer 120 on the described first surface 100-1 and between conductor, forming conductor interconnection layer 110 in the dielectric layer 120, described conductor interconnection layer 110 comprises one deck conductive layer 110a at least, also comprise conductive through hole 110b, can realize being electrically connected by conductive through hole 110b between the conductive layer 110a and/or between same first substrate 110 of conductive layer 110a.
Then, on conductor interconnection layer 110, form bonded layer 130.
At bonded layer 130 is among the embodiment of polysilicon layer, can form the bonded layer 130 that is electrically connected with conductor interconnection layer 110 by above-mentioned interconnection process, preferably, this bonded layer 130 has function of shielding, be the function of shielding layer, for example polysilicon, poly-SiGe, amorphous silicon, aluminium (Al), copper (Cu) etc.
At bonded layer 130 is among the embodiment of insulating barrier, can on conductor interconnection layer 110, form the bonded layer of dielectric material, for example silica, silicon oxynitride, amorphous silicon etc. by the method for deposit and planarization, preferably, described conductor interconnection layer 110 comprises two conductive layers 110a at least.
Wherein, described conductor interconnection layer 110, conductive layer 110a and conductive through hole 110b can be semi-conducting material or other suitable electric conducting materials, for example Al, Cu, the polysilicon etc. of metal or doping.
At step S13, provide second substrate 200.
With reference to figure 5, described second substrate 200 have second surface 200-1 and with its facing surfaces.In the present embodiment, described second substrate 200 is monocrystalline or polysilicon, in other embodiments, described second substrate can also be other monocrystalline or polycrystalline or amorphous semiconductor material or other suitable materials, for example glass, quartz etc., described second substrate 200 also can be the lamination that is formed by different materials.
At step S14, by bonded layer 130 described first substrate 100 and conductor interconnection layer 110 are connected to the second surface 200-1 of second substrate 200, so that first substrate 100 and conductor interconnection layer 110 are fixed in second substrate 200, with reference to figure 6.
Particularly, second surface 200-1 with the conductor interconnection layer 110 on first substrate 100 and the first surface thereof and the bonded layer 130 and second substrate 200 is oppositely arranged earlier, bonded layer 130 is contacted with second surface 200-1, then, exert pressure from the back side of the one 100 and second substrate 200, make bonded layer 130 repeat bonding with second substrate 200 and be connected, so that first substrate 100 and conductor interconnection layer 110 are fixed in second substrate 200, for example bonded layer is a polysilicon.Be example only, the present invention is not limited to this herein, and described bonding step of connecting is different because of bonded layer 130 materials.
Preferably, after bonding connects second substrate 200, can also further carry out attenuate and polishing from back side 100-2, so that first substrate 100 reaches desired thickness to first substrate.
So far, the substrat structure that present embodiment provides completes, be formed with conductor interconnection layer 110 between first substrate 100 and second substrate 200, can be according to the design needs of device, first substrate and/or second substrate on first substrate and/or second substrate, form device, circuit or other structures, for example make MEMS or power device/circuit etc., owing to can be the substrate that forms by crystal growth, therefore do not have the problem of thickness and self stress, avoided unnecessary stress in the substrate.
More than to substrat structure and the manufacture method thereof that first substrate and conductor interconnection layer and second substrate couple together being described in detail by bonded layer, in addition, on the basis of this substrat structure, can further include other structure, the isolated area in first substrate for example, first cavity in second substrate, second cavity between first substrate and second substrate, doped layer on the first surface of first substrate or epitaxial loayer, draw through hole or their combination in any in first substrate, below will be described in detail these substrat structures according to specific embodiment.
Embodiment two
The aspect that below will be only be different from embodiment one with regard to embodiment two is set forth.The part of Miao Shuing not will be understood that with embodiment one and has adopted identical step, method or technology to carry out, and does not therefore repeat them here.
With reference to figure 7, Fig. 8, for bonded layer among the embodiment two is respectively the embodiment of the substrat structure of insulating barrier and conductive layer, can be on the basis of the substrat structure of embodiment one, further comprise the isolated area that connects first substrate, as shown in the figure, particularly, this substrat structure comprises:
First substrate 100 that is oppositely arranged and second substrate 200;
Connect the isolated area 140 of first substrate 100, a plurality of isolated areas 140 are separated into first substrate 100 in the zone of mutually insulated;
The first surface 100-1 of described first substrate 100 is towards the second surface 200-1 of second substrate 200, and described first surface 100-1 is disposed with conductor interconnection layer 110 and bonded layer 130;
Described bonded layer 130 is connected first substrate 100 and conductor interconnection layer 110 with second substrate 200.
Wherein, a plurality of described isolated areas 140 are separated into first substrate 100 in the zone of a plurality of mutually insulateds.
Compare with embodiment one, difference only is, has further comprised isolated area 140, this isolated area 140 is an insulating material, first substrate 100 is separated into the zone of a plurality of mutually insulateds, make first substrate isolated electrically, and substrat structure mechanically is still connection.Repeat no more with embodiment one identical part.
For the manufacture method of embodiment two,, specifically may further comprise the steps with reference to figure 7-8:
S21 provides first substrate 100, forms isolated area 140 from the first surface 100-1 of first substrate 100 in first substrate.
Can be by forming the traditional handicraft of isolating in the semiconductor technology, from first surface 100-1 etching opening in first substrate, then by deposition insulating material and carry out planarization and form isolated area 140 (scheming not shown), the degree of depth of described isolated area 140 can be determined according to the thickness of first substrate 100 in the substrat structure of final formation, the thickness of first substrate 100 in the final structure can be equal to or greater than.
S22 forms conductor interconnection layer 110 and bonded layer 130 successively on the first surface 100-1 of described first substrate 100.
At step S23, provide second substrate 200.
At step S24, by bonded layer 130 described first substrate 100 and conductor interconnection layer 110 are connected to the second surface 200-1 of second substrate 200, so that first substrate 100 and conductor interconnection layer 110 are fixed in second substrate 200.
At step S25,, expose described isolated area 140 from first surface 100-1 facing surfaces 100-2 attenuate and polish first substrate 100.Thereby form the isolated area 140 that connects first substrate, a plurality of isolated areas 140 are separated into first substrate 100 in the zone of mutually insulated.
Manufacture method with embodiment one is compared, and difference only is step S21 and step S25, and same section repeats no more.By forming isolated area 140, first substrate 100 is separated into the zone of mutually insulated, and then can in subsequent device is made, makes required device in the area of mutually insulated.
Embodiment three
The aspect that below will be only be different from embodiment one with regard to embodiment three is set forth.The part of Miao Shuing not will be understood that with embodiment one and has adopted identical step, method or technology to carry out, and does not therefore repeat them here.
Fig. 9, Figure 10 are respectively the embodiment of the substrat structure of insulating barrier and conductive layer for bonded layer among the embodiment three, can be on the basis of the substrat structure of embodiment one or embodiment two, further comprise first cavity 150 in second substrate or second cavity 152 between first surface 100-1 and the second surface 200-1, perhaps further comprise the combination of first cavity 150 and second cavity 152.
As shown in Figure 9, particularly, in certain embodiments, described substrat structure comprises:
First substrate 100 that is oppositely arranged and second substrate 200;
The first surface 100-1 of described first substrate 100 is towards the second surface 200-1 of second substrate 200, and described first surface 100-1 is disposed with conductor interconnection layer 110 and bonded layer 130;
Be arranged in first cavity 150 described second substrate 200, that form by second substrate 200 and bonded layer 130;
Described bonded layer 130 is connected first substrate 100 and conductor interconnection layer 110 with second substrate 200.
Wherein, described first cavity can be used as the part of device, for example the reference pressure chamber of pressure sensor; Also can be used as the alignment patterns on second substrate, in the time of can being used for bonded layer and connecting first substrate and second substrate, second substrate is with respect to the align structures of first substrate.
As shown in figure 10, in further embodiments, described substrat structure comprises:
First substrate 100 that is oppositely arranged and second substrate 200;
The first surface 100-1 of described first substrate 100 is towards the second surface 200-1 of second substrate 200, and described first surface 100-1 is disposed with conductor interconnection layer 110 and bonded layer 130;
Second cavity 152 between first surface 100-1 and second surface 200-1;
Described bonded layer 130 is connected first substrate 100 and conductor interconnection layer 110 with second substrate 200.
Wherein, described second cavity can be used for device or the structure that follow-up formation needs cavity, for example is used for the reference pressure chamber of pressure sensor, or other purposes.Be example only, the present invention is not limited to this herein.
In addition, (scheme not shown) in other embodiment, described substrate can comprise above-mentioned first cavity and second cavity simultaneously, and particularly, described substrat structure comprises:
First substrate that is oppositely arranged and second substrate;
The first surface of described first substrate is towards the second surface of second substrate, and described first surface is disposed with conductor interconnection layer and bonded layer;
Be arranged in first cavity described second substrate, that form by second substrate and bonded layer, and second cavity between first surface and second surface;
Described bonded layer is connected first substrate and conductor interconnection layer with second substrate.
Further, described first cavity can connect second cavity 152 by first cavity 150 and form the 3rd cavity (scheming not shown) corresponding to second cavity, forms a darker or bigger cavity, the device or the structure that are used for the big cavity of follow-up formation needs, or other functions.
Alternatively, this substrat structure can further include isolated area 140 in first substrate 100 (scheme not shown, with reference to the diagram of the foregoing description).
Compare with embodiment one or embodiment two, difference only is that further comprised first cavity 150 and/or second cavity 152, same section repeats no more.Described first cavity can be used as the part of device, also can be the alignment patterns on second substrate, in the time of can being used for bonded layer and connecting first substrate and second substrate, second substrate is with respect to the align structures of first substrate, the combination of described second cavity or first and second cavity can be used for device or the structure that follow-up formation needs cavity, for example is used for the reference pressure chamber of pressure sensor.
For the manufacture method of embodiment three, to compare with embodiment one or embodiment two, difference is:
In certain embodiments, difference is, the step of second substrate 200 is provided, and particularly, comprises when second substrate is provided: second substrate 200 is provided, and forms first opening from the second surface 200-1 of second substrate 200 in described second substrate 200; And in the step that connects second substrate, comprise: the second surface 200-1 that described first substrate 100 and conductor interconnection layer 110 is connected to second substrate 200 by bonded layer 130, so that first substrate 100 and conductor interconnection layer 110 are fixed in second substrate 200, and make first opening and bonded layer form first cavity 150.
Wherein, according to the needs of designs, when connecting, described first cavity 150 can be in alignment with other structures in the conductor interconnection layer on first substrate or first substrate.
In other embodiment, difference is, forms the step of conductor interconnection layer and bonded layer, particularly, comprising: form conductor interconnection layer 110 and bonded layer 130, then, described bonded layer 130 of etching and conductor interconnection layer 120 form second opening that exposes first surface 110-1; And in the step that connects second substrate, comprise: the second surface 200-1 that described first substrate 100 and conductor interconnection layer 110 is connected to second substrate 200 by bonded layer 130, so that first substrate 100 and conductor interconnection layer 110 are fixed in second substrate 200, and make second opening and second surface 200-1 form second cavity 152.
Wherein, described second cavity can be used for device or the structure that follow-up formation needs cavity, for example is used for the reference pressure chamber of pressure sensor, or other purposes.
In other embodiment, difference is, the step that second substrate is provided and forms conductor interconnection layer and bonded layer, particularly, form the step of conductor interconnection layer and bonded layer, comprising: form conductor interconnection layer 110 and bonded layer 130, then, described bonded layer 130 of etching and conductor interconnection layer 120 form second opening that exposes first surface 110-1; And the step that second substrate is provided, comprising: second substrate 200 is provided, and in described second substrate 200, forms first opening from the second surface 200-1 of second substrate 200; The step that connects second substrate is specially: by bonded layer 130 first substrate 100 and conductor interconnection layer 110 are connected to second surface 200-1, so that first opening forms first cavity 150, and second opening form second cavity 152, and described first substrate and conductor interconnection layer are fixed in second substrate.
Wherein, when connecting, according to the needs of designs, described first cavity 150 can be aimed at conductor interconnection layer 110 on second cavity 152, first substrate or other structures in first substrate 100.
Aim among the embodiment of second cavity at first cavity, first cavity 150 connects second cavity 152, forms the 3rd cavity that first cavity 150 connects second cavity 152, forms a darker or bigger cavity, the device or the structure that are used for the big cavity of follow-up formation needs, or other functions.。
Manufacture method with embodiment one or embodiment two is compared, and difference only is that further formed first cavity 150 and/or second cavity 152, same section repeats no more.Described first cavity can be used as the part of device, also can be used for the align structures that subsequent device is made, the combination of described second cavity or first and second cavity can be used for device or the structure that follow-up formation needs cavity, for example is used for the reference pressure chamber of pressure sensor.
Embodiment four
The aspect that below will be only be different from embodiment one with regard to embodiment four is set forth.The part of Miao Shuing not will be understood that with embodiment one and has adopted identical step, method or technology to carry out, and does not therefore repeat them here.
With reference to Figure 11, Figure 12, for bonded layer among the embodiment four is respectively the embodiment of the substrat structure of insulating barrier and conductive layer, can be on the basis of embodiment one, embodiment two or embodiment three, further comprise doped layer or epitaxial loayer 160, particularly, as shown in the figure, this substrat structure comprises:
First substrate 100 that is oppositely arranged and second substrate 200, the first surface 100-1 of described first substrate 100 has doped layer or epitaxial loayer 160;
The first surface 100-1 of described first substrate 100 is towards the second surface 200-1 of second substrate 200, and described first surface 100-1 is disposed with conductor interconnection layer 110 and bonded layer 130;
Described bonded layer 130 is connected first substrate 100 and conductor interconnection layer 110 with second substrate 200.
Wherein, described doped layer or epitaxial loayer 160 can be used to form the partial function layer of device, and for example form and bury grid or line or other functions, only be example herein.
Perhaps, on the basis of embodiment one, embodiment two or embodiment three, further comprise and draw through hole 170, drawing through hole 170 by this can be drawn out to conductor interconnection layer on the second surface 100-2 of first substrate, the conductor interconnection layer that is equivalent to be embedded under first substrate is drawn out on first substrate, and then be convenient to carry out the subsequent device electrical connection, and simplify follow-up manufacturing process on the one hand, saved the area of follow-up integrated device on the other hand.
Perhaps, in certain embodiments, further, as Figure 11, Figure 12, can also comprise run through described first substrate 110 draw through hole 170.According to the specific design needs, this is drawn through hole 170 and can couple together by doped layer or the epitaxial loayer 160 that described conductor interconnection layer 110 will be used to form part of devices, further this connection is drawn out on the second surface 100-2 of first substrate, and then carries out follow-up electrical connection by drawing through hole.
Above-mentioned through hole 170 outer walls of drawing can have dielectric isolation layer 172.
Above-mentioned conductive through hole 170 can be used for to dispatch from foreign news agency conductor introduction interconnection layer 110, so that conductor interconnection layer 110 further is electrically connected or guides into pressure welding weld pad, perhaps other functions when encapsulating.
In addition, alternatively, substrat structure among this embodiment can further include isolated area 140, first cavity 150 in second substrate or second cavity 152 between first surface and the second surface in first substrate 100, perhaps their combination in any (scheme not shown, with reference to the diagram of the foregoing description).
Compare with embodiment three with embodiment one, embodiment two, the difference of present embodiment is to have doped layer or epitaxial loayer and/or draws through hole, and same section repeats no more.Described doped layer and/or epitaxial loayer can be used to form the partial function layer of device, with in subsequent device is made, form required device, the described through hole of drawing is used for to dispatch from foreign news agency conductor introduction interconnection layer, the conductor interconnection layer that is equivalent to be embedded under first substrate is drawn out on first substrate, and then be convenient to carry out the subsequent device electrical connection, and simplify follow-up manufacturing process on the one hand, saved the area of follow-up integrated device on the other hand.
For the manufacture method of embodiment four, to compare with embodiment one, embodiment two or embodiment three, difference is:
When first substrate is provided, comprising: provide on the first surface 100-1 of first substrate, 100, the first substrates to have doped layer or epitaxial loayer 160, be used to form the partial function layer of device.
Perhaps, when first substrate is provided, also comprise: from first surface 100-1, doped layer or epitaxial loayer 160 in first substrate 100, form have a dielectric isolation layer 172 draw through hole 170; And after connecting second substrate 200, also comprise: from first surface facing surfaces 100-2 attenuate and polish first substrate 100, expose and describedly draw through hole 170, connect first substrate 100 so that draw through hole 170, the described through hole 170 of drawing is used for to dispatch from foreign news agency conductor introduction interconnection layer 110.
Compare with above-mentioned manufacture method, difference only is that further formed doped layer or epitaxial loayer 160 and/or drawn through hole, same section repeats no more.Described doped layer and/or epitaxial loayer 160 can be used to form the partial function layer of device, with in subsequent device is made, form required device, the described through hole 170 of drawing is used for to dispatch from foreign news agency conductor introduction interconnection layer 11, so that conductor interconnection layer 110 further is electrically connected or guides into pressure welding weld pad, perhaps other functions when encapsulating.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Substrat structure provided by the invention has avoided forming the stress in the substrate of device, can further make device, circuit or other structures, especially MEMS and power device and circuit according to the needs of specific design.
Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art, do not breaking away under the technical solution of the present invention scope situation, all can utilize the method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, all still belongs in the scope of technical solution of the present invention protection any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims (23)

1. a substrat structure is characterized in that, comprising:
First substrate that is oppositely arranged and second substrate;
The first surface of described first substrate is towards the second surface of second substrate, and described first surface is disposed with conductor interconnection layer and bonded layer;
Described bonded layer is connected first substrate and conductor interconnection layer with second substrate.
2. substrat structure according to claim 1 is characterized in that, described first substrate comprises single crystal semiconductor or monocrystalline compound semiconductor.
3. substrat structure according to claim 1 is characterized in that described conductor interconnection layer comprises one deck conductive layer at least.
4. substrat structure according to claim 1 is characterized in that, described bonded layer is insulating barrier or conductive layer.
5. according to claim 1 or 3 described substrat structures, it is characterized in that described bonded layer is a conductive layer, described conductive layer is the function of shielding layer.
6. substrat structure according to claim 1 is characterized in that, described bonded layer is an insulating barrier, and described conductor interconnection layer comprises two conductive layers at least.
7. substrat structure according to claim 1 is characterized in that, also comprises: connect the isolated area of first substrate, a plurality of isolated areas are separated into first substrate in the zone of mutually insulated.
8. substrat structure according to claim 1 is characterized in that, also comprises: be arranged in first cavity described second substrate, that be made up of second substrate and bonded layer.
9. according to claim 1 or 8 described substrat structures, it is characterized in that, also comprise: second cavity between described first surface and described second surface.
10. substrat structure according to claim 9 is characterized in that, also comprises: connect the 3rd cavity that second cavity is formed by first cavity.
11. substrat structure according to claim 1 is characterized in that, the described first substrate lower surface has epitaxial loayer or doped layer, and described epitaxial loayer or doped layer are used to form the partial function layer of device.
12. according to claim 1 or 11 described substrat structures, it is characterized in that, also comprise: run through the through hole of drawing of described first substrate, the described through hole outer wall of drawing has dielectric isolation layer, and the described through hole of drawing is used for to dispatch from foreign news agency electricity conductor introduction interconnection layer.
13. the manufacture method of a Semiconductor substrate structure is characterized in that, comprising:
First substrate is provided;
On the first surface of described first substrate, form conductor interconnection layer and bonded layer successively;
Second substrate is provided;
By bonded layer described first substrate and conductor interconnection layer are connected to the second surface of second substrate, so that first substrate and conductor interconnection layer are fixed in second substrate.
14. manufacture method according to claim 13 is characterized in that, the step that forms described conductor interconnection layer comprises: form the conductor interconnection layer that comprises one deck conductive layer at least on described first surface.
15. manufacture method according to claim 13 is characterized in that, described bonded layer is insulating barrier or conductive layer.
16., it is characterized in that described bonded layer is a conductive layer according to claim 13 or 14 described manufacture methods, described conductive layer is the function of shielding layer.
17. manufacture method according to claim 13 is characterized in that, described bonded layer is an insulating barrier, and the step that forms described conductor interconnection layer is: form the conductor interconnection layer that comprises two conductive layers at least on described first surface.
18. manufacture method according to claim 13 is characterized in that, after connecting second substrate, also comprises step: from first surface facing surfaces attenuate and polish described first substrate.
19. manufacture method according to claim 13 is characterized in that, when first substrate is provided, also comprises: in first substrate, form isolated area from the first surface of first substrate; And after connecting second substrate, also comprise: from first surface facing surfaces attenuate and polish first substrate, expose described isolated area, so that isolated area connects first substrate, a plurality of isolated areas are separated into first substrate in the zone of mutually insulated.
20. manufacture method according to claim 13 is characterized in that, when second substrate is provided, also comprises: in described second substrate, form first opening from the second surface of second substrate; The step that connects second substrate is specially: by bonded layer described first substrate and conductor interconnection layer are connected to second surface, so that first opening and bonded layer form first cavity, and first substrate and conductor interconnection layer are fixed in second substrate.
21. according to claim 13 or 20 described manufacture methods, it is characterized in that, after forming conductor interconnection layer and bonded layer, also comprise: described bonded layer of etching and conductor interconnection layer form second opening that exposes first surface;
The step that connects second substrate is specially: the second surface that first substrate and conductor interconnection layer is connected to second substrate by bonded layer, so that second opening forms second cavity with second surface, and described first substrate and conductor interconnection layer be fixed in second substrate;
Perhaps, the step that connects second substrate is specially: by bonded layer first substrate and conductor interconnection layer are connected to second surface, so that first opening forms first cavity, and second opening forms second cavity, and described first substrate and conductor interconnection layer are fixed in second substrate.
22. manufacture method according to claim 13 is characterized in that, when first substrate is provided, comprising: first substrate is provided, has doped layer or epitaxial loayer on the first surface of described first substrate, be used to form the partial function layer of device.
23. according to claim 13 or 22 described manufacture methods, it is characterized in that, when first substrate is provided, also comprise: in first substrate, form the through hole of drawing with dielectric isolation layer from first surface; And after connecting second substrate, also comprise: from first surface facing surfaces attenuate and polish first substrate, expose the described through hole of drawing, connect first substrate so that draw through hole, the described through hole of drawing is used for to dispatch from foreign news agency conductor introduction interconnection layer.
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