CN102222746A - Light emitting device, light emitting device package and illumination system - Google Patents

Light emitting device, light emitting device package and illumination system Download PDF

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Publication number
CN102222746A
CN102222746A CN2011100517404A CN201110051740A CN102222746A CN 102222746 A CN102222746 A CN 102222746A CN 2011100517404 A CN2011100517404 A CN 2011100517404A CN 201110051740 A CN201110051740 A CN 201110051740A CN 102222746 A CN102222746 A CN 102222746A
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semiconductor layer
type semiconductor
electrode
conductive type
layer
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CN102222746B (en
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金省均
林祐湜
范熙荣
罗珉圭
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Suzhou Lekin Semiconductor Co Ltd
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LG Innotek Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21KNON-ELECTRIC LIGHT SOURCES USING LUMINESCENCE; LIGHT SOURCES USING ELECTROCHEMILUMINESCENCE; LIGHT SOURCES USING CHARGES OF COMBUSTIBLE MATERIAL; LIGHT SOURCES USING SEMICONDUCTOR DEVICES AS LIGHT-GENERATING ELEMENTS; LIGHT SOURCES NOT OTHERWISE PROVIDED FOR
    • F21K9/00Light sources using semiconductor devices as light-generating elements, e.g. using light-emitting diodes [LED] or lasers
    • F21K9/20Light sources comprising attachment means
    • F21K9/23Retrofit light sources for lighting devices with a single fitting for each light source, e.g. for substitution of incandescent lamps with bayonet or threaded fittings
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2105/00Planar light sources
    • F21Y2105/10Planar light sources comprising a two-dimensional array of point-like light-generating elements
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2113/00Combination of light sources
    • F21Y2113/10Combination of light sources of different colours
    • F21Y2113/13Combination of light sources of different colours comprising an assembly of point-like light sources
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F21LIGHTING
    • F21YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES F21K, F21L, F21S and F21V, RELATING TO THE FORM OR THE KIND OF THE LIGHT SOURCES OR OF THE COLOUR OF THE LIGHT EMITTED
    • F21Y2115/00Light-generating elements of semiconductor light sources
    • F21Y2115/10Light-emitting diodes [LED]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008Processes
    • H01L2933/0016Processes relating to electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

Abstract

Disclosed are a light emitting device, a light emitting device package, and an illumination system. The light emitting device includes a substrate; a light emitting structure layer including a first conductive type semiconductor layer formed on the substrate and having first and second upper surfaces, in which the second upper surface is closer to the substrate than the first upper surface, an active layer on the first conductive type semiconductor layer, and a second conductive type semiconductor layer on the active layer; a second electrode on the second conductive type semiconductor layer; and at least one first electrode extending at least from the second upper surface of the first conductive type semiconductor layer to a lower surface of the substrate by passing through the substrate.

Description

Luminescent device, luminescent device encapsulation and illuminator
Technical field
The invention provides a kind of luminescent device, luminescent device encapsulation and illuminator.
Background technology
The III-V group-III nitride semiconductor has been widely used in primary raw material such as the luminescent device of light-emitting diode (LED) or laser diode (LD) because of its physics and chemical characteristic.Usually, the III-V group-III nitride semiconductor comprises having In xAl yGa 1-x-yThe semi-conducting material of the composition formula of N (0≤x≤1,0≤y≤1,0≤x+y≤1).
LED converts the electrical signal to infrared ray or light by the characteristic of utilizing compound semiconductor, thus the semiconductor device of transmitting/receiving signal.LED also is used as light source.
Adopt the LED or the LD of nitride semi-conductor material to be mainly used in order to the luminescent device of light to be provided.For example, LED or LD are used as light source and are used to various products, for example, and cellular keypad luminous component, e-mail number plate and illuminating device.
Summary of the invention
Embodiment provides a kind of luminescent device with novel electrode structure.
Embodiment provides a kind of luminescent device with growth substrates and vertical-type electrode structure.
According to embodiment, a kind of luminescent device comprises: substrate; The ray structure layer, it comprises active layer on first conductive type semiconductor layer, first conductive type semiconductor layer and second conductive type semiconductor layer on the active layer, wherein, first conductive type semiconductor layer is formed on the substrate and has first upper surface and second upper surface, wherein, second upper surface is than the more close substrate of first upper surface; Second electrode on second conductive type semiconductor layer; And at least one first electrode, described at least one first electrode is by passing substrate extends to substrate at least from second upper surface of first conductive type semiconductor layer lower surface.
According to embodiment, a kind of luminescent device comprises: substrate, and this substrate comprises transmission material; The ray structure layer, it comprises active layer on the inside of first conductive type semiconductor layer, first conductive type semiconductor layer and second conductive type semiconductor layer on the active layer, wherein, first conductive type semiconductor layer is formed on the substrate and has the outside that forms step from least one side of substrate; Second electrode on second conductive type semiconductor layer; And a plurality of first electrodes, described a plurality of first electrodes are by passing substrate extends to the outside of first conductive type semiconductor layer from the lower surface of substrate side surface.
Description of drawings
Fig. 1 shows the side cutaway view according to the luminescent device of first embodiment;
Fig. 2 is the plane graph of Fig. 1;
Fig. 3 is the upward view of Fig. 1;
Fig. 4 A and Fig. 4 B show the figure of example in the hole of Fig. 1;
Fig. 5 to Figure 10 shows the figure of manufacture process of the luminescent device of Fig. 1;
Figure 11 to Figure 13 shows the figure that forms the example in first electrode and hole according to embodiment in channel region;
Figure 14 shows the side cutaway view according to the luminescent device of second embodiment;
Figure 15 shows the side cutaway view according to the luminescent device of the 3rd embodiment;
Figure 16 and Figure 17 are according to the side cutaway view of the luminescent device of the 4th embodiment and plane graph;
Figure 18 shows the side cutaway view according to the luminescent device of the 5th embodiment;
Figure 19 shows the side cutaway view according to the luminescent device of the 6th embodiment;
Figure 20 shows the side cutaway view according to the luminescent device of the 7th embodiment;
Figure 21 shows the side cutaway view according to the luminescent device of the 8th embodiment;
Figure 22 shows the side cutaway view according to the luminescent device of the 9th embodiment; And
Figure 23 shows the side cutaway view according to the luminescent device of the tenth embodiment;
Figure 24 is the figure that illustrates according to the display device of embodiment;
Figure 25 is the figure that illustrates according to another display device of embodiment; And
Figure 26 is the figure that illustrates according to the illuminating device of embodiment.
Embodiment
In the explanation of embodiment, will be appreciated that, when layer (or film), zone, pattern or structure be called as another substrate, another layer (or film), another zone, another pad or another pattern " on " or during D score, can perhaps also can there be one or more intermediate layer in it " directly " or " indirectly " in another substrate, another layer (or film), another zone or another pad top.Be described with reference to the position of accompanying drawing this kind layer.
Purpose for convenience or clearly, scalable, as to omit or schematically draw each shown in the accompanying drawing layer thickness and size.In addition, each size of component does not reflect actual size.
Fig. 1 shows the side cutaway view according to the luminescent device 100 of first embodiment, and Fig. 2 is the plane graph of Fig. 1.
With reference to Fig. 1, luminescent device 100 comprises: substrate 101, first semiconductor layer 105, first conductive type semiconductor layer 110, active layer 115, second conductive type semiconductor layer 120, second electrode 150 and 152 and first electrode 160.
Luminescent device 100 comprises LED, and LED comprises a plurality of compound semiconductor layers, for example, and a plurality of III-V compound semiconductor elements.Indigo plant, the green or ruddiness of LED in can the visible emitting wave band, the perhaps light in the UV wave band.
Substrate 101 is a growth substrates, and it comprises the insulating material or the electric conducting material of the compound semiconductor that use will be grown.Substrate 101 can be from by Al 2O 3, GaN, SiC, ZnO, Si, GaP, InP, Ga 2O 3Select in the group of forming with GaAs.Hereinafter, will comprise sapphire (Al 2O 3) the insulation growth substrates be described as the example of substrate 101, and substrate 101 can comprise transmissive substrate.Substrate 101 is provided with light extraction structures, as concaveconvex structure or coarse structure.The thickness of substrate 101 can be in 50 μ m to 500 mu m ranges.If substrate 101 comprises transmission material, then can improve the angle of departure of light.
Can be provided with first semiconductor layer 105 on the substrate 101.First semiconductor layer 105 can have based on semi-conductive pattern of II to VI group element compound or layer.First semiconductor layer 105 can comprise one of them that select from the group of being made of ZnO, GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP.First semiconductor layer 105 can comprise resilient coating or the semiconductor layer that is not doped, and the lattice constant that this resilient coating has reduced between nitride-based semiconductor and the substrate 101 is poor.The semiconductor layer that is not doped can comprise the nitride-based semiconductor that is not doped.In other words, the semiconductor layer that is not doped is not by the semiconductor layer of conductive doped alloy painstakingly.The semiconductor layer that is not doped has obviously more weak conductivity than first conductive type semiconductor layer 110.For example, the semiconductor layer that is not doped can comprise the GaN layer that is not doped, and has the characteristic of first conduction type.
First semiconductor layer 105 can comprise superlattice structure, and can comprise from by GaN, InN, AlN, InGaN, AlGaN, InAlGaN, SiO 2, SiO x, SiN 2, SiN xAnd SiO xN yMaterial and the metal material selected in the group of forming.Superlattice structure comprises at least two pairs, wherein, alternately repeats to have at least two layers of different-energy band gap.For example, superlattice structure comprises the InGaN/GaN stacked structure.Every layer of thickness that can have several at least A of superlattice structure.
In addition, first semiconductor layer 105 can comprise the reflector with following structure, in this structure, alternately piles up at least two layers with different refractivity.For example, first semiconductor layer 105 can comprise the DBR (distributed Bragg reflector) of the stacked structure with at least two GaN/AlN layers.
First conductive type semiconductor layer 110 is formed on first semiconductor layer 105, and active layer 115 is formed on first conductive type semiconductor layer 110.Second conductive type semiconductor layer 120 is formed on the active layer 115.Also second half conductor layer can be arranged in each layer top or each layer below, but embodiment is not limited thereto.
First conductive type semiconductor layer 110 can comprise the III-V group element compound semiconductor that is doped with the first conduction type alloy.For example, first conductive type semiconductor layer 110 can comprise the material of selecting from the group of being made up of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP.First conductive type semiconductor layer 110 can comprise having In xAl yGa 1-x-yThe semi-conducting material of the composition formula of N (0≤x≤1,0≤y≤1,0≤x+y≤1).
First conductive type semiconductor layer 110 can comprise n type semiconductor layer.For example, n type semiconductor layer comprises N type alloy, for example, and Si, Ge, Sn, Se and Te.First conductive type semiconductor layer 110 can be used as contact electrode layer, and can have the single or multiple lift structure, but embodiment is not limited thereto.
First conductive type semiconductor layer 110 can comprise and wherein piles up the superlattice structure that different semiconductor layers are arranged.Superlattice structure comprises GaN/InGaN structure or GaN/AlGaN structure.Superlattice structure is several at least by piling up at least two pairs have
Figure BSA00000443936500051
Thickness two different layers and obtain.
First conductive type semiconductor layer 110 comprises the structure of at least two steps.For example, first conductive type semiconductor layer 110 can comprise that the width than the lower surface of first conductive type semiconductor layer 110 has the structure of more wide degree.
First conductive type semiconductor layer 110 comprises first 112 and second portion 113.First 112 can have identical semiconductor layer or different semiconductor layers with second portion 113.First 112 can be the bottom of first conductive type semiconductor layer 110, and second portion 113 can be the top of first conductive type semiconductor layer 110.First 112 and second portion 113 are owing to ledge structure is distinguished from each other.First 112 also can comprise following zone, and described zone has at least one side surface of being derived from second portion 113 or whole ledge structures of side surfaces.Therefore, second portion 113 can be set in the presumptive area of first 112.
The upper surface of second portion 113 can have the width narrower than the lower surface of first 112, and this width equates with the width of the lower surface of active layer 115 or wideer than it.The outer upper surface 111 of first 112 is than the more close substrate 101 of the upper surface of second portion 113, and outwardly disposed from the side surface of the side surface of second portion 113 or active layer 115.When checking in plane graph, the outer upper surface 111 of the first 112 of first conductive type semiconductor layer 110 is arranged to side surface than second conductive type semiconductor layer 120 more towards the outside.
As shown in Figure 2, the outer upper surface 111 of the first 112 of first conductive type semiconductor layer 110 begins to have the width W 1 of about 1 μ m to about 50 μ m from the side surface of second portion 113.Width W 1 can be the distance between the side surface of the side surface of second portion 113 and first 112.As shown in Figure 2, the side surface of active layer 115 is spaced apart with the preset distance G1 and first electrode 160, and prevents short circuit between semiconductor layer 113,115 and 120 apart from G1.
The outer upper surface 111 of the first 112 of first conductive type semiconductor layer 110 is used as the Ga-face, and can comprise light extraction structures, as coarse structure.
The upper surface of the second portion 113 of first conductive type semiconductor layer 110 can be an end face, and can be than the outer upper surface 111 more close active layers 115 of first 112.In addition, the outer upper surface 111 of first 112 can be than the more close substrate 101 of the end face of second portion 113.
Active layer 115 is formed on first conductive type semiconductor layer 110, and can have at least one that select from the group of being made up of single quantum, multi-quantum pit structure, quantum wire structure and quantum-dot structure.Active layer 115 can have stacked structure, and this stacked structure comprises trap layer and the barrier layer of being made by the III-V group iii v compound semiconductor material.For example, the trap layer of active layer 115 has In xAl yGa 1-x-yThe composition formula of N (0≤x≤1,0≤y≤1,0≤x+y≤1), and the barrier layer of active layer 115 has In xAl yGa 1-x-yThe composition formula of N (0≤x≤1,0≤y≤1,0≤x+y≤1).Active layer 115 can have from by at least one the stacked structure of selecting InGaN trap/GaN barrier layer, InGaN trap/AlGaN barrier layer and the group that the InGaN trap/the InGaN barrier layer is formed.
First conductive coating can be set between first conductive type semiconductor layer 110 and the active layer 115.First conductive coating can comprise the GaN base semiconductor.First conductive coating has the band gap bigger than the band gap of the barrier layer of active layer 115, and its limiting carrier.
Second conductive coating can be set between the active layer 115 and second conductive type semiconductor layer 120.Second conductive coating can comprise the GaN base semiconductor.Second conductive coating has the band gap bigger than the band gap of the barrier layer of active layer 115, and its limiting carrier.The width of active layer 115 can be narrower than the width of substrate 101.
Second conductive type semiconductor layer 120 is set on the active layer 115.Second conductive type semiconductor layer 120 can comprise the III-V group element compound semiconductor that is doped with the second conduction type alloy.For example, second conductive layer 120 can be selected from the group of being made up of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP.Preferably, second conductive type semiconductor layer 120 can comprise having In xAl yGa 1-x-yThe semi-conducting material of the composition formula of N (0≤x≤1,0≤y≤1,0≤x+y≤1).
Second conductive type semiconductor layer 120 has single layer structure or sandwich construction.If second conductive type semiconductor layer 120 has sandwich construction, then second conductive type semiconductor layer 120 can comprise superlattice structure, as the AlGaN/GaN structure.
Second conductive type semiconductor layer 120 can comprise p type semiconductor layer.For example, p type semiconductor layer comprises P type alloy, such as Mg, Be and Zn.Second conductive type semiconductor layer 120 can be used as contact electrode layer, but embodiment is not limited thereto.
First conductive type semiconductor layer 110, active layer 115 and second conductive type semiconductor layer 120 can be defined as ray structure layer 125.First conductive type semiconductor layer 110 can comprise P type semiconductor, and second conductive type semiconductor layer 120 can comprise n type semiconductor layer.Ray structure layer 125 can comprise the 3rd conductive type semiconductor layer on second conductive type semiconductor layer 120, and the 3rd conductive type semiconductor layer can comprise the semiconductor layer that has opposite polarity with second conductive type semiconductor layer.Ray structure layer 125 can comprise at least a in N-P junction structure, P-N junction structure, N-P-N junction structure and the P-N-P junction structure.In this case, " N " expression n type semiconductor layer, " P " represent P type semiconductor, and the structure that " " expression semiconductor layer directly or indirectly piles up each other.Hereinafter, the structure that wherein second conductive type semiconductor layer 120 is set at the superiors place of ray structure layer 125 describes as an example.
Second electrode 152 is set on second conductive type semiconductor layer 120, and comprises the pad 150 that is electrically connected to second electrode 152.Second electrode 152 can have single layer structure or sandwich construction, and it comprises select at least a from the group by Ti, Al, Al alloy, In, Ta, Pd, Co, Ni, Si, Ge, Ag, Ag alloy, Au, Hf, Pt, Ru and Au or their alloy composition.Can form at least one pad 150, and second electrode 152 is electrically connected to pad 150.For example, second electrode 152 can be with at least a pad 150 that is connected to of branch-like, arm shape and finger-shaped.
Second electrode 152 can have the ring-type at the peripheral part place of the end face of second conductive type semiconductor layer 120.This ring-type forms near the edge of second conductive type semiconductor layer 120.This ring-type can be formed continuous or discrete.Second electrode 152 can be near a plurality of first electrodes 160.
Current extending or transmission layer can be set between second electrode 152 and second conductive type semiconductor layer 120.Current extending comprises transmission oxide material or transmission nitride material.For example, current extending can comprise the material of selecting from the group of being made up of ITO (indium tin oxide), IZO (indium-zinc oxide), IZON (IZO nitride), IZTO (indium zinc tin oxide), IAZO (indium aluminium zinc oxide), IGZO (indium gallium zinc oxide), IGTO (indium gallium tin-oxide), AZO (aluminium zinc oxide), ATO (antimony tin oxide) and GZO (gallium zinc oxide).Current extending is formed on second conductive type semiconductor layer 120, and with current expansion in whole zone.
First electrode 160 can be arranged in not overlapping with active layer 115, in the simultaneously vertical zone with active layer 115.Preferably, first electrode 160 can be arranged in the channel region M, that is, expose in the zone of first conductive type semiconductor layer 110.First electrode 160 can be arranged in not overlapping with second electrode 152, at least one simultaneously vertical zone with second electrode 152.The zone that exposes first conductive type semiconductor layer 110 can be arranged on the outside of at least one side surface of active layer 115.
First electrode 160 can be spaced apart with at least one side surface of active layer 115, and is preferably, spaced apart with two side surfaces or four side surfaces of active layer 115.In addition, first electrode 160 can be arranged as the side surface of the first 112 of more close first conductive type semiconductor layer 110.First electrode 160 can be set to edge than more close first conductive type semiconductor layer 110 of the side surface of active layer 115.
At least one hole 165 is formed in the first 112 of substrate 101, first semiconductor layer 105 and first conductive type semiconductor layer 110.Hole 165 comprises electric conducting material.This electric conducting material can comprise metal.Can handle by plating and form first electrode 160.
First electrode 160 can comprise select a kind of from the group by Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag and Au or their alloy composition.First electrode 160 can comprise the conductive compound that contains metal.For example, first electrode 160 can comprise metal oxide, but embodiment is not limited thereto.
First electrode 160 can extend to the bottom of substrate 101 from the first 112 of first conductive type semiconductor layer 110.One first electrode 160 or a plurality of first electrode 160 can be set.If one first electrode 160 is set, then may not provide electric current smooth-goingly.The embodiment that adopts a plurality of first electrodes 160 will be described below.
The upper end of first electrode 160 can be exposed to the end face 111 of first 112, and the lower end of first electrode 160 can be exposed to the lower surface of substrate 101.
Each first electrode 160 can have from the first 112 of first conductive type semiconductor layer 110 wears via form to substrate 101.This via can have the circuit form perpendicular to the lower surface of substrate 101, perhaps is not orthogonal to the circuit form of the lower surface of substrate 101.
First electrode 160 can be spaced apart from each other with preset distance.For example, can arrange first electrode 160 periodically, randomly or brokenly.Interval between first electrode 160 can change according to the current efficiency and the pattern of second electrode 150.
At least one first electrode 160 can be arranged in the first 112 of first conductive type semiconductor layer 110, or be exposed to outside the outer wall of device.
First electrode 160 is exposed on outside the bottom of substrate 101.Can utilize the predetermined pattern or the predetermined layer of the bottom that is positioned at substrate 101, the electrode 160 of winning is interconnected each other.The lower end of first electrode 160 is used as pad, perhaps can form pad in addition.
Thickness T 1 between the first 112 of the lower surface of substrate 101 and first conductive type semiconductor layer 110 arrives about 3 μ m than the thick about 2 μ m of substrate thickness.The thickness of substrate 101 can be in about 100 μ m to the scope of about 400 μ m.The lower surface of substrate 101 can have flat structures or coarse structure, but embodiment is not limited thereto.
Fig. 2 is the plane graph of Fig. 1, and Fig. 3 is the upward view of Fig. 2.
With reference to Fig. 2 and Fig. 3, in second electrode 152, the width of pad 150 can be greater than the live width of second electrode 152.The live width of second electrode 152 can reduce gradually from pad 150 to predetermined portions, but embodiment is not limited thereto.
Pad 150 can be arranged between the corner, perhaps be arranged in the part place of corner, but embodiment be not limited thereto.
The edge of the pad 150 and more close second conductive type semiconductor layer 120 in center of second electrode, 152 to the second conductive type semiconductor layers 120 that are connected with pad 150, and it can be arranged to and make dotted line that electrode 160 the is connected with each other preset distance D4 of being separated by that wins.
Second electrode 152 and pad 150 are disposed in the edge of the end face of second conductive type semiconductor layer 120, but not the center of the end face of second conductive type semiconductor layer 120, thereby, can prevent by pad 150 and the optical loss that causes in the line of pad 150 combinations.
Also transmissive conductive layer is arranged between second conductive type semiconductor layer 120 and second electrode 152, so that can be in whole zone current expansion.Thus, can improve internal quantum efficiency (internal quantum efficiency).
The upper end of a plurality of first electrodes 160 is set on the upper surface 111 of first conductive type semiconductor layer 110, its with for example, at least one side surface in four side surfaces of active layer 115 is spaced apart, and second electrode 152 can have and a plurality of first electrode, 160 corresponding ring-types.
When the top of chip was observed, pad 150 can be positioned at the center of chip.Can in the technical scope of embodiment, make change to the layout of pad 150.
Second electrode 152 can be with branch-like from pad 150 branches.For example, second electrode 152 can have continuous annular or discontinuous ring-type.Second electrode 152 can have the multiple shape such as radiation pattern, at least one branch's pattern, arc patterns, straight-line pattern, polygon pattern, circular pattern or their combination, but embodiment is not limited thereto.
First electrode 160 is spaced apart from each other with distance D 1 or bigger distance on the upper surface of the first 112 of first conductive type semiconductor layer 110, and arranges corresponding to second electrode 152.As shown in Figure 2, the upper end of first electrode 160 is set to and second electrode, 152 interval preset distances.Can be along the lower end of arranged around first electrode 160 of the lower surface 101A of substrate 101, as shown in Figure 3.
Owing to first electrode 160 is arranged corresponding to second electrode 152, therefore, electric current can be flowed through the whole zone of ray structure layer 125 equably.
The last diameter D2 (shown in Fig. 2) of first electrode 160 can be less than the following diameter (shown in Fig. 3) or the width D 3 of first electrode 160.Last diameter or width D 2 can be in about 1 μ m to the scope of about 50 μ m.Although first electrode 160 has circular profile shown in the drawings, first electrode 160 also can have various profiles, for example polygon, ellipse or the shape that the angle is arranged except circle and spherical combination.
As shown in Figure 1, transmissive substrate 101 is disposed in the luminescent device with vertical-type electrode structure, thereby energy improve the angle of departure of the light of advancing owing to the thickness of transmissive substrate 101.Thus, can improve light extraction efficiency.
Fig. 4 A and Fig. 4 B show the figure in the hole 165 of Fig. 1.
Shown in Fig. 4 A, hole 165 can have trapezoidal shape.Following diameter (or width) D3 in hole 165 is in about 0.5 μ m to the scope of about 50 μ m, and last diameter (or width) D2 in hole 165 is in about 0.5 μ m to the scope of about 20 μ m.In this case, can under the condition of D3>D2, form hole 165.Last diameter D2 and following diameter D3 can change according to the size of device.With respect to the imaginary axis vertical with the lower surface of substrate 101, can satisfy condition 1<30 ° of 0<θ of the tiltangle 1 in hole 165.Because the shape in hole 165 can be roughly the same with the shape of first electrode 160, therefore, the shape of first electrode 160 is with the benchmark that is shaped as in hole 165.
Shown in Fig. 4 B, hole 165A has incline structure, and this incline structure has around the various angles perpendicular to the imaginary axis of the lower surface of substrate 101, and this incline structure is set at the bottom of hole 165A.The incline structure that is set at the bottom of hole 165A can have the lower end, and this lower end has the width wideer than the width of upper end.
Fig. 5 to Figure 10 shows the profile of manufacture process of the luminescent device of Fig. 1.
With reference to Fig. 5, substrate 101 is carried on the growth apparatus, and II to VI group element compound semiconductor layer can be formed on the substrate 101.
This growth apparatus can comprise: electron beam deposition equipment, PVD (physical vapor deposition) equipment, CVD (chemical vapor deposition) equipment, PLD (plasma laser deposition) equipment, dimorphism hot vaporizer, sputtering equipment and MOCVD (metal organic chemical vapor deposition) equipment.But embodiment is not limited thereto.
Substrate 101 can comprise conductive substrates or dielectric substrate.For example, substrate 101 can comprise from by sapphire (Al 2O 3), GaN, SiC, ZnO, Si, GaP, InP, Ga 2O 3The material of selecting in the group of forming with GaAs.Substrate 101 can be provided with concaveconvex structure on its end face, it comprises lenticular or striated, and this concaveconvex structure can comprise pattern or rough line.In addition, can be provided with first semiconductor layer 105 on the substrate 101, and first semiconductor layer 105 can comprise semi-conductive layer of use II to VI group element compound or pattern.For example, can be with at least a being formed on the substrate 101 in ZnO layer (not shown), resilient coating (not shown) and the semiconductor layer (not shown) that is not doped.Resilient coating and the semiconductor layer that is not doped can comprise the compound semiconductor of III-V family element.It is poor that resilient coating has reduced with the lattice constant of substrate 101.The semiconductor layer that is not doped has the conductance lower than first conductive type semiconductor layer 110, and can comprise the GaN base semiconductor that is not doped.
First semiconductor layer 105 can comprise from by GaN, InN, AlN, InGaN, AlGaN, InAlGaN, SiO 2, SiO x, SiN 2, SiN xAnd SiO xN yMaterial and the metal selected in the group of forming.First semiconductor layer 105 can have heterojunction superlattice structure or light extraction structures.First semiconductor layer 105 can have dbr structure, wherein, has at least two layer alternating growths of different refractivity.In resilient coating, the semiconductor layer that is not doped, superlattice structure and the dbr structure at least one can be formed on the substrate 101.
With reference to Fig. 5 and 6, ray structure layer 125 can be formed on first semiconductor layer 105.Ray structure layer 125 comprises first conductive type semiconductor layer 110, active layer 115 and second conductive type semiconductor layer 120.Also another layer can be arranged on the top of each layer or below, but embodiment is not limited thereto.
First conductive type semiconductor layer 110 is formed on first semiconductor layer 105, and can comprise one of them that select from the group that the semi-conductive GaN of III-V group element compound, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and the AlGaInP that are doped with first conductive dopant by conduct form.First conductive type semiconductor layer 110 can comprise having In xAl yGa 1-x-yThe semi-conducting material of the composition formula of N (0≤x≤1,0≤y≤1,0≤x+y≤1).First conductive type semiconductor layer 110 is a n type semiconductor layer, and this n type semiconductor layer comprises N type alloy, such as Si, Ge, Sn, Se or Te.First conductive type semiconductor layer 110 can be used as contact electrode layer, and can have single or multiple lift.But embodiment is not limited thereto.
First conductive type semiconductor layer 110 can have superlattice structure, and wherein, different semiconductor layers is alternately piled up, and this superlattice structure comprises GaN/InGaN structure or GaN/AlGaN structure.
Active layer 115 is formed on first conductive semiconductor layer 110, and can have single quantum or multi-quantum pit structure.Active layer 115 can have stacked structure, and this stacked structure comprises trap layer and the barrier layer of being made by the III-V group iii v compound semiconductor material.For example, active layer 115 can have from by at least one the stacked structure of selecting InGaN trap/GaN barrier layer, InGaN trap/AlGaN barrier layer and the InGaN trap/InGaN barrier layer.
First conductive coating can be inserted between first conductive type semiconductor layer 110 and the active layer 115.First conductive coating can comprise the GaN base semiconductor.First conductive coating has the band gap bigger than the band gap of the barrier layer of active layer 115, and its limiting carrier.
Second conductive coating can be inserted between second conductive type semiconductor layer 120 and the active layer 115.Second conductive coating can comprise the GaN base semiconductor.Second conductive coating has the band gap bigger than the band gap of the barrier layer of active layer 115, and its limiting carrier.
Second conductive type semiconductor layer 120 is set on the active layer 115.Second conductive type semiconductor layer 120 can comprise the III-V group element compound semiconductor that is doped with the second conduction type alloy.For example, second conductive layer 120 can be selected from the group of being made up of GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, AlGaAs, GaP, GaAs, GaAsP and AlGaInP.Preferably, second conductive type semiconductor layer 120 can comprise having In xAl yGa 1-x-yThe semi-conducting material of the composition formula of N (0≤x≤1,0≤y≤1,0≤x+y≤1).
Second conductive type semiconductor layer 120 has single layer structure or sandwich construction.If second conductive type semiconductor layer 120 has sandwich construction, then second conductive type semiconductor layer 120 can comprise superlattice structure, as the AlGaN/GaN structure.
Second conductive type semiconductor layer 120 can comprise p type semiconductor layer.For example, p type semiconductor layer comprises P type alloy, such as Mg, Be and Zn.Second conductive type semiconductor layer 120 can be used as contact electrode layer, but embodiment is not limited thereto.
First semiconductor layer 110, active layer 115 and second conductive type semiconductor layer 120 can be defined as ray structure layer 125.Ray structure layer 125 also can comprise the 3rd conductive type semiconductor layer on second conductive type semiconductor layer 120, and the 3rd conductive type semiconductor layer can comprise the semiconductor layer that has opposite polarity with second conductive type semiconductor layer.Ray structure layer 125 can comprise at least a in N-P junction structure, P-N junction structure, N-P-N junction structure and the P-N-P junction structure.In this case, " N " expression n type semiconductor layer, " P " represent P type semiconductor, and the structure that "-" expression semiconductor layer directly or indirectly piles up each other.Hereinafter, the structure that wherein second conductive type semiconductor layer 120 is set at the superiors place of ray structure layer 125 describes as an example.
With reference to Fig. 7, carry out etch processes.For example, carry out etch processes with the desired depth of distance second conductive type semiconductor layer 120.With respect to the peripheral part of chip, promptly channel region is carried out etch processes.Etch processes can comprise in order to the isolation etch processes of cutting apart chip and/or in order to the mesa etch of the part that exposes first conductive type semiconductor layer 110 to be handled.
By etch processes, the part of first conductive type semiconductor layer 110, for example, the upper surface of first 112 is exposed.In first conductive type semiconductor layer 110, first 112 and second portion 113 form ledge structure.In other words, by etch processes, the border between the chip, that is, channel region M1 is exposed.
With reference to Fig. 8, a plurality of holes 165 are formed in the channel region M1.By using laser and/or drilling tool, hole 165 can extend to the lower surface of substrate 101 from the first 112 of first conductive type semiconductor layer 110.
The landform pore-forming 165 as shown in Figures 2 and 3.Hole 165 can have the structure of the diameter of upper end less than the diameter of lower end, as shown in Figure 4.
Outer peripheral portion along independent chip forms hole 165.Interval between the hole 165 can be constant, irregular or at random.For example, at least one that can be in four sidewalls of each chip and form hole 165 is perhaps in two opposing sidewalls of chip or all form hole 165 on the sidewall.
With reference to Fig. 9, second electrode 152 is formed in second conductive type semiconductor layer 120, and first electrode 160 is formed in the hole 165 of first conductive type semiconductor layer 110.For example, first electrode 160 can be handled formation by plating after forming crystal seed layer, perhaps can handle forming by filler, but embodiment is not limited thereto.
First electrode 160 can comprise select a kind of from the group by Cu, Ti, Cr, Ta, Al, In, Pd, Co, Ni, Ge, Ag and Au or their alloy composition.First electrode 160 can comprise non-metallic conducting material, but embodiment is not limited thereto.
Second electrode 152 comprises pad 150.Second electrode 152 can have single layer structure or sandwich construction, and it comprises select at least a from the group by Ti, Al, Al alloy, In, Ta, Pd, Co, Ni, Si, Ge, Ag, Ag alloy, Au, Hf, Pt, Ru and Au or their alloy composition.Although second electrode 152 can comprise at least one pad 150,, two pads just can be set, but embodiment is not limited thereto if second electrode 152 has big area.
Second electrode 152 is connected to pad 150, and can have ring-type, rectilinear form, arcuate shape, polygon-shaped and round-shaped at least a, but embodiment is not limited thereto.
Current extending can be formed between second electrode 152 and second conductive type semiconductor layer 120.Current extending can be formed on second conductive type semiconductor layer 120.Can before or after carrying out etch processes, form current extending, but embodiment is not limited thereto.Current extending can comprise transmission oxide material or transmission nitride material.For example, current extending can comprise the material of selecting from the group of being made up of ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO and GZO.But, can form current extending, but embodiment is not limited thereto.
Subsequently, form independent chip shown in Figure 10 by cutting process or break process along the line of demarcation C1 between the chip.
With reference to Figure 10, a plurality of first electrodes 160 are set on the lower surface of substrate 101, and the power supply with first polarity is provided to first conductive type semiconductor layer 110 via first electrode 160.The pad 150 of second electrode 152 is connected to the connecting elements such as wiring, and receives the electric power with second polarity.In addition, the electric power with second polarity is provided to second conductive type semiconductor layer 120 via the pad 150 and second electrode 152.Therefore, can will supply power to the entire portion of luminescent device 100 uniformly, thereby can improve internal quantum efficiency.
Figure 11 to Figure 13 shows the figure of another example of the hole in the channel region of luminescent device and first electrode.The hole is irregularly formed in light-emitting zone.Reference symbol A1 and A2 represent chip area, and reference symbol C1 is illustrated in the interior line of demarcation that the first of first conductive type semiconductor layer is separated of chip area.
With reference to Figure 11, hole 165 can be arranged in the both sides of the boundary line C1 in the area of isolation of two adjacent chips zone A1 and A2.Hole 165 can be disposed in each chip area A1 and the A2.
Electrode 160A is formed in the hole 165, and extends at the lip-deep conductive pattern place of area of isolation, thereby electrode 160A can be arranged in each chip area A1 and the A2.In this case, the width that conductive pattern can have from boundary line C 1 towards each chip area A1 and A2 limits.
In this case, the width in two adjacent chips zones can be in about 5 μ m to the scope of about 100 μ m, and can be used as the channel region between the chip on the substrate.
With reference to Figure 12, during the both sides of the boundary line C1 in the area of isolation that hole 165 can be arranged in two adjacent chips zone A1 and A2, hole 165 can be distributed to each among chip area A1 and the A2.The conductive pattern place of electrode 160B in the inside in hole 165 and the lip-deep conductive pattern place extension in hole 165, thus electrode 160B can be arranged in each chip area A1 and the A2.
With reference to Figure 13, in the time of on the boundary line C1 in the channel region that hole 165 can be formed on two adjacent chips zone A1 and A2, hole 165 can shared each chip area A1 and the area of isolation of A2.The conductive pattern place of the first electrode 160C in the inside in hole 165 and the lip-deep conductive pattern place extension in hole 165, thus the first electrode 160C can be electrically connected to each chip area A1 and A2.In this case, conductive pattern can extend and can be electrically connected to the semiconductor layer (for example, first conductive type semiconductor layer 110) of each chip area A1 and A2 from boundary line C1.In this case, the outside of the first electrode 160C can be exposed to the outside of chip.
Figure 14 shows the side cutaway view according to the luminescent device of second embodiment.In the following relevant description of second embodiment,, structure and the parts identical with first embodiment are described no longer for avoiding redundant.
With reference to Figure 14, luminescent device 100A comprises the ray structure layer 125 (110,115 and 120) with inclined side surfaces S1.First conductive layer 161 can be set at the peripheral part of first conductive type semiconductor layer 110.First conductive layer 161 can extend to the side surface of second portion 113 from the end face 111 of the first 112 of first conductive type semiconductor layer 110.First conductive layer 161 can comprise and the material identical materials of first electrode, another kind of conductive metallic material or transmissive conductive material.
First conductive layer 161 makes the upper end of at least two first electrodes 160 be connected with each other, the electric power that supply stably has first polarity, and extend current.First conductive layer 161 has preset width, and can have closed loop shape or open loop-shaped.One first conductive layer 161 or a plurality of first current carrying part 161 can be set, but embodiment is not limited thereto.
The lower end 163 of first electrode 160 can be arranged individually, can be that unit is connected with each other with one group perhaps.
Second electrode 150 comprises pad, and current extending 155 can be arranged between the pad and second conductive type semiconductor layer 120.Current extending 155 can be formed on the almost entire portion of second conductive type semiconductor layer 120.Current extending 155 can comprise transmission conductive oxide or transmission conductive nitride.Current extending 155 can comprise the material of selecting from the group of being made of ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO and GZO.Can form current extending 155, but embodiment is not limited thereto.
Figure 15 shows the side cutaway view according to the luminescent device of the 3rd embodiment.In the following relevant description of the 3rd embodiment,, structure and the parts identical with first embodiment are described no longer for avoiding redundant.
With reference to Figure 15, in luminescent device 100B, first electrode 160 passes the first 112 and the substrate 101 of first conductive type semiconductor layer 110.In luminescent device 100B, the end face 111 of the first 112 of first conductive type semiconductor layer 110 and the end face of first semiconductor layer 105 can expose.Although the example that exposes first semiconductor layer 105 has been described, the end face of the outside of substrate 101 also can expose.
In the second channel region M2, the end face of first semiconductor layer 105 can further expose owing to isolating etch processes, thereby makes chip be separated from each other.Can handle via mesa etch and form the first channel region M1, thereby expose the part of first conductive type semiconductor layer 110.The first channel region M1 and the second channel region M2 can have ledge structure.
First electrode 160 has first conductive layer 161 therein from the end face 111 of first conductive type semiconductor layer 110 extends and the second conductive layer 161A extends at the end face of first semiconductor layer 105 structure.Because first electrode 160 has the expansion pattern that passes first conductive layer 161 and the second conductive layer 161A, so stablizing with the side surface of first conductive type semiconductor layer 110, first electrode 160 contact, thus can the effective supply electric current.
First conductive layer 161 can separate with active layer 115 with preset distance D6.Insulating barrier 190 can be set at the outside of second portion 113, active layer 115 and second conductive type semiconductor layer 120 of first conductive type semiconductor layer 110.Insulating barrier 190 can prevent electrical short, and is applicable to other embodiment.
Figure 16 shows the side cutaway view according to the luminescent device of the 4th embodiment, and Figure 17 is the plane graph of Figure 16.In the following relevant description of the 4th embodiment,, structure and the parts identical with first embodiment are described no longer for avoiding redundant.
With reference to Figure 16 and Figure 17, in luminescent device 100C, first conductive layer 161 is set on the end face 111 of first 112 of first conductive type semiconductor layer 110.First conductive layer 161 is electrically connected to each other the electrode 160 of winning, as shown in figure 17.First conductive layer 161 can have ring-type, perhaps can be divided into a plurality of zones.
Electrode layer 170 is formed on the lower surface of substrate 101.Electrode layer 170 can comprise select a kind of from the group by Ag, Ag alloy, Ni, Al, Al alloy, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf or their alloy composition.Electrode layer 170 can be used as reflecting electrode.Electrode layer 170 can be used as the binder course that is used for chips incorporate.
Can form electrode layer 170 by piling up two kinds of materials with different refractivity.For example, can form electrode layer 170 by piling up at least two kinds of materials from the group of forming by ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, GZO, Ag, Ag alloy, Ni, Al, Al alloy, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf, selecting.
In addition, according to embodiment, except that electrode layer 170, also heating plate can be set.This heating plate can comprise the metal material with excellent heat conductivity.Heating plate can be connected to electrode layer 170, perhaps can separate with electrode layer 170.
Figure 18 shows the side cutaway view according to the luminescent device of the 5th embodiment.In the following relevant description of the 5th embodiment,, structure and the parts identical with the 4th embodiment are described no longer for avoiding redundant.
With reference to Figure 18, in luminescent device 100C, the part of the end face of the part of first conductive type semiconductor layer 110 and first semiconductor layer 105 can expose.Can form the part of the end face of the part of first conductive type semiconductor layer 110 and first semiconductor layer 105 via at least two kinds of etch processes.
In this case, above-mentioned at least two kinds of etch processes comprise isolation etch processes and mesa etch processing.The second channel region M2 can expose by isolating etch processes, and the first channel region M1 can handle exposure by mesa etch.The first channel region M1 and the second channel region M2 can handle by dry etching and expose, but embodiment is not limited thereto.Can will not participate in a luminous part among channel region M1 and the M2 as electrode district.
First conductive layer 161 that first electrode 160 comprises on the end face 111 of the first 112 that is arranged on first conductive type semiconductor layer 110 and realizes electrically contacting.Can not will second conductive layer be formed on the end face of first semiconductor layer 105.
First conductive layer 161 is electrically connected to each other the electrode 160 of winning, as shown in figure 17.One first conductive layer 161 or a plurality of first conductive layer 161 can be set.If a plurality of first conductive layers 161 are set, then first conductive layer 161 can be spaced apart from each other.
First electrode 160 can extend to the lower end of substrate 191 from the side surface of the first 112 of first conductive type semiconductor layer 110, and can be connected to the lower surface of first conductive layer 161.
Electrode layer 170 is formed on the lower surface of substrate 101.Electrode layer 170 can comprise select a kind of from the group by Ag, Ag alloy, Ni, Al, Al alloy, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf or their alloy composition, and can be used as reflecting electrode.In addition, electrode layer 170 can be used as the binder course that is used for chips incorporate.
Can form electrode layer 170 by piling up two kinds of materials with different refractivity.For example, can form electrode layer 170 by piling up at least two kinds of materials from the group of forming by ITO, IZO, IZTO, IAZO, IGZO, IGTO, AZO, ATO, GZO, Ag, Ag alloy, Ni, Al, Al alloy, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au and Hf, selecting.
Figure 19 shows the side cutaway view according to the luminescent device of the 6th embodiment.In the following relevant description of the 6th embodiment,, structure and the parts identical with first embodiment are described no longer for avoiding redundant.
With reference to Figure 19, in luminescent device 100D, concaveconvex structure 102 is formed on the substrate 101, and can reflect the light that penetrates from active layer 115.Concaveconvex structure 102 changes of substrate 101 advance to the critical angle of the light of substrate 101 from active layer 115, thereby can improve external quantum efficiency.
First semiconductor layer 105 can have the concaveconvex structure 102 corresponding concaveconvex structures with substrate 101.Concaveconvex structure 102 can comprise the spaced apart pattern with 1/2 λ or 1/4 λ.
Figure 20 shows the side cutaway view according to the luminescent device of the 7th embodiment.In the following relevant description of the 7th embodiment,, structure and the parts identical with first embodiment are described no longer for avoiding redundant.
With reference to Figure 20, in luminescent device 100E, concaveconvex structure 103 and electrode layer 170 are formed on the lower surface of substrate 101.Electrode layer 170 can with the concaveconvex structure 103 corresponding formation of substrate 101.Electrode layer 170 can be used as reflecting electrode.Concaveconvex structure 103 can have the spaced apart pattern with 1/2 λ or 1/4 λ.
The concaveconvex structure 103 that is formed on the lower surface of substrate 101 can change the critical angle that is mapped to the light of substrate 101 from active layer 115.Electrode layer 170 can reflect incident light.The concaveconvex structure 103 of substrate 101 and electrode layer 170 change the critical angle of 101 light of advancing from active layer 115 towards substrate downwards, thereby can improve external quantum efficiency.According to embodiment, the concaveconvex structure of Figure 19 can be formed on the substrate 101, but embodiment is not limited thereto.
Figure 21 shows the side cutaway view according to the luminescent device of the 8th embodiment.In the following relevant description of the 8th embodiment,, structure and the parts identical with first embodiment are described no longer for avoiding redundant.
With reference to Figure 21, in luminescent device 100F, the end face 111 of the first 112 of the end face of substrate 101 and first conductive type semiconductor layer 110 is exposed.
First electrode 160 passes substrate 101, and via the end face of substrate 101 and lower surface and expose.The 3rd conductive layer 163A be set at first electrode 160 the lower end below, and the electrode 160 of winning is electrically connected to each other.
The 3rd conductive layer 160B is formed on the upper end of first electrode 160, and extends to the end face 111 of the first 112 of first conductive type semiconductor layer 110 from the end face of substrate 101.The last end in contact of the lower end of the 3rd conductive layer 160B and first electrode 160, and the inside of the 3rd conductive layer 160B contacts with the side surface of the first 112 of first conductive type semiconductor layer 110.Therefore, first electrode 160 and third electrode layer 160B can be in the whole zone of first conductive type semiconductor layer 110 supply of current equably.
According to embodiment, the 3rd conductive layer 163A can comprise metal material, perhaps can comprise conducting strip and/or electrode, but embodiment is not limited thereto.
The 3rd conductive layer 160B is spaced apart with the side surface of the second portion 113 of the preset distance D7 and first conductive type semiconductor layer 110, thereby prevents layer short circuit.
The width of the comparable substrate 101 of the width of the width of active layer 115 and first conductive type semiconductor layer 110 is narrower.
Figure 22 shows the side cutaway view according to the luminescent device of the 9th embodiment.In the following relevant description of the 9th embodiment,, structure and the parts identical with first embodiment are described no longer for avoiding redundant.
With reference to Figure 22, luminescent device comprises a plurality of first conductive layers 161, and one or more first electrode 160 be set at first conductive layer 161 below.Pad 150 can be set at the center of second conductive type semiconductor layer 120, but embodiment is not limited thereto.
According to embodiment, luminescent device can carry out the local mesa etch processes with the width of first conductive layer 161.According to the local mesa etch processes, the zone that needs to form electrode is subjected to etching, and forms the hole in etching area, thereby forms first electrode 160 and first conductive layer 161.In this case, because active layer is not etched, therefore, can will not be subjected to the zone of mesa etch processing as light-emitting zone.Thus, can improve disclosed light-emitting area among the embodiment.
Thereby first electrode 160 can be connected to the outside of first conductive type semiconductor layer 110 by first conductive layer 161.The outside of substrate 101 can expose via isolating etch processes.
Figure 23 shows the sectional view according to the luminescent device encapsulation of the tenth embodiment.
With reference to Figure 23, luminescent device encapsulation 30 comprises: main body 20; The first and second lead-in wire electrodes 31 and 32, this first and second lead-in wires electrode 31 and 32 is formed on the main body 20; According to the luminescent device 100 of embodiment, it is disposed on the main body 20 and electrically is connected to the first and second lead-in wire electrodes 31 and 32; And shaped component 40, this shaped component 40 surrounds luminescent device 100.
Main body 20 can be silicon, synthetic resin or metal material.Cavity 22 can be formed on the office, top of main body 20, and luminescent device 100 is provided in the cavity 25.Inclined surface can be formed on luminescent device 100 around.Cavity 25 can tilt perpendicular to the lower surface of main body 20 or with respect to the lower surface of main body 20, but embodiment is not limited thereto.
The first and second lead-in wire electrodes 31 and 32 are electrically isolated mutually, electric power is offered luminescent device 100.In addition, improving optical efficiency, and the thermal transpiration that will produce from luminescent device 100 is to the outside from the light of luminescent device 100 emission for the first and second lead-in wire electrodes 31 and 32 reflections.
Luminescent device 100 can be installed on the main body 20, perhaps on the first and second lead-in wire electrodes 31 and 32.
Luminescent device 100 is connected to the first lead-in wire electrode 31 by wiring, and chips incorporate to the second lead-in wire electrode 32.
Shaped component 40 can surround luminescent device 100 with protection luminescent device 100.In addition, shaped component 40 comprises fluorophor, to change from luminescent device 100 wavelength of light emitted.
Luminescent device according to embodiment (embodiment) is attached to the second lead-in wire electrode 32 by insulated substrate or growth substrate by chip, and packed, thereby luminescent device can be used as the light source of indicating device, illuminating device and display device.Embodiment can optionally be can be applicable to another embodiment.
Luminescent device or luminescent device encapsulation according to embodiment can be applied to lighting unit as light source.Lighting unit has the structure of wherein arranging a plurality of luminescent device encapsulation, and comprises the head lamp and the electronic mark board of illuminating lamp, signal lamp, vehicle.
<illuminator 〉
Luminescent device encapsulation according to embodiment can be applied to lighting unit.Lighting unit comprises a plurality of luminescent devices or the luminescent device encapsulation that is arranged in the lighting unit.Lighting unit can comprise the head lamp and the electronic mark board of illuminating lamp, signal lamp, vehicle.
Illuminator can comprise the illuminating device shown in the display device shown in Figure 24 and Figure 25, Figure 26, illuminating lamp, signal lamp, auto bulb, electronic console or the like.
Figure 24 is the decomposition diagram that illustrates according to the display device of embodiment.
With reference to Figure 24, can comprise according to the display unit 1000 of embodiment: light guide plate 1041; Light emitting module 1031, described light emitting module 1031 offers light guide plate 1041 with light; Reflecting member 1022, described reflecting member 1022 is below light guide plate 1041; Optical sheet 1051, described optical sheet 1051 is on light guide plate 1041; Display floater 1061, described display floater 1061 is on optical sheet 1051; And bottom 1011, described bottom 1011 holds light guide plate 1041, light emitting module 1031 and reflecting member 1022; Yet it is not limited thereto.
Bottom 1011, reflector plate 1022, light guide plate 1041 and optical sheet 1051 can be defined as lighting unit 1050.
Light guide plate 1041 is used for diffused light, is surface source of light so that it is assembled.Utilize transparent material to form light guide plate 1041, and light guide plate 1041 for example can comprise in allyl resin, polyethylene terephthalate (PET), Merlon (PC), cycloolefin co-polymer (COC) and Polyethylene Naphthalate (PEN) resin such as polymethyl methacrylate (PMMA).
Light emitting module 1031 offers at least one side of light guide plate 1041 with light, and finally is used as the light source of display device.
Comprise at least one light emitting module 1031, and light emitting module 1031 can provide light at a side place of light guide plate 1041 directly or indirectly.Light emitting module 1031 comprises luminescent device encapsulation 30 and the substrate 1033 according to the foregoing description.Luminescent device encapsulation 30 can be arranged on the substrate 1033 with predetermined interval.
Substrate 1033 can be the printed circuit board (PCB) (PCB) that comprises the circuit pattern (not shown).Yet substrate 1033 not only can comprise typical PCB, and can comprise metal core PCB (MCPCB) or flexible PCB (FPCB), and it is not limited thereto.Be installed on the side of bottom 1011 in luminescent device encapsulation 30 or under the situation on the heating panel, substrate 1033 can be cancelled.At this, the part of heating panel can touch the upper surface of bottom 1011.
A plurality of luminescent device encapsulation 30 can be installed on the substrate 1033, make light-emitting area separate predetermined distance with light guide plate 1041, and there is not restriction in this.Luminescent device encapsulation 30 can directly or indirectly offer light the light entering part, that is, and and a side of light guide plate 1041, and this is not existed restriction.
Reflecting member 1022 can be set at the below of light guide plate 1041.Reflecting member 1022 is at the light that upwards reflects the lower surface that is incided light guide plate 1041 upward, thus the brightness that can improve lighting unit 1050.For example, for example can utilize PET, PC or PVC (polyvinyl chloride) resin to form reflecting member 1022; Yet it is not limited thereto.Reflecting member 1022 can be the upper surface of bottom 1011; Yet, this is not existed restriction.
Bottom 1011 can hold light guide plate 1041, light emitting module 1031 and reflecting member 1022.For this reason, bottom 1011 can be provided with memory cell 1012, and it has its upper surface by the box-like shape of opening, and there is not restriction in this.Bottom 1011 can make up with top cover, and there is not restriction in this.
Can utilize metal material or resin material to form bottom 1011, and can use and push or extrusion forming process is made bottom 1011.Bottom 1011 can also comprise metal or the nonmetallic materials with outstanding thermal conductivity, and there is not restriction in this.
Display floater 1061 for example is, the LCD panel, and comprise first and second substrates of transmission and the liquid crystal layer between first and second substrates.On at least one side of display floater 1061, can attached polarization plates; Yet attachment structure is not limited thereto.Display floater 1061 comes display message by the light that passes optical sheet 1051.Display device 1000 can be applied to the monitor of various cell phones, notebook, the monitor and the TV of laptop computer.
Optical sheet 1051 is set between display floater 1061 and the light guide plate 1041, and comprises at least one translucent.Optical sheet 1051 can comprise at least one in for example diffusion sheet, level and vertical prism sheets, the brightness enhancement sheet.The diffusion sheet diffusion into the light emitted.Level is or/and vertical prism sheets concentrates on the viewing area with incident light.Brightness enhancement sheet is reused the light lost to highlight.Screening glass can be disposed on the display floater 1061, and there is not restriction in this.
At this, on the light path of light emitting module 1031, light guide plate 1041 and optical sheet 1051 can be included as optical component; Yet, this is not existed restriction.
Figure 25 is the figure that illustrates according to the display unit of embodiment.
With reference to Figure 25, display unit 1100 comprises: bottom 1152, substrate 1120, optical component 1154 and display floater 1155.At this, above-mentioned luminescent device encapsulation 30 is arranged on the substrate 1120.
Substrate 1120 and luminescent device encapsulation 30 can be defined as light emitting module 1060.Bottom 1152, at least one light emitting module 1060 and optical component 1154 can be defined as lighting unit.
Bottom 1152 can be provided with memory cell 1153, and there is not restriction in this.
At this, optical component 1154 can comprise at least one in lens, light guide plate, diffusion sheet, level and vertical prism sheets and the brightness enhancement sheet.Can utilize PC material or polymethyl methacrylate (PMMA) material to form light guide plate, and can remove this light guide plate.The diffusion sheet diffusion into the light emitted.Level or/and vertical prism sheets incident light is concentrated on the viewing area.Brightness enhancement sheet is reused the light lost to highlight.
Optical component 1154 is set on the light emitting module 1060.Optical component 1154 will be converted to surface source of light from the light of light emitting module 1060 emissions, perhaps light be carried out diffusion or collection.
Figure 26 is the perspective view that illustrates according to the illuminating device of embodiment.
With reference to Figure 26, illuminating device 1500 comprises: housing 1510; Light emitting module 1530, this light emitting module 1530 is installed to housing 1510; And splicing ear 1520, this splicing ear 1520 is installed to housing 1510, and is provided with the electric power that comes from external power source.
Preferably, utilize material to form housing 1510 with excellent heat dissipation characteristics.For example, can utilize metal material or resin material to form housing 1510.
Light emitting module 1530 can comprise substrate 1532 and be installed on the substrate 1532 according to the luminescent device of embodiment encapsulation 30.A plurality of luminescent device encapsulation 30 can be arranged with the form of matrix, perhaps arrange with predetermined interval with being separated from each other.
Substrate 1532 can be the insulator that wherein is printed on circuit pattern.For example, substrate 1532 can comprise PCB, metal core PCB, flexible PCB, ceramic PCB and FR-4 substrate.
Substrate 1532 can also utilize catoptrical effectively material to form, and perhaps its surface can be coated with catoptrical effectively color, for example, and white or silver color.
At least one luminescent device encapsulation 30 can be installed on the substrate 1532.Each luminescent device encapsulation 30 can comprise at least one light-emitting diode (LED) chip.Led chip can comprise the light-emitting diode such as the visible light of red, green, blue or white, perhaps the UV light-emitting diode of emission ultraviolet ray (UV).
The combination of various luminescent device encapsulation 30 can be disposed in the light emitting module 1530, to obtain shade of color and brightness.For example, in order to ensure high color rendering index (CRI) (CRI), can make up and arrange white light emitting diode, red light-emitting diode and green light LED.
Splicing ear 1520 can electrically be connected to light emitting module 1530 so that electric power to be provided.Splicing ear 1520 is threaded onto external power source with the method for socket; Yet, this is not existed restriction.For example, the shape that splicing ear 1520 can be formed pin perhaps can be connected to external power source by wiring to be inserted into external power source.
A kind of manufacturing comprises the steps: to form a plurality of compound semiconductor layers that comprise first conductive type semiconductor layer, active layer and second conductive type semiconductor layer according to the method for the luminescent device of embodiment on substrate; Expose the part of first conductive type semiconductor layer by first etch process; Formation is penetrated at least one hole of the lower surface of substrate from first conductive type semiconductor layer that is exposed; And at least one hole, form at least one first electrode, make to form electrical connection from the lower surface of substrate to the part of first conductive type semiconductor layer by electrode.
In this manual, anyly mean in conjunction with the embodiments that for quoting of " embodiment ", " embodiment ", " exemplary embodiment " etc. special characteristic, structure or the characteristic described are included among at least one embodiment of the present invention.In specification, identical embodiment needn't all be represented in this class phrase of Chu Xianing throughout.In addition, when describing special characteristic, structure or characteristic in conjunction with any embodiment, other embodiment in thinking in conjunction with the embodiments realizes that such feature, structure or characteristic are also in those skilled in the art's understanding scope.
Though described embodiment, should be appreciated that those skilled in the art can design many interior other modification and embodiment of spirit and scope that will fall into the principle of present disclosure with reference to a plurality of exemplary embodiments of the present invention.More specifically, in the scope of present disclosure, accompanying drawing and appended claims, the building block that the combination of theme is arranged and/or the variations and modifications of layout aspect all are possible.Except the variation and modification of building block and/or layout aspect, for a person skilled in the art, alternative use also will be conspicuous.

Claims (15)

1. luminescent device comprises:
Substrate;
The ray structure layer, described ray structure layer comprises active layer on first conductive type semiconductor layer, described first conductive type semiconductor layer and second conductive type semiconductor layer on the described active layer, wherein, described first conductive type semiconductor layer is formed on the described substrate and has first upper surface and second upper surface, wherein, described second upper surface is than the more close described substrate of described first upper surface;
Second electrode on described second conductive type semiconductor layer; And
At least one first electrode, described at least one first electrode is by passing described substrate extends to described substrate at least from described second upper surface of described first conductive type semiconductor layer lower surface.
2. luminescent device according to claim 1, also be included at least one first semiconductor layer between described first conductive type semiconductor layer and the described substrate, wherein, described second upper surface of described first conductive type semiconductor layer is formed by the ledge surface of at least one side surface that stems from described active layer.
3. luminescent device according to claim 1, wherein, described first electrode is formed a plurality of, and wherein, the top of described at least a plurality of first electrodes is spaced apart each other.
4. luminescent device according to claim 1, wherein, the following width of described first electrode is equal to or greater than the last width of described first electrode.
5. luminescent device according to claim 3 also comprises first conductive layer, and described first conductive layer is used for making that the top of at least two first electrodes is connected with each other.
6. luminescent device according to claim 1, wherein, described first electrode comprises structure vertical with respect to the lower surface of described first conductive type semiconductor layer or that tilt.
7. luminescent device according to claim 3, wherein, described second electrode is than the fringe region of the upper surface of more close described second conductive type semiconductor layer in central area of the described upper surface of close described second conductive type semiconductor layer.
8. luminescent device according to claim 3 also comprises second conductive layer, and described second conductive layer is used for making that the bottom of at least two first electrodes is connected with each other.
9. luminescent device according to claim 3, also be included in first upper surface of described first conductive type semiconductor layer and the inclined side surfaces between second upper surface, and first conductive layer, described first conductive layer is formed on second upper surface and described inclined side surfaces of described first conductive type semiconductor layer, and is connected to described first electrode.
10. luminescent device according to claim 1, wherein, the upper surface of described substrate and at least one in the lower surface comprise concaveconvex structure.
11. luminescent device according to claim 2, wherein, the part of described first semiconductor layer stretches out from the side surface of described first conductive type semiconductor layer, and the 3rd conductive layer is connected to the part of described first electrode by passing described first semiconductor layer.
12. luminescent device according to claim 1 also is included in the current extending between at least a portion of described second conductive type semiconductor layer and described second electrode.
13. luminescent device according to claim 3, wherein, described substrate comprises transmission material, and described first electrode is set to the side surface of the outside of described first conductive type semiconductor layer.
14. luminescent device according to claim 1, wherein, described second upper surface of described first conductive type semiconductor layer comprises the Ga-face.
15. luminescent device according to claim 1, wherein, described second electrode comprises at least one pad, and has from continuous or discrete annular of described pad branch.
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