CN102222601A - Method for enhancing sharpness of wafer ID - Google Patents
Method for enhancing sharpness of wafer ID Download PDFInfo
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- CN102222601A CN102222601A CN 201010154722 CN201010154722A CN102222601A CN 102222601 A CN102222601 A CN 102222601A CN 201010154722 CN201010154722 CN 201010154722 CN 201010154722 A CN201010154722 A CN 201010154722A CN 102222601 A CN102222601 A CN 102222601A
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- identification code
- passivation layer
- wafer identification
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- aluminium film
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Abstract
A method for enhancing sharpness of a wafer ID comprises the following steps: providing a wafer, wherein a surface of the wafer is covered with a passivation layers one; forming an aluminum coating on the passivation layers one; etching the aluminum coating and reserving the aluminum coating in a shielding area, wherein the shielding area is corresponding to a mark position of the wafer ID. In the method of the invention, the aluminum coating of the shielding area is remained on the passivation layers one. Because of opacity of the aluminum, graphics of semiconductor devices under the shielding area is not blended with the wafer ID in the shielding area. Therefore, the sharpness of the wafer ID is high.
Description
Technical field
The present invention relates to semiconductor applications, particularly strengthen the method for wafer identification code definition.
Background technology
Wafer identification code (wafer ID) is marked on each wafer, can be used to distinguish each batch wafer.Common, the wafer identification code can be formed on the outer peripheral areas of wafer prior to semiconductor device, also can be formed on the outer peripheral areas of wafer after forming semiconductor device.The wafer identification code is prior to the shortcoming that semiconductor device is formed on the outer peripheral areas of wafer: some layer covering of the composition semiconductor device that the wafer identification code can be formed by subsequent technique, thus the wafer identification code can't be identified.The wafer identification code is formed on the shortcoming that the outer peripheral areas of wafer has avoided the wafer identification code to be covered by semiconductor device after forming semiconductor device, this kind mode usually is applied in the technology of 40 nanometers, 45 nanometers and 90 nanometers.
In the technology of 40 nanometers and 45 nanometers, the wafer identification code forms usually in the following way: be formed on the device area of wafer at semiconductor device after, on described wafer, form first passivation layer that covers described semiconductor device, first passivation layer is carried out photoetching (comprise exposure, develop) handle, in the process of photoetching treatment, to also carrying out exposure-processed with the corresponding zone of described outer peripheral areas on first passivation layer, then, on first passivation layer, form the aluminium film, and etching aluminium film forms the aluminum pad that connects semiconductor device, when etching aluminium film, aluminium film corresponding with described outer peripheral areas on the aluminium film also is etched away, on the aluminium film, form second passivation layer that covers described aluminium film, marking wafer identification code on second passivation layer.In the aforesaid way, because in forming the semiconductor device process before, crystal column surface is heated evenly and guarantees the consistency of performance of semiconductor device when guaranteeing annealing operation, forming the service area of semiconductor device and the layer of gate regions must cover the whole surface of wafer and can form figure at whole crystal column surface, because first passivation layer and second passivation layer are transparent, therefore, the figure that the wafer identification code can and be formed at service area, gate regions mixes, thereby, make the definition step-down of wafer identification code.In addition, because the mark position area occupied of wafer identification code is bigger, therefore, the figure that is positioned at each semiconductor device of device area also may mix with the wafer identification code, makes that also the definition of wafer identification code is low.
The problem that wafer identification code definition is low also is present in the technology of 90 nanometers, and 90 nanometer technologies generally include FEOL and last part technology, and FEOL described herein and last part technology are to form metal level as separation.In 90 nanometer technologies, the wafer identification code is marked on second passivation layer, the concrete grammar of marking wafer identification code is: carrying out exposure-processed and etching away the corresponding aluminium film and first passivation layer with the mark position corresponding position of described wafer identification code on first passivation layer He on the aluminium film, on the aluminium film, form second passivation layer, and in the mark position marking wafer identification code of the wafer identification code of second passivation layer.In this kind mode, the figure of the service area of the semiconductor device that forms in FEOL and gate regions layer can make that still the definition of wafer identification code is low.
In addition, can also be about the correlation technique of marking wafer identification code referring to No. 02106277.3, Chinese patent application.
Summary of the invention
The technical problem that the present invention solves is the low problem of wafer identification code definition.
In order to address the above problem, the invention provides a kind of method that strengthens wafer identification code definition, this method comprises the steps: to provide surface coverage that the wafer of first passivation layer is arranged; On described first passivation layer, form the aluminium film; The described aluminium film of etching, the aluminium film of reservation blocked area, described blocked area is the zone corresponding with the mark position of wafer identification code.
Alternatively, the area of described blocked area equals the area of the mark position of wafer identification code at least.
Alternatively, described first passivation layer is silicon dioxide layer or silicon nitride layer.
Alternatively, the described aluminium film of described etching, the aluminium film that keeps described blocked area comprises: form photoresist layer on described aluminium film, the photoresist outside the described blocked area is exposed, develops, then the described aluminium film of etching.
Alternatively, described method also comprises: at described blocked area marking wafer identification code.
Alternatively, described method also is included in and forms second passivation layer on the described aluminium film.
Alternatively, described second passivation layer is a silicon nitride layer.
Alternatively, described method also comprises described second passivation layer of etching, keeps the second passivation layer zone corresponding with described blocked area, at the second passivation layer zone marker wafer identification code corresponding with described blocked area.
Compared with prior art, the invention has the beneficial effects as follows:
1, the aluminium film of blocked area of the present invention is stayed on first passivation layer, because the opacity of aluminium, the figure that is positioned at the semiconductor device under the blocked area can or not be positioned at second passivation layer with the wafer identification code that is positioned at the blocked area and mix corresponding to the wafer identification code of blocked area, thereby, the definition height of wafer identification code.
2,, like this, can avoid when etching forms aluminum pad and blocked area, producing the electric arc defective because the blocked area is coated with photoresist layer.
3, owing to be formed with second passivation layer, like this, not only protection is positioned at the wafer identification code of blocked area, and, can protect the semiconductor device on aluminium film and the wafer.
Description of drawings
Fig. 1 is the flow chart of first embodiment of the present invention's method of strengthening wafer identification code definition;
Fig. 2 is the crystal circle structure schematic diagram of the embodiment of the invention;
Fig. 3 to Fig. 7 is the A-A directional profile structural representation of the wafer of each step in the first embodiment of the invention along Fig. 2;
Fig. 8 is the present invention forms second passivation layer in first embodiment a schematic diagram;
Fig. 9 is the flow chart of second embodiment of the present invention's method of strengthening wafer identification code definition;
Figure 10 is the wafer cross-sectional view of the step S24 of described second embodiment of Fig. 9.
Embodiment
The present inventor is in the process of marking wafer identification code, discovery is in the technology of 40 nanometers and 45 nanometers, because first passivation layer and second passivation layer that are formed on the semiconductor device are transparent, can make form the figure of service area, gate regions of semiconductor device or figure and the wafer identification code that is positioned at each semiconductor device of device area and mix, make that the definition of wafer identification code is low.In addition, in the FEOL of 90 nanometer technologies, though the zone of the home position of the corresponding wafer identification code of first passivation layer is etched, because second passivation layer is transparent, the service area of the semiconductor device below it and the figure of gate regions can make that still the definition of wafer identification code is low.
For this reason, the present inventor provides a kind of method that strengthens wafer identification code definition, and as shown in Figure 1, this method comprises:
S11: provide surface coverage that the wafer of first passivation layer is arranged;
S12: on described first passivation layer, form the aluminium film;
S13: the described aluminium film of etching, the aluminium film of reservation blocked area, described blocked area is the zone corresponding with the mark position of wafer identification code.
Below in conjunction with accompanying drawing above-mentioned execution mode is described in detail.
As shown in Figure 1, execution in step S11, the wafer 1 that provides surface coverage that first passivation layer 2 is arranged.
In this step, as shown in Figures 2 and 3, described wafer 1 comprises outer peripheral areas 11 and device area, and outer peripheral areas 11 is the zones beyond the device area, and device area is used to form semiconductor device 12.
See also Fig. 4, be coated with first passivation layer 2 on the surface of described wafer 1.First passivation layer 2 (passivation layers one) is positioned at semiconductor device on the wafer 1 in order to protection, such as, this first passivation layer 2 can be silicon dioxide layer (SiO
2) or silicon nitride layer (Si
3N
4).When this first passivation layer 2 is silicon dioxide layer, can adopt aumospheric pressure cvd (APCVD) method that silane and oxygen are generated silicon dioxide layer by the oxidation reaction deposit, deposit becomes silicon dioxide layer to method by oxidation reaction with oxygen with silane perhaps to adopt low-pressure chemical vapor deposition (LPCVD perhaps is referred to as low pressure chemical vapor deposition) down at lower temperature (about 450 ℃).When this first passivation layer 2 is silicon nitride layer, can adopt low-pressure chemical vapor deposition with dichloro-dihydro silicon (SiCl
2H
2) and ammonia (NH
3) reaction and deposit becomes silicon nitride layer.
See also Fig. 5, after forming first passivation layer 2, on this first passivation layer 2, coat photoresist (photoresist), such as, adopt spin coating photoresist equipment to be coated with the above photoresist, and adopt the crystal round fringes particle to remove mode (EBR, also be referred to as edge bead remove) remove the photoresist at first passivation layer, 2 edges on the wafer 1, then, the figure on the mask of making is in advance aimed at wafer 1, then the photoresist on first passivation layer 2 is exposed; Then, the photosensitive area with the described photoresist of developing solution dissolution develops; Then, the described developing regional of etching and exposing needs the semiconductor device 12A that is connected with external devices in the described semiconductor device 12, do not need the semiconductor device 12B that is connected with external devices to be covered removal photoresist etching is finished after by first passivation layer 2.In this step, described first passivation layer 2 of etching can adopt this area mode commonly used.
Please in conjunction with consulting Fig. 1, Fig. 5 and Fig. 6, execution in step S12 forms aluminium film 3 on described first passivation layer 2.
In this step, aluminium film 3 can adopt magnetron sputtering, pulsed laser deposition, metal organic chemical vapor deposition or chemical vapour deposition (CVD) to form on first passivation layer 2, and on the aluminium film 3 with described outer peripheral areas 11 corresponding positions define a blocked area 31, the particular location of this blocked area 31 is by the mark position decision of wafer identification code in the subsequent technique, the position of this blocked area 31 overlaps with the position of wafer identification code mark at least, and the area of this blocked area 31 equals the area of the mark position of wafer identification code at least.
Please in conjunction with consulting Fig. 1, Fig. 6 and Fig. 7, execution in step S13, the described aluminium film 3 of etching, the aluminium film of reservation blocked area 31.
In this step, described blocked area 31 is the defined zone corresponding with the mark position of wafer identification code among the step S12.Be specially: on described aluminium film 3, coat photoresist, and photoresist is exposed, especially, and when the photoresist on the aluminium film 3 is exposed, the photoresist of the described blocked area 31 of not exposing, this advantage illustrates at subsequent step; Then, fall the photoresist of exposure and develop with developing solution dissolution, the described aluminium film 3 of etching then, such as, can adopt the described aluminium film 3 of chlorine-based gas etching, after the etching, the aluminium film 3 of blocked area 31 is retained on first passivation layer 2, other regional aluminium films 3 form patterns and as the aluminum pad 32 that is connected with corresponding semiconductor device 12A, before the described aluminium film 3 of etching, owing to the photoresist of described blocked area 31 is not exposed and still covers on the blocked area 31, like this, produce the electric arc defective when avoiding etching aluminium film 3, because blocked area 31 is used for shielding patterns, area equals the area of the mark position of wafer identification code at least, area is bigger, if the blocked area do not blocked by photoresist, when etching aluminium film 3, because the area of blocked area 31 is bigger, the gas atom of etching aluminium film 3 is easy to and blocked area 31 collisions, and produces electric arc, and such electric arc damages semiconductor device 12 easily.After etching was finished, described blocked area 31 was the mark position of wafer identification code, and the marking wafer identification code gets final product on this blocked area 31.
In this way,,, form pattern on each floor of semiconductor device 12 and be blocked and distinguish 31 and block, can not mix with the wafer identification code based on the opacity of aluminium film 3 because blocked area 31 is made up of aluminium film 3, thereby, the definition height of wafer identification code.
See also Fig. 8; as improvement; in order further to protect semiconductor device 12 and the aluminium film 3 on the semiconductor; can also on described aluminium film 3, form second passivation layer 4; this second passivation layer 4 can be silicon nitride layer; then, photoetching successively, described second passivation layer 4 of etching and expose described aluminum pad 32.After forming second passivation layer 4, can also protect the wafer identification code of blocked area 31.
See also Fig. 9, the present invention also provides another to strengthen the method for wafer identification code definition, and this method comprises:
S21: provide surface coverage that the wafer of first passivation layer is arranged;
S22: on described first passivation layer, form the aluminium film;
S23: the described aluminium film of etching, the aluminium film of reservation blocked area, described blocked area is the zone corresponding with the mark position of wafer identification code;
S24: form second passivation layer on described aluminium film, described second passivation layer of etching keeps the second passivation layer zone corresponding with described blocked area.
In this embodiment, step S21 and step S22 and the first embodiment step S11 and S12 are similar, do not repeat them here, the step S13 of the step S23 and first embodiment is similar, the difference of this step S23 and step S13 is: described blocked area 31 is not used as the mark position of wafer identification code, only is used for blocking figure.
See also Figure 10, describe step S24 in detail: form second passivation layer 4 on described aluminium film, described second passivation layer 4 of etching keeps the second passivation layer zone 41 corresponding with described blocked area 31.
In this step, second passivation layer 4 is generally silicon nitride layer, because silicon nitride layer can suppress the diffusion of impurity and moisture well, described silicon nitride layer can adopt the method for LPVCD to be deposited on the described aluminium film 3, adopt LPVCD deposit silicon nitride on aluminium film 3 can adopt existing technology, do not repeat them here this technology, behind deposit second passivation layer 4, define on this second passivation layer 4 and the 31 corresponding second passivation layer zones 41, described blocked area, this second passivation layer zone 41 is the mark position of marking wafer identification code in the subsequent technique; Then, on second passivation layer 4, coat photoresist, photoresist is exposed,, the photoresist in the second passivation layer zone 41 is not exposed, behind the resist exposure photoresist is developed in when exposure; Then, described second passivation layer 4 of etching exposes described aluminum pad 32 and stays second passivation layer zone, 41 back removal photoresists; At last, the second passivation layer zone 41 is as the mark position of wafer identification code, in described second passivation layer zone 41 marking wafer identification codes.
In a second embodiment, when exposure not to the resist exposure in the second passivation layer zone 41, like this, when etching, the second passivation layer zone 41 can not stay pattern, and owing to the opacity of aluminium film 3, the pattern on each layer of forming semiconductor device 12 can be blocked in blocked area 31 again, so, wafer identification code definition height.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (8)
1. a method that strengthens wafer identification code definition is characterized in that, comprises the steps:
Provide surface coverage that the wafer of first passivation layer is arranged;
On described first passivation layer, form the aluminium film;
The described aluminium film of etching, the aluminium film of reservation blocked area, described blocked area is the zone corresponding with the mark position of wafer identification code.
2. the method for enhancing wafer identification code definition as claimed in claim 1 is characterized in that the area of described blocked area equals the area of the mark position of wafer identification code at least.
3. the method for enhancing wafer identification code definition as claimed in claim 1 is characterized in that described first passivation layer is silicon dioxide layer or silicon nitride layer.
4. the method for enhancing wafer identification code definition as claimed in claim 1, it is characterized in that, the described aluminium film of described etching, the aluminium film that keeps described blocked area comprises: form photoresist layer on described aluminium film, photoresist outside the described blocked area is exposed, develops, then the described aluminium film of etching.
5. the method for enhancing wafer identification code definition as claimed in claim 1 is characterized in that, also comprises: at described blocked area marking wafer identification code.
6. the method for enhancing wafer identification code definition as claimed in claim 1 is characterized in that, also is included in and forms second passivation layer on the described aluminium film.
7. the method for enhancing wafer identification code definition as claimed in claim 6 is characterized in that described second passivation layer is a silicon nitride layer.
8. the method for enhancing wafer identification code definition as claimed in claim 6, it is characterized in that, also comprise: described second passivation layer of etching keeps the second passivation layer zone corresponding with described blocked area, at the second passivation layer zone marker wafer identification code corresponding with described blocked area.
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| CN102222601B CN102222601B (en) | 2016-03-16 |
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| CN103107097A (en) * | 2011-11-11 | 2013-05-15 | 无锡华润上华科技有限公司 | Chip manufacturing method of multi-project wafer and outer-layer metal mask plate of multi-project wafer |
| CN105427752A (en) * | 2015-11-03 | 2016-03-23 | 景旺电子科技(龙川)有限公司 | Synchronous marking method for LEDs of multiple BINs |
| CN110335811A (en) * | 2019-07-09 | 2019-10-15 | 山东宝乘电子有限公司 | A kind of deposition method of oxygen-containing polysilicon passivating film and chip with the passivating film |
| CN110390325A (en) * | 2019-07-30 | 2019-10-29 | 深圳市技美智能自动化有限公司 | A kind of network centralization OCR identifying system and method |
| CN111192833A (en) * | 2018-12-12 | 2020-05-22 | 深圳方正微电子有限公司 | Silicon carbide wafer and method for producing same |
| CN113745198A (en) * | 2021-07-23 | 2021-12-03 | 上海积塔半导体有限公司 | Wafer structure and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103107097A (en) * | 2011-11-11 | 2013-05-15 | 无锡华润上华科技有限公司 | Chip manufacturing method of multi-project wafer and outer-layer metal mask plate of multi-project wafer |
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| CN111192833A (en) * | 2018-12-12 | 2020-05-22 | 深圳方正微电子有限公司 | Silicon carbide wafer and method for producing same |
| CN110335811A (en) * | 2019-07-09 | 2019-10-15 | 山东宝乘电子有限公司 | A kind of deposition method of oxygen-containing polysilicon passivating film and chip with the passivating film |
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| CN110390325A (en) * | 2019-07-30 | 2019-10-29 | 深圳市技美智能自动化有限公司 | A kind of network centralization OCR identifying system and method |
| CN110390325B (en) * | 2019-07-30 | 2021-07-02 | 深圳市静尚云科技有限公司 | Network centralized OCR recognition system and method |
| CN113745198A (en) * | 2021-07-23 | 2021-12-03 | 上海积塔半导体有限公司 | Wafer structure and manufacturing method thereof |
| CN113745198B (en) * | 2021-07-23 | 2024-02-02 | 上海积塔半导体有限公司 | Wafer structure and manufacturing method thereof |
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