CN103107097B - The manufacturing method of chip of MPW - Google Patents
The manufacturing method of chip of MPW Download PDFInfo
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- CN103107097B CN103107097B CN201110358724.XA CN201110358724A CN103107097B CN 103107097 B CN103107097 B CN 103107097B CN 201110358724 A CN201110358724 A CN 201110358724A CN 103107097 B CN103107097 B CN 103107097B
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Abstract
The present invention discloses a kind of manufacturing method of chip of MPW, comprise the following steps: on the mask plate corresponding with the outermost metal of objective chip, set up barrier metal figure, described barrier metal figure corresponds to the outer chip of the processing procedure belonging to a block with objective chip together; The mask plate having set up barrier metal figure described in utilization carries out graphical treatment to the outermost metal on MPW; Deposit insulating medium layer and passivation layer in outermost metal after carrying out graphical treatment; Utilize the PAD layer mask plate corresponding to described mask plate, graphical treatment is carried out to described insulating medium layer and passivation layer, form PAD.And a kind of outer layer metal mask plate being suitable for the MPW of said method.After the insulating medium layer of the outer chip surface of processing procedure and passivation layer are patterned immediately, the contact hole of formation can on barrier metal layer, and the steps such as etching, cleaning can not cause defect on the outer chip of processing procedure.
Description
[technical field]
The present invention relates to MPW manufacture, especially relate to a kind of manufacturing method of chip of MPW and the outer layer metal mask plate of MPW.
[background technology]
In MPW processing procedure, each wafer comprises multiple different chip, and MPW is the product of different processing procedure is save the wafer that development cost shares a set of mask plate.
MPW is owing to having multiple different chip information, and outermost metal is usually designed to different thickness and adopts different mask plates to form circuitous pattern.Based on this, in the process of formation PAD (pad) subsequently, contact hole will aim at the outermost metal figure generated by different mask plate just must adopt different PAD mask plates, otherwise use single PAD mask plate (for saving cost, this single PAD mask plate itself is for individual event order wafer) contact hole probably can be made to be formed at other chip areas, and extending to the position not having metal level, so corresponding with this contact hole position can produce defect in the process forming contact hole.
[summary of the invention]
Based on this, be necessary to provide a kind of manufacturing method of chip using the MPW of single PAD mask plate.
A manufacturing method of chip for MPW, comprises the following steps: on the mask plate corresponding with the outermost metal of objective chip, set up barrier metal figure, and described barrier metal figure corresponds to the outer chip of the processing procedure belonging to a block with objective chip together; The mask plate having set up barrier metal figure described in utilization carries out graphical treatment to the outermost metal on MPW; Deposit insulating medium layer and passivation layer in outermost metal after carrying out graphical treatment; Utilize the PAD layer mask plate corresponding to described mask plate, graphical treatment is carried out to described insulating medium layer and passivation layer, form PAD.
Preferably, described barrier metal figure is for the formation of the barrier metal layer of monoblock.
Preferably, described barrier metal figure is for the formation of the multiple metal derbies corresponding with the contact hole that PAD layer mask plate is formed.
In addition, a kind of outer layer metal mask plate of the MPW that can coordinate with single PAD mask plate is also provided.
A kind of outer layer metal mask plate of MPW, corresponding with the outermost metal on MPW, which is provided with the targeted graphical corresponding with objective chip, it is characterized in that, be also provided with the barrier metal figure corresponding to the outer chip of the processing procedure belonging to a block with objective chip together.
Preferably, described barrier metal figure is for the formation of the barrier metal layer of monoblock.
Preferably, described barrier metal figure is for the formation of the multiple metal derbies corresponding with the contact hole that PAD layer mask plate is formed.
The manufacturing method of chip of above-mentioned MPW and the outermost metal mask plate of MPW, because PAD layer mask plate is corresponding with the mask plate of the outermost metal of objective chip, therefore can form correct PAD region in objective chip.And after the insulating medium layer of the outer chip surface of processing procedure and passivation layer be patterned immediately, the contact hole of formation can on barrier metal layer.Therefore in the process forming contact hole, due to the existence of barrier metal layer, the steps such as etching, cleaning can not cause defect on the outer chip of processing procedure.Therefore, even if use single PAD mask plate also not have problem.
[accompanying drawing explanation]
Fig. 1 is the manufacturing method of chip flow chart of the MPW of an embodiment;
Fig. 2 is MPW schematic diagram;
Fig. 3 is the close-up schematic view of block;
Fig. 4 is the schematic diagram after the block in Fig. 3 being formed PAD contact hole.
[embodiment]
As shown in Figure 1, be the manufacturing method of chip flow chart of MPW of an embodiment.The method comprises the steps:
S110: set up barrier metal figure on the mask plate corresponding with the outermost metal of objective chip, described barrier metal figure corresponds to the outer chip of the processing procedure belonging to a block with objective chip together.As shown in Figure 2, be MPW schematic diagram.A block 10 of MPW comprises multi-chip information.As shown in Figure 3, be the partial enlarged drawing of block 10, this block 10 comprises objective chip 102 and the outer chip 104 of the processing procedure adjacent with objective chip 102.Objective chip 102 refers to the chip planning in this processing procedure to obtain, and is formed at the target area on wafer.Corresponding with this target area have for patterned each layer mask plate.The mask plate corresponding with the outermost metal of objective chip can form circuitous pattern in outermost metal.The outer chip 104 of processing procedure refers in MPW, does not carry out the chip of the technological operation of being correlated with in this processing procedure, and the outer chip of processing procedure belongs to different projects from objective chip.
On the mask plate corresponding with the outermost metal of objective chip 102, be provided with targeted graphical, for outermost metal is graphical.In addition, this mask plate is also provided with barrier metal figure, this barrier metal figure corresponds to the outer chip 104 of processing procedure, for forming barrier metal layer on the outer chip 104 of processing procedure.This barrier metal figure is preferred for the barrier metal layer forming monoblock.
S120: the mask plate having set up barrier metal figure described in utilization carries out graphical treatment to the outermost metal on MPW.This graphical treatment makes objective chip 102 to be formed required circuit connection figure 202 on the one hand, defines barrier metal layer 204 on the other hand on the outer chip 104 of processing procedure.Barrier metal layer 204 can be the metal level of monoblock, also can be the multiple metal derbies corresponding with the contact hole that PAD layer mask plate is formed, and only contact hole need be blocked.
S130: deposit insulating medium layer and passivation layer in the outermost metal after carrying out graphical treatment.This step is conventional steps after metallization, is not repeated herein.
S140: utilize the PAD layer mask plate corresponding to described mask plate, carry out graphical treatment to described insulating medium layer and passivation layer, forms PAD.After graphical treatment, insulating medium layer and passivation layer form contact hole, exposed portion outermost metal, form PAD.As shown in Figure 4, circuit connection figure 202 is touched the part exposed in hole 302 and forms PAD.Barrier metal layer 204 is touched the part exposed in hole 304 can stop outside destruction.
Because this PAD layer mask plate is corresponding with the mask plate of the outermost metal of objective chip 102, therefore correct PAD region can be formed in objective chip 102.And after the insulating medium layer on outer chip 104 surface of processing procedure and passivation layer be patterned immediately, the contact hole of formation can on barrier metal layer.Therefore in the process forming contact hole, due to the existence of barrier metal layer, the steps such as etching, cleaning can not cause defect on the outer chip 104 of processing procedure.
In addition, a kind of outermost metal mask plate of MPW is also provided.This mask plate is corresponding with the outermost metal on MPW, which is provided with the targeted graphical corresponding with objective chip, is also provided with the barrier metal figure corresponding to the outer chip of the processing procedure adjacent with objective chip.
Objective chip refers to the chip planning in this processing procedure to obtain, and is formed at the target area on wafer.Corresponding with this target area have for patterned each layer mask plate.The mask plate corresponding with the outermost metal of objective chip can form circuitous pattern in outermost metal.The outer chip of processing procedure refers in MPW, does not carry out the chip of the technological operation of being correlated with in this processing procedure, and the outer chip of processing procedure belongs to different projects from objective chip.
On the mask plate corresponding with the outermost metal of objective chip, be provided with targeted graphical, for outermost metal is graphical.In addition, this mask plate is also provided with barrier metal figure, this barrier metal figure corresponds to the outer chip of processing procedure, for forming barrier metal layer on the outer chip of processing procedure.This barrier metal figure is preferred for the barrier metal layer forming monoblock.
The mask plate of above-mentioned outermost metal can form barrier metal layer on the outer chip of processing procedure, therefore can avoid the destruction using single PAD layer mask plate to the outer chip of processing procedure.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (3)
1. a manufacturing method of chip for MPW, is characterized in that, comprises the following steps:
The mask plate corresponding with the outermost metal of objective chip is set up barrier metal figure, and described barrier metal figure corresponds to the outer chip of the processing procedure belonging to a block with objective chip together; The mask plate corresponding with the outermost metal of objective chip forms circuitous pattern in outermost metal;
The mask plate having set up described barrier metal figure is utilized to carry out graphical treatment to the outermost metal on MPW;
Deposit insulating medium layer and passivation layer in outermost metal after carrying out graphical treatment;
Utilize the pad layer mask plate having set up the mask plate of described barrier metal figure described in corresponding to, graphical treatment is carried out to described insulating medium layer and passivation layer, form pad.
2. the manufacturing method of chip of MPW as claimed in claim 1, it is characterized in that, described barrier metal figure is for the formation of the barrier metal layer of monoblock.
3. the manufacturing method of chip of MPW as claimed in claim 1, it is characterized in that, described barrier metal figure is for the formation of the multiple metal derbies corresponding with the contact hole that pad layer mask plate is formed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110358724.XA CN103107097B (en) | 2011-11-11 | 2011-11-11 | The manufacturing method of chip of MPW |
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| CN201110358724.XA CN103107097B (en) | 2011-11-11 | 2011-11-11 | The manufacturing method of chip of MPW |
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| CN103107097A CN103107097A (en) | 2013-05-15 |
| CN103107097B true CN103107097B (en) | 2016-03-09 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038435A (en) * | 2006-03-17 | 2007-09-19 | 蔡士成 | Wafer lithography mask, its manufacturing method and wafer photolithography method |
| CN102222601A (en) * | 2010-04-14 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method for enhancing sharpness of wafer ID |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010033975A1 (en) * | 1999-05-19 | 2001-10-25 | Wen-Jye Chung | Yield of dies by adding dummy pattern on open area of multi-project mask |
| US7521287B2 (en) * | 2006-11-20 | 2009-04-21 | International Business Machines Corporation | Wire and solder bond forming methods |
| JP5211635B2 (en) * | 2007-10-25 | 2013-06-12 | 富士通セミコンダクター株式会社 | Dummy chip exposure method and semiconductor integrated circuit device manufacturing method |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101038435A (en) * | 2006-03-17 | 2007-09-19 | 蔡士成 | Wafer lithography mask, its manufacturing method and wafer photolithography method |
| CN102222601A (en) * | 2010-04-14 | 2011-10-19 | 中芯国际集成电路制造(上海)有限公司 | Method for enhancing sharpness of wafer ID |
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Effective date of registration: 20180625 Address after: 214135 -6, Linghu Road, Taihu international science and Technology Park, Wuxi, Jiangsu, 180 Patentee after: WUXI DISI MICROELECTRONIC CO., LTD. Address before: 214028 No. 8 Xinzhou Road, national hi tech Industrial Development Zone, Wuxi, Jiangsu Patentee before: Wuxi Huarun Shanghua Technology Co., Ltd. |
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