CN102214686B - Cathode patterns of electric semiconductor device and patterned arrangement method of cathode fingers thereof - Google Patents
Cathode patterns of electric semiconductor device and patterned arrangement method of cathode fingers thereof Download PDFInfo
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Abstract
The invention discloses cathode patterns of an electric semiconductor device and a patterned arrangement method of cathode fingers thereof, which are widely applied in the design of cathode patterns in an electric semiconductor, an electric electronic device, an all-controlled thyristor and the like. The cathode patterns comprises equant sector areas and concentric rings which are divided with a circle centre as an axle; the intersecting places of the sector areas and the concentric rings are pattern units; fingers distributed in the sector areas and located in one ring are arranged along a circle arc of the ring; the outer edge lines of each circle of fingers are circular arcs; and the directions of the fingers are all parallel to the centre lines of the sector areas; and gate pole fast channels are left between adjacent two sector areas. The cathode patterns are transferred to the surfaces of chips by photoetching the designed photomask plates to finish the final manufacturing. According to the cathode patterns and the patterned arrangement method of the cathode fingers thereof, the utilization rate of the effective areas of the chips is increased; the opening/closing uniformity of each finger is improved; the balancing of the opening/closing difference of the fingers, caused by the distance from gate pole electrodes is facilitated; and the machining formation is conveniently realized.
Description
Technical field
The present invention relates to power semiconductor and the method for designing thereof of field of semiconductor devices, especially a kind of cathode pattern and negative electrode sliver figure arrangement method thereof that is applied to electric semiconductor, power electronic device, full-control type thyristor etc.
Background technology
The cathode pattern design is the basic link of all kinds of electronic device design, and the full-control type thyristor is even more important.The cathode pattern of full-control type thyristor and gate pole figure are complementary, and directly affect the dynamic parameter of device, so the graphic designs of full-control type thyristor must be prudent.Generally after the balancing device parameters, design roughly figure, determine final graphics in conjunction with the graphic characteristics that designer's Aesthetic Style and enterprise acts on.The figure that designs take mask plate as carrier, is transferred to chip surface by photoetching process again, and marks off corresponding gate pole and negative electrode.
Such as IGCT(Intergrated Gate Commutated Thyristors, integrated gate commutated thyristor) and GTO(Gate Turn-Off Thyristor, turn-off thyristor) this class full-control type electric semiconductor, negative electrode is usually arranged by many tiny slivers and is formed, the gate pole district institute that is communicated with by integral body on every side around, this is a kind of typical structural design, has fully satisfied the Static and dynamic performance requirement of device, and the concrete arrangement mode of its gate electrode design and sliver is varied.As depicted in figs. 1 and 2, the cathode pattern design mainly comprises: the steps such as sector division, annulus division, sliver layout, gate pole setting, lithography process and figure transfer.Wherein, it mainly is that disc radially is divided into N fan section that the sector is divided, and N is called sector number.It mainly is that disc is divided into M wide annular concentric zone that annulus is divided, and M is called the annulus number.The zone that sector and annulus intersect is the fundamental figure unit.In the step of cathode pattern design, a most important step is exactly that sliver is arranged.Present existing sliver arrangement mode has three classes:
1, even rectanglar arrangement: as shown in Figure 3, the sliver size is identical, and direction is consistent, branch's proper alignment.On the whole circular chip surface is divided into several rectangles, graphic structure is simple.But the area utilization of chip is not high, can not take full advantage of with position, circular curve boundary, especially is not suitable for using the annular door electrode structure, so only at the early stage device that is used for the low-side current capacity of full-control type thyristor exploitation.
2, evenly circumference is arranged: as shown in Figure 4, the sliver size is identical, radially towards, concentric circumference is arranged.Figure is even on the whole, simple for structure, distribute regular, so use wider.But the sliver radial distribution, each concentric circles girth does not wait, and sliver can not be corresponding one by one, and increase with the place radius of a circle, and radially the angle back gauge is constantly amplified, sliver gap approximate trapezoid, it is different that each encloses sliver gap shape area, and the chip area utilance is not high.
3, subregion is compound arranges: as shown in Figure 5, the chip negative electrode is divided 16 fanned partitions take the center of circle as axle, sliver rectanglar arrangement in the subregion, and sliver is still arranged by circumference between each subregion.Figure is relatively regular on the whole, gate pole uniformity around the sliver in the subregion.But each subregion all has rectangle and the waste of circular arc boundary irregular area, reduced the utilance of chip area, and it is larger to increase waste with the figure radius, is not suitable for large diameter full-control type device.
As can be seen from above, three kinds of sliver arrangement modes all have pluses and minuses separately, therefore it is high with rate to develop a kind of chip area rate, is convenient to machine-shaping, and the semiconductor device cathode pattern that is applicable to various sizes and gate pole set-up mode becomes current problem demanding prompt solution.
Summary of the invention
The purpose of this invention is to provide a kind of power semiconductor device cathode pattern and negative electrode sliver figure arrangement method thereof, this cathode pattern and negative electrode sliver figure arrangement method thereof have improved the effective area utilance of chip, improved the uniformity that each sliver is opened/turn-offed, be conducive to the sliver that equilibrium distance gate electrode distance brings and open/turn-off difference, be convenient to machine-shaping.
The present invention specifically provides a kind of embodiment of power semiconductor device cathode pattern, a kind of power semiconductor device cathode pattern, comprise: five equilibrium sector and the donut divided as the center of circle take the center of the cathode plane of power semiconductor device, sector and donut intersection are graphic element, the sliver of negative electrode is sector circular arc arrangement, the sliver that is distributed in the sector and is positioned at same annulus is arranged along the circular arc of annulus, the outer edge of every circle sliver is circular arc, and sliver towards the center line that all is parallel to the sector, leave the quick passage of gate pole between two adjacent sectors.
As the further execution mode of a kind of power semiconductor device cathode pattern of the present invention, after the sector forms, according to the width that stays between adjacent two sectors, increase or do not increase a sliver, increase sliver and can better guarantee the effective usable floor area of negative electrode, guarantee simultaneously the whole uniformity of sliver.
As the further execution mode of a kind of power semiconductor device cathode pattern of the present invention, sector number is 4 ~ 64, and the annulus number is 1 ~ 16.The quantity of annulus is determined according to chip design diameter and sliver design size Auto-matching.
As the further execution mode of a kind of power semiconductor device cathode pattern of the present invention, sector number is 16.
As the further execution mode of a kind of power semiconductor device cathode pattern of the present invention, cathode pattern is applied to the full-control type semiconductor device.
As the further execution mode of a kind of power semiconductor device cathode pattern of the present invention, cathode pattern is applied to the multiple device of IGCT or GTO or contrary guide structure.
As the further execution mode of a kind of power semiconductor device cathode pattern of the present invention, the central area of cathode pattern or annular region or fringe region are provided with gate pole.
The present invention also provides a kind of embodiment of power semiconductor device negative electrode sliver figure arrangement method, and a kind of power semiconductor device negative electrode sliver figure arrangement method may further comprise the steps:
(A) center take the cathode plane of power semiconductor device is divided into the five equilibrium sector as the center of circle with the cathode plane of power semiconductor device;
(B) divide donut according to the length of sliver at the cathode plane of power semiconductor device;
(C) sliver is set in the sector, the sliver that is distributed in the sector and be positioned at same annulus is arranged along the circular arc of annulus so that the outer edge of every circle sliver is circular arc, and the sliver setting towards the center line that all is parallel to the sector;
(D) between two adjacent sectors, reserve the quick passage of gate pole;
(E) at central area or annular region or the edge rings region division gate pole of cathode plane;
(F) will process by photoetching process by the lithography mask version of above-mentioned steps design, designed cathode pattern be transferred to the surface of chip.
As the further execution mode of a kind of power semiconductor device negative electrode of the present invention sliver figure arrangement method, the quick passage of gate pole between adjacent two sectors inserts single sliver.
As the further execution mode of a kind of power semiconductor device negative electrode of the present invention sliver figure arrangement method, take the center of circle as axle the cathode plane of power semiconductor device is divided into 4 ~ 64 five equilibrium sectors; Cathode plane at power semiconductor device is divided into 1 ~ 16 donut.
By implementing a kind of power semiconductor device cathode pattern of the present invention and the described technical scheme of negative electrode sliver figure arrangement method embodiment thereof, can reach following technique effect:
1, sliver is arranged along circular arc in the graphic element, and direction is parallel, and the gate region around the sliver is equivalence fully, has improved the uniformity that each sliver is opened/turn-offed;
2, the sector circular arc is arranged pattern edge for circular, and is smooth regular, do not have the figure wedge angle, agrees with fully with the shape of chip own, guarantees convenience and the practicality of chip following process, need not special protection;
3, the same sliver number of turns, the chip diameter that takies is slightly little, has namely improved the effective area utilance of chip;
4, the radially quick passage of the gate pole between the sector is conducive to improve gate characteristics, and difference is opened/turn-offed to the sliver that equilibrium distance gate electrode distance is brought;
5, graphic element is conducive to the automatic characterization processes of sliver and sliver moulding process by the circle symmetry arrangement.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is that schematic diagram is divided in the sector that power semiconductor device negative electrode sliver figure is arranged;
Fig. 2 is that the annulus that power semiconductor device negative electrode sliver figure is arranged is divided schematic diagram;
Fig. 3 is the schematic diagram of the even rectanglar arrangement of power semiconductor device negative electrode sliver;
Fig. 4 is the schematic diagram that the even circumference of power semiconductor device negative electrode sliver is arranged;
Fig. 5 is the schematic diagram of the compound zoning arrangement of power semiconductor device negative electrode sliver;
Fig. 6 is the schematic diagram that a kind of embodiment of power semiconductor device cathode pattern of the present invention sector circular arc is arranged;
Fig. 7 is the sliver detailed schematic that a kind of embodiment of power semiconductor device cathode pattern of the present invention sector circular arc is arranged;
Fig. 8 is the sliver detailed schematic of the compound zoning arrangement of power semiconductor device negative electrode sliver;
Fig. 9 is the schematic diagram of a kind of embodiment of power semiconductor device cathode pattern of the present invention sector circular arc sliver and chip outer edge when arranging;
The schematic diagram of sliver and chip outer edge when Figure 10 is the compound zoning arrangement of a kind of embodiment of power semiconductor device cathode pattern of the present invention;
Figure 11 is the specific embodiment of power semiconductor device cathode pattern of the present invention when 16 sectors, 3 annulus are arranged;
Figure 12 is the specific embodiment of power semiconductor device cathode pattern of the present invention when 16 sectors, 5 annulus are arranged;
Figure 13 is the specific embodiment of power semiconductor device cathode pattern of the present invention when 16 sectors, 9 annulus are arranged;
Figure 14 is the specific embodiment of power semiconductor device cathode pattern of the present invention when 16 sectors, 10 annulus are arranged;
Among the figure, 1-sector, 2-graphic element, 3-annulus, the quick passage of 4-gate pole, 5-sliver, 6-central area, 7-fringe region, 8-annular region.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described.Obviously, described embodiment only is a part of embodiment of the present invention, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Embodiment as a kind of power semiconductor device cathode pattern of the present invention, power semiconductor device cathode pattern as shown in Figure 6 comprises five equilibrium sector 1 and the donut 3 of dividing as the center of circle take the center of the cathode plane of power semiconductor device, sector 1 is graphic element 2 with concentric annulus 3 intersections, the sliver 5 that is distributed in the sector 1 and is positioned at same annulus 3 is arranged along the circular arc of annulus, the outer edge of every circle sliver is circular arc, and sliver 5 towards the center line that all is parallel to sector 1.Sliver arrangement mode in such graphic element, so that fully equivalence of each graphic element on the same annulus, in the same sector, the graphic element area is increasing from inside to outside with the annulus position, the sliver number that can arrange is also more and more.Sliver in the graphic element is measure-alike, arranges along the annulus lower sideline, and direction all is parallel to graphic element center radial transmission line.
On the sliver of sector intersection is arranged, owing to sliver is arranged along graphic element center radial transmission line, in the angle zone that the sector intersection exists two graphic element slivers to form towards differing.This zone is the quick passage of gate pole radially, leaves the quick passage 4 of gate pole between two adjacent sectors, and is favourable to the gate current conducting.Simultaneously in order effectively to utilize cathode area, when the width of the quick passage 4 of gate pole between adjacent two sectors during greater than the width of single sliver 5, insert the single sliver of radially arranging 5 between adjacent two sectors.Number of sectors is 16, and the annulus number is 1 ~ 16, and the annulus number is relevant with the sliver size with the chip diameter, and the quantity of annulus is determined according to chip design diameter and sliver design size Auto-matching.This cathode pattern can be applied to the full-control type semiconductor device, especially the multiple device of IGCT or GTO or contrary guide structure.In the central area of cathode pattern or annular region or fringe region be provided with gate pole.
A kind of embodiment of power semiconductor device negative electrode sliver figure arrangement method may further comprise the steps:
(A) center take the cathode plane of power semiconductor device is divided into the five equilibrium sector as the center of circle with the cathode plane of power semiconductor device;
(B) divide donut according to the length of sliver at the cathode plane of power semiconductor device;
(C) sliver is set in the sector, the sliver that is distributed in the sector and be positioned at same annulus is arranged along the circular arc of annulus so that the outer edge of every circle sliver is circular arc, and the sliver setting towards the center line that all is parallel to the sector;
(D) between two adjacent sectors, reserve the quick passage of gate pole;
(E) at central area or annular region or the edge rings region division gate pole of cathode plane;
(F) will process by photoetching process by the lithography mask version of above-mentioned steps design, designed cathode pattern is transferred to the surface of chip, supporting other chip manufacture technique is finished the making of whole chip.
Can be further according to the width that leaves the quick passage 4 of gate pole between two sectors, the quick passage of gate pole between adjacent two sectors inserts single sliver.Insert single sliver and can guarantee better the effective usable floor area of negative electrode, guarantee simultaneously the whole uniformity of sliver.
Usually take the center of circle as axle the cathode plane of power semiconductor device is divided into 4 ~ 64 five equilibrium sectors; Cathode plane at power semiconductor device is divided into 1 ~ 16 donut.As a kind of better exemplary embodiment, the cathode plane of power semiconductor device is divided into the sector of 16 five equilibriums.
Its good response speed of opening of full-control type thyristor mainly determines by the gate pole figure, and the gate pole figure then is by negative electrode sliver rear formation of arranging.Negative electrode sliver sector circular arc arrange so that in the sector the outer gate structure of each sliver in full accord, be conducive to the retainer member dynamic homogeneity; Sector juncture area gate structure is slightly different, and sliver is arranged sparse a little, has so also formed the quick passage that the far-end gate electrode is opened/turn-offed, and is conducive to the difference that the far and near difference of equilibrium distance electrode is brought.
The even rectanglar arrangement of the comprehensive prior art of negative electrode sliver sector circular arc arrangement mode that the specific embodiment of the invention is described, even circumference are arranged, the advantage of compound zoning arrangement, the sector that circle is divided into five equilibrium, the inner sliver in sector is towards unanimously, be parallel to the sector center line, and arrange along circular arc with the circle sliver, insert single radially sliver according to size between the sector.The chip area utilance is high like this, and sliver is arranged regular, the sector between the sliver gate pole shape in full accord, the quick passage of formation gate current is conducive to the difference that equilibrium distance gate electrode distance is brought between the sector.The described negative electrode sliver of specific embodiment of the invention sector circular arc arrangement method is adapted to the full-control type power semiconductor devices such as all size, various types of IGCT or GTO, and the diameter of chip is generally 30mm ~ 150mm.
Arrange in the arrangement of gate electrode, gate electrode arranges unfettered, and center gate pole, annular gate pole or edge gate pole all can.The central area 6 of cathode plane has been shown, fringe region 7 among Fig. 6.Circle ring area 8 has been shown in Figure 13 and 14.
General small diameter chip adopts the center gate pole, and the larger diameter chip adopts annular gate pole, wherein:
Center gate pole: design a panel region leading-out exit utmost point electrode in chip cathode pattern center.Characteristic of Picture is: gate electrode is for circular, and extraction location is at the cathode pattern center, little (the about 0.5cm of contact area
2).Such design is so that gate electrode mechanical structure is simple, but lack of homogeneity is too concentrated, triggered to gate signal, only is fit to the device of current capacity low side.
Annular gate pole: design a circular annular region at chip cathode pattern medium position and draw gate electrode.Characteristic of Picture is: gate electrode is annular, and extraction location is at cathode pattern middle part, medium (the about 2.5cm of contact area
2).Such design gate signal bi-directional is conducive to improve uniformity, is applicable to the device of the middle and high end of current capacity, but the gate pole complicated in mechanical structure, and cathode electrode need be split as two parts.
Edge gate pole: design a circular annular region at chip cathode pattern marginal position and draw gate electrode.Characteristic of Picture is: gate electrode is annular, and its extraction location is peripheral in cathode pattern, large (the about 5cm of contact area
2).Such design is used for the full-control type device less, and gate signal is concentrated toward center position and transmitted, and triggers lack of homogeneity, the gate pole complicated in mechanical structure, and it is larger to consume the negative electrode effective area.
Gate pole application example centered by Figure 11, Figure 12 is applicable to minor diameter (IGCT of Φ 30～60mm), GTO device.Wherein, Figure 11 is the concrete application example that 16 sectors, 3 annulus are arranged; Figure 12 is the concrete application example that 16 sectors, 5 annulus are arranged.
Figure 13, Figure 14 are annular gate pole application example, are applicable to larger diameter (IGCT of Φ 60～100mm), GTO device.Wherein, Figure 13 is the concrete application example that 16 sectors, 9 annulus are arranged; Figure 14 is the concrete application example that 16 sectors, 10 annulus are arranged.
Sector circular arc arrangement method compound zoning arrangement method compared to prior art, its superiority major embodiment be in the following areas:
Such as A section and the B section of Fig. 7, and shown in Figure 9, and the outer edge of every circle sliver was circular arc when the sector circular arc was arranged, and adapted with chip form, was conducive to the part table moulding.And such as C section and the D section of Fig. 8, and the every circle sliver of compound zoning arrangement method outer edge shown in Figure 10 is 16 limit shapes, and 16 limit shapes and the chip form of outmost turns are not mated, and are unfavorable for device edge processing.In addition, the required chip diameter of the same sliver number of turns was obviously smaller when the sector circular arc was arranged, and the concrete technique effect that brings thus as described later.Onesize sliver is arranged by gap between same circle and is requiredly descended most diameter contrast such as following table:
Table 1: the sector circular arc is arranged and the required radius contrast of compound zoning arrangement
| The sliver number of turns | Compound zoning arrangement method cathode pattern effective diameter (mm) | The sector circular arc method cathode pattern effective diameter (mm) of arranging | The sector circular arc cathode pattern reduced value (mm) of arranging |
| First lap | 14.2088 | 14.0860 | 0.1228 |
| The second circle | 20.6764 | 20.4826 | 0.1938 |
| The 3rd circle | 27.1432 | 26.8860 | 0.2572 |
| The 4th circle | 33.6088 | 33.2860 | 0.3228 |
| The 5th circle | 40.2194 | 39.6860 | 0.5334 |
| The 6th circle | 57.3088 | 56.5648 | 0.7440 |
| The 7th circle | 63.9300 | 62.9650 | 0.9650 |
| The 8th circle | 70.3998 | 69.3650 | 1.0348 |
| The 9th circle | 76.8972 | 75.7650 | 1.1322 |
| The tenth circle | 83.4820 | 82.1650 | 1.3170 |
Remarks: sliver length 2.92mm has comprised center gate pole or the shared size of annular gate pole in the above-mentioned radius value.
Can be reached a conclusion by above list data: the sliver of the same number of turns of arranging, cathode pattern when design sector circular arc are arranged, and to take diameter than compound zoning arrangement little, effectively utilized valuable chip area.More space has been reserved in the table top moulding that can be simultaneously device, so that the optimised devices voltage parameter.If the sliver design number of turns is more, the sector circular arc is arranged and can be saved more diameters, and the area that has more more slivers of can arranging are with the current capacity of increase device.
With the comparison of arranging of the compound subregion sliver of prior art, circular arc the arrange advantage of figure and method and technology scheme thereof in the described negative electrode sliver of specific embodiment of the invention sector has:
1, the same sliver number of turns, the chip diameter that takies reduces, and has improved the effective area utilance of chip, and when the sliver design number of turns was more, the advantage of its high area utilization was more obvious;
2, sliver is arranged along circular arc in the graphic element, and direction is parallel, and the gate region around the sliver is equivalence fully, has improved the uniformity that each sliver is opened/turn-offed;
3, the radially quick passage of the gate pole between the sector is conducive to improve gate characteristics, and difference is opened/turn-offed to the sliver that equilibrium distance gate electrode distance is brought;
4, negative electrode sliver sector circular arc arrangement mode is applicable to the multiple gate pole arrangements such as center gate pole, annular gate pole and edge gate pole, has greatly improved the range of application of its cathode pattern;
5, the sector circular arc is arranged pattern edge for circular, and smooth regular, there is not the figure wedge angle in good looking appearance, agrees with fully with the shape of chip own, guarantees convenience and the practicality of chip following process.Graphic element is conducive to the automatic characterization processes of sliver and sliver moulding process by the circle symmetry arrangement.
The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Although the present invention discloses as above with preferred embodiment, yet is not to limit the present invention.Any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention, any simple modification of above embodiment being done according to technical spirit of the present invention, be equal to replacements, equivalence changes and modify, all still belong in the scope that technical solution of the present invention protects.
Claims (10)
1. power semiconductor device cathode pattern, comprise five equilibrium sector and the donut divided as the center of circle take the center of the cathode plane of power semiconductor device, sector and donut intersection are graphic element, it is characterized in that: the sliver of negative electrode is sector circular arc arrangement, the sliver that is distributed in the sector and is positioned at same annulus is arranged along the circular arc of annulus, the outer edge of every circle sliver is circular arc, and sliver towards the center line that all is parallel to the sector, leave the quick passage of gate pole between two adjacent sectors.
2. a kind of power semiconductor device cathode pattern according to claim 1, it is characterized in that: the quick passage of gate pole between described adjacent two sectors is provided with single sliver.
3. a kind of power semiconductor device cathode pattern according to claim 1 and 2, it is characterized in that: described sector number is 4 ~ 64, described annulus number is 1 ~ 16.
4. a kind of power semiconductor device cathode pattern according to claim 3, it is characterized in that: described sector number is 16.
5. a kind of power semiconductor device cathode pattern according to claim 4, it is characterized in that: described cathode pattern is applied to the full-control type semiconductor device.
6. a kind of power semiconductor device cathode pattern according to claim 5 is characterized in that: described cathode pattern is applied to the multiple device of IGCT or GTO or contrary guide structure.
7. a kind of power semiconductor device cathode pattern according to claim 6, it is characterized in that: the central area of described cathode pattern or annular region or fringe region are provided with gate pole.
8. one kind is carried out the method that negative electrode sliver figure is arranged to claim 1 or 2 described power semiconductor device cathode pattern, it is characterized in that described arrangement method may further comprise the steps:
(A) center take the cathode plane of power semiconductor device is divided into the five equilibrium sector as the center of circle with the cathode plane of power semiconductor device;
(B) divide donut according to the length of sliver at the cathode plane of power semiconductor device;
(C) sliver is set in the sector, the sliver that is distributed in the sector and be positioned at same annulus is arranged along the circular arc of annulus so that the outer edge of every circle sliver is circular arc, and the sliver setting towards the center line that all is parallel to the sector;
(D) between two adjacent sectors, reserve the quick passage of gate pole;
(E) at central area or annular region or the edge rings region division gate pole of cathode plane;
(F) will process by photoetching process by the lithography mask version of above-mentioned steps design, designed cathode pattern be transferred to the surface of chip.
9. a kind of power semiconductor device negative electrode sliver figure arrangement method according to claim 8, it is characterized in that: the quick passage of gate pole between described adjacent two sectors inserts single sliver.
10. a kind of power semiconductor device negative electrode sliver figure arrangement method according to claim 9 is characterized in that: take the center of circle as axle the cathode plane of power semiconductor device is divided into 4 ~ 64 five equilibrium sectors; Cathode plane at power semiconductor device is divided into 1 ~ 16 donut.
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| CN104600101A (en) * | 2015-02-03 | 2015-05-06 | 清华大学 | Dual-gate-electrode contact ring cathode surface layer structure of integrated gate electrode commutation thyristor chip |
| CN104795439B (en) * | 2015-03-18 | 2017-07-18 | 清华大学 | A kind of door pole stream-exchanging thyristor chip applied to hybrid dc circuit breaker |
| CN109979998B (en) * | 2018-12-27 | 2024-02-09 | 清华大学 | Integrated gate commutated thyristor device with high current surge tolerance |
| CN112234015B (en) * | 2020-10-12 | 2022-05-13 | 烟台睿瓷新材料技术有限公司 | Electrostatic chuck electrode pattern structure with concentric circle structure |
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