CN102203748B - High-speed counter processing method and counter - Google Patents
High-speed counter processing method and counter Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
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Abstract
A counter processing method and counter are provided by the embodiments of the present invention, which relate to the field of computer, can avoid the loss of the memory count and be realized easily, and have low device cost. The method provided by the embodiment of the present invention includes: when the counter value in a first storage or the transform value transformed from the counter value is not less than the depth value of a first in first out data buffer FIFO, the counter value in the first storage is moved into the FIFO, wherein the first storage is a storage with the function of static access.
Description
Technical field
The present invention relates to computer realm, relate in particular to a kind of high-speed counter disposal route and counter.
Background technology
In the statistics of 40Gbps and higher rate, as high speed router etc., need the statistical counter of a large amount of high speeds, now substantially adopt SRAM (Static Random Access Memory, static RAM)+DRAM (Dynamic Random Access Memory, dynamic RAM) hybrid plan, utilize SRAM fast and the jumbo feature of DRAM, its structure is as shown in Figure 1.
Wherein, most critical is the disposal route (Counter Management Algorithm, CMA) of counter, at present, in prior art, this has been proposed a lot of different solutions.
A kind of counter disposal route is: judge counter in SRAM whether can move DRAM in a time, adopt random thresholding to judge.An i.e. threshold T of random setting in the time that SRAM has counting event to occur, is taken out Counter Value wherein from SRAM, judges whether this Counter Value is more than or equal to threshold T, if be more than or equal to, the Counter Value in SRAM is moved in DRAM.Between SRAM and DRAM, there is a little FIFO (First In First Out, the data buffer of first in first out) to carry out buffer memory because DRAM performance limitations has little time to move immediately the Counter Value of DRAM.Even attempt to reach in the situation that the FIFO degree of depth is less by random thresholding, still can carry out moving from SRAM to DRAM with more uniform speed, on probability, avoid moving from SRAM to DRAM in speed, to occur burst.
But realizing in this process, inventor finds: the realization of random thresholding comparatively bothers, in addition, due to the probability statistics of random thresholding, in long-time running, likely occur that all SRAM Counter Values all approach the situation of this random thresholding equally; Or people send particular flow rate extrapolating after this random thresholding, thereby cause all SRAM Counter Values all to approach equally this random thresholding, therefore can cause FIFO to overflow or a large amount of SRAM Counter Values overflows, finally cause counting loss.
Another kind of counter disposal route is: regularly resettlement, according to the renewal rate ratio of SRAM and DRAM, according to all SRAM Counter Values are all moved to the required time in DRAM, determine the size of moving thresholding.In other words, see how long SRAM overflows, in the time period of not overflowing at guarantee SRAM counter, from SRAM, Counter Value is moved to DRAM; Then regularly move by this time period.Meanwhile, adopt the method, also need to safeguard that a large FIFO carries out buffer memory.
But realizing in this process, inventor finds: when resettlement, most Counter Value is all smaller, but the resettlement of each Counter Value can consume the bandwidth between SRAM and DRAM, and therefore SRAM and DRAM bandwidth occupancy are high; In addition, the method sum counter number strong correlation, in the time that counter number is many, need to takies a large amount of storage resources and be used as FIFO buffer memory and just can prevent from overflowing.
Generally speaking, high-speed counter disposal route of the prior art and counter, take a large amount of internal memories, fails effectively to avoid counting loss, and be difficult to realize, and equipment cost is high.
Summary of the invention
Embodiments of the invention provide a kind of high-speed counter disposal route and counter, can avoid internal memory counting loss, are easy to realize, equipment cost is low.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of high-speed counter disposal route, comprising:
In the time that the transformed value obtaining after the Counter Value in first memory or the conversion of described Counter Value is not less than the depth value of first in first out data buffer FIFO, described Counter Value in described first memory is moved in described FIFO, wherein, described first memory is the storer with static access facility.
A kind of high-speed counter, comprising:
First memory, for memory counter value, wherein, described first memory is the storer with static access facility;
Processing unit, in the time that the transformed value obtaining after the Counter Value of first memory or the conversion of described Counter Value is not less than the depth value of first in first out data buffer FIFO, moves into the described Counter Value in described first memory in described FIFO;
FIFO, for receive and buffer memory described in the Counter Value of first memory.
High-speed counter disposal route and counter that the embodiment of the present invention provides, in the time that the transformed value obtaining after the Counter Value in first memory or Counter Value conversion is not less than the depth value of FIFO, Counter Value in first memory is moved in FIFO, wherein, first memory is the storer with static access facility.In embodiments of the present invention, first memory is to come to its moving data, because the degree of depth of FIFO can change with its outside moving data, so for first memory, the thresholding of moving is dynamic according to the degree of depth of FIFO.So cannot estimate this threshold value by statistical computation, also just avoid estimating out all Counter Values approaching possibility of overflowing simultaneously after threshold value, reduce the probability of counting loss.In addition, the embodiment of the present invention does not need first memory and the FIFO of larger capacity yet, and equipment cost is low, is easy to realize.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is the existing counter block diagram based on hybrid plan.
The FB(flow block) of the high-speed counter disposal route that Fig. 2 provides for the embodiment of the present invention;
The FB(flow block) of the high-speed counter disposal route that Fig. 3 provides for another embodiment of the present invention;
The SRAM of high-speed counter disposal route and the schematic diagram of FIFO that Fig. 4 provides for further embodiment of this invention;
The structured flowchart of the high-speed counter that Fig. 5 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The high-speed counter disposal route that the embodiment of the present invention provides, as shown in Figure 2, the method step comprises:
S201, in the time that the transformed value obtaining after the conversion of the Counter Value in first memory or this Counter Value is not less than the depth value of first in first out data buffer FIFO, this Counter Value in first memory is moved in FIFO, wherein, this first memory is the storer with static access facility.
Concrete, first memory can be the static memory that speed is higher in actual applications, for example: static RAM SRAM (Static Random Access Memory).
Counter Value is: while having counting event to occur, and the result that the Counter Value in first memory obtains after adding up.Suppose that the Counter Value in current first memory is C, have counting event to occur, the result obtaining after adding up is C=C+1.
The transformed value obtaining after Counter Value conversion can be: the Counter Value in this first memory deducts the value obtaining after the value of initial threshold value gained, or be: Counter Value deducts after initial thresholding, convert in proportion the value of rear gained according to the depth capacity of FIFO, its concrete mapping mode describes in the following embodiments, in addition, described initial thresholding can be user-defined threshold value.
If the transformed value obtaining after the Counter Value in above-mentioned first memory or Counter Value conversion is not more than the depth value of FIFO, do not move into Counter Value to this FIFO.
Further, the method can also comprise:
S202, when having value in this FIFO, and between FIFO and second memory when available free bandwidth, the value in FIFO is moved in second memory, wherein, this second memory is the storer with dynamic access function.
Second memory can be slow storer, for example: dynamic RAM DRAM (Dynamic Random Access Memory).
In a word, first memory is the different storer of renewal rate with second memory.
The high-speed counter disposal route that the embodiment of the present invention provides, in the time that the transformed value obtaining after the Counter Value in first memory or Counter Value conversion is not less than the depth value of FIFO, moves into the Counter Value in first memory in FIFO.In embodiments of the present invention, first memory is to come to its moving data, because the degree of depth of FIFO can change with its outside moving data, so for first memory, the thresholding of moving is dynamic according to the degree of depth of FIFO.So cannot estimate this threshold value by statistical computation, also just avoid estimating out all Counter Values approaching possibility of overflowing simultaneously after threshold value, reduce the probability of counting loss.In addition, the embodiment of the present invention does not need first memory and the FIFO of larger capacity yet, and equipment cost is low, is easy to realize.
The high-speed counter disposal route providing in another embodiment of the present invention, as shown in Figure 3, the method step comprises:
S301, in the time that first memory has counting event to occur, it is cumulative that the Counter Value in this first memory count, obtains the Counter Value after counting.Wherein, this first memory is the storer with static access facility.
In the present embodiment, alternatively, first memory is high-speed memory SRAM.Suppose that the Counter Value in current first memory is C, in the time that this first memory has counting event to occur, Counter Value is counted cumulative, obtains the Counter Value after counting, is C=C+1.
S302, in the time determining that the transformed value obtaining after the conversion of this Counter Value or this Counter Value is not less than the depth value of FIFO, this Counter Value is moved into FIFO, this Counter Value is made zero simultaneously.
If this Counter Value or transformed value are not more than the depth value of FIFO, in FIFO, do not move into, this Counter Value C after counting is still written back in first memory.
At this, the transformed value obtaining after Counter Value conversion can be: this Counter Value deducts the value obtaining after the value of initial threshold value gained.Concrete, suppose that T is initial thresholding, this initial thresholding is user-defined threshold value.The degree of depth of supposing current FIFO is D, " determining that the transformed value obtaining after this Counter Value conversion is not less than the depth value of FIFO " can be for determining (C-T) > D or (C-T) >=D, can find out, in the time of T=0, counter transformed value=Counter Value.
S303, when there being value in FIFO, and between FIFO and second memory when available free bandwidth, the value in this FIFO is moved to second memory.Wherein, this second memory is the storer with dynamic access function.
In the present embodiment, second memory is dynamic RAM DRAM.When FIFO is not empty, and between FIFO and DRAM when available free bandwidth, the value in this FIFO is moved in DRAM.
It should be noted that, the invention process example assumes first memory is SRAM, and second memory is DRAM, just illustrates, and the embodiment of the present invention is not limited to this, and other any two different storeies of renewal rate can.And SRAM and DRAM are not limited to memory chip in the time of specific implementation, it can be also storage on chip.
The high-speed counter disposal route that the embodiment of the present invention provides, in the time that first memory has counting event to occur, counting is cumulative, obtains the Counter Value after counting; In the time that the transformed value obtaining after this Counter Value or the conversion of this Counter Value is not less than the depth value of FIFO, this Counter Value in first memory is moved in FIFO; Then, when there being value in FIFO, and between FIFO and second memory when available free bandwidth, the value in this FIFO is moved to second memory.In embodiments of the present invention, first memory is to come to its moving data, because the degree of depth of FIFO can change with its outside moving data, so for first memory, the thresholding of moving is dynamic according to the degree of depth of FIFO.So cannot estimate this threshold value by statistical computation, also just avoid estimating out all Counter Values approaching possibility of overflowing simultaneously after threshold value, reduce the probability of counting loss.In addition, the embodiment of the present invention does not need first memory and the FIFO of larger capacity yet, and equipment cost is low, is easy to realize.
Further, suppose that above-described embodiment Counter adds up to M, r is the speed ratio that the counter of SRAM and DRAM upgrades, and r > 1, and T is initial thresholding.Can obtain thus DRAM average bandwidth occupancy is β=r/T.The method that adopts above-described embodiment to provide, the degree of depth of supposing FIFO is n, can calculate, works as setting
time, make SRAM Counter Value can overflow required timing statistics maximum.
In addition, for specific FIFO degree of depth n, through calculating that can obtain one can make SRAM Counter Value overflow for minimum statistics number to be:
In addition, can also obtain a rational FIFO degree of depth according to the timing statistics of practical application, ensure that the SRAM Counter Value within the application cycle can never overflow.
The high-speed counter disposal route providing in another embodiment of the present invention, supposes that first memory is SRAM, and second memory is DRAM.
When SRAM is external in practice, may there is more bit bit wide as memory counter value, so can judge whether can move in FIFO for one group of Counter Value in SRAM.Judge in this SRAM whether one group of Counter Value that counting obtains after cumulative is not less than the degree of depth of current FIFO, if this group of Counter Value is not less than the degree of depth of current FIFO, this group Counter Value is moved into FIFO, this group Counter Value in SRAM is made zero simultaneously.Moving between FIFO afterwards and DRAM is same as the previously described embodiments, does not repeat them here.
Lift an object lesson below, the judgement Counter Value transformed value in this enforcement is described.As shown in Figure 4, suppose that SRAM bit wide is 10bit, Counter Value is C, and initial thresholding is T=512, the depth capacity D=128 of FIFO.The method providing according to the invention described above embodiment, can, in the time of ((C-T) > > 2) μ D, move into the count value of SRAM in FIFO.Wherein, > > is dextroposition operation, moves to right 2 and is equivalent to divided by 4.
Can find out from above-described embodiment, when SRAM bit wide wider, and the FIFO degree of depth hour, SRAM median can be equaled to the later Counter Value of the FIFO degree of depth, or Counter Value deducts the value after initial threshold, convert in proportion according to the FIFO degree of depth, obtain Counter Value transformed value, thereby make this transformed value still can be used to judge with the degree of depth of this FIFO.The transform method that above-described embodiment carries out just illustrates; the embodiment of the present invention is not limited to this, and can reach the counter transformed value all methods that still can be used to judge with the degree of depth of this FIFO that make after conversion all should be within protection scope of the present invention.
In embodiments of the present invention, first memory is to come to its moving data, because the degree of depth of FIFO can change with its outside moving data, so for first memory, the thresholding of moving is dynamic according to the degree of depth of FIFO.So cannot estimate this threshold value by statistical computation, also just avoid estimating out all Counter Values approaching possibility of overflowing simultaneously after threshold value, reduce the probability of counting loss.In addition, the embodiment of the present invention does not need first memory and the FIFO of larger capacity yet, and equipment cost is low, is easy to realize.
In addition, the present embodiment explanation, the numerical value section in the time judging whether SRAM counter can be moved can flexible expansion, but utilizes the FIFO degree of depth constant as the core of dynamic threshold.
Further, on the basis of above-described embodiment, can also judge that the value further ensureing in first memory can not overflow in following scene.
A kind of judge that scene is: when counter and/or first memory are read, judge.,, in the time that counter and/or first memory are read, in the time that the transformed value obtaining after the Counter Value in first memory or Counter Value conversion is not less than the depth value of FIFO, this Counter Value in first memory is moved in FIFO.
Certainly,, except in the time that counter and/or first memory are read, outside it is judged and is processed, can also, in the time that this first memory is carried out to other any processing, carry out judgement and the processing of above-mentioned counter disposal route to it.
Another kind of judgement scene is: periodic scanning judges the Counter Value in first memory.That is, periodic scanning judges Counter Value or the counter transformed value in first memory, in the time that the Counter Value in first memory or counter transformed value are not less than the depth value of FIFO, this Counter Value in first memory is moved in FIFO.
Moreover in the time carrying in FIFO, if find, this FIFO is full, can also suspend to first memory enter counter value.
Supplement by above-mentioned these, can further effectively prevent counting loss.
The method that the invention described above embodiment provides, all supposes that first memory is SRAM, and second memory is DRAM, just illustrates, and the embodiment of the present invention is not limited to this, and other any two different storeies of renewal rate can.And first memory and second memory can be both chip external memories, it can be also on-chip memory.
The high-speed counter that the embodiment of the present invention provides, as shown in Figure 5, comprising:
First memory 501, for memory counter value, wherein, this first memory 501 is for having the storer of static access facility.
Processing unit 502, in the time that the transformed value obtaining after the Counter Value of first memory 501 or the conversion of this Counter Value is not less than the depth value of FIFO503, moves into this Counter Value in first memory 501 in FIFO503;
FIFO503, for receiving the also Counter Value of buffer memory first memory 501.
Further, this counter also comprises: second memory 504, wherein, this second memory 504 is for having the storer of dynamic access function.
Processing unit 502 also for having value as FIFO503, and between FIFO503 and second memory 504 when available free bandwidth, is moved the value in FIFO503 in second memory 504.
Second memory 504, for receiving and store the value of FIFO503.
So, can reduce the bandwidth that takies second memory.
The high-speed counter that the embodiment of the present invention provides, in the time that the transformed value obtaining after the Counter Value in first memory or the conversion of this Counter Value is not less than the depth value of FIFO, moves into this Counter Value in first memory in described FIFO.Therefore be, to come to its moving data, because the degree of depth of FIFO can change with its outside moving data, so for first memory, the thresholding of moving is dynamic according to the degree of depth of FIFO for first memory.So cannot estimate this threshold value by statistical computation, also just avoid estimating out all Counter Values approaching possibility of overflowing simultaneously after threshold value, reduce the probability of counting loss.In addition, the embodiment of the present invention does not need first memory and the FIFO of larger capacity yet, and equipment cost is low, is easy to realize.
It should be noted that, first memory of the invention process can be any two storeies that renewal rate is different with second memory.And first memory and second memory can be both memory chips in the time of specific implementation, it can be also storage on chip.
One of ordinary skill in the art will appreciate that all or part of flow process realizing in above-described embodiment method, is to carry out hardware that instruction is relevant or the logical circuit of chip completes by computer program.Simultaneously this counter is not limited only to time counting number, also can be used for other countings, as message length counting etc.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should described be as the criterion with the protection domain of claim.
Claims (10)
1. a high-speed counter disposal route, is characterized in that, comprising:
In the time that the transformed value obtaining after the Counter Value in first memory or the conversion of described Counter Value is not less than the depth value of first in first out data buffer FIFO, described Counter Value in described first memory is moved in described FIFO, wherein, described first memory is the storer with static access facility;
Wherein, the transformed value obtaining after described Counter Value conversion is that described Counter Value deducts the value obtaining after initial threshold value, or deduct after initial thresholding for described Counter Value, the value obtaining after converting in proportion according to the depth value of described FIFO, described initial thresholding is user-defined threshold value.
2. high-speed counter disposal route according to claim 1, is characterized in that, after the Counter Value in described first memory is moved into described FIFO, described method also comprises:
Described Counter Value in described first memory is made zero.
3. according to the high-speed counter disposal route described in any one in claim 1 to 2, it is characterized in that, described method also comprises:
When having value in described FIFO, and between described FIFO and second memory when available free bandwidth, the value in described FIFO is moved in described second memory, wherein, described second memory is the storer with dynamic access function.
4. high-speed counter disposal route according to claim 1, is characterized in that, described method also comprises:
While reading counter and/or described first memory, in the time that the transformed value obtaining after the Counter Value in described first memory or the conversion of described Counter Value is not less than the depth value of described FIFO, the described Counter Value in described first memory is moved in described FIFO.
5. high-speed counter disposal route according to claim 1, is characterized in that, described method also comprises:
The transformed value obtaining after Counter Value described in periodic scanning in first memory or the conversion of described Counter Value, in the time that described Counter Value or described transformed value are not less than the depth value of FIFO, the described Counter Value in described first memory is moved in described FIFO.
6. high-speed counter disposal route according to claim 1, is characterized in that, described method also comprises:
In the time that described FIFO expires, suspend to described first memory enter counter value.
7. high-speed counter disposal route according to claim 3, is characterized in that, the renewal rate of described first memory and described second memory is different.
8. a high-speed counter, is characterized in that, comprising:
First memory, for memory counter value, wherein, described first memory is the storer with static access facility;
Processing unit, in the time that the transformed value obtaining after the Counter Value of first memory or the conversion of described Counter Value is not less than the depth value of first in first out data buffer FIFO, moves into the described Counter Value in described first memory in described FIFO;
FIFO, for receive and buffer memory described in the Counter Value of first memory;
Wherein, the transformed value obtaining after described Counter Value conversion is that described Counter Value deducts the value obtaining after initial threshold value, or deduct after initial thresholding for described Counter Value, the value obtaining after converting in proportion according to the depth value of described FIFO, described initial thresholding is user-defined threshold value.
9. high-speed counter according to claim 8, is characterized in that, described counter also comprises second memory, and wherein, described second memory is the storer with dynamic access function;
Described processing unit also for having value as described FIFO, and between described FIFO and described second memory when available free bandwidth, is moved the value in described FIFO in described second memory;
Described second memory, for receiving and store the value of described FIFO.
10. high-speed counter according to claim 9, is characterized in that, the renewal rate of described first memory and described second memory is different.
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| PCT/CN2009/074983 WO2011060570A1 (en) | 2009-11-17 | 2009-11-17 | High-speed counter processing method and counter |
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| CN105786718A (en) * | 2014-12-26 | 2016-07-20 | 中兴通讯股份有限公司 | Counting processing method and device |
| CN105119768A (en) * | 2015-06-26 | 2015-12-02 | 华为技术有限公司 | Field-programmable gate array FPGA and data storage method |
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| US6967885B2 (en) * | 2004-01-15 | 2005-11-22 | International Business Machines Corporation | Concurrent refresh mode with distributed row address counters in an embedded DRAM |
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Effective date of registration: 20211220 Address after: 450046 Floor 9, building 1, Zhengshang Boya Plaza, Longzihu wisdom Island, Zhengdong New Area, Zhengzhou City, Henan Province Patentee after: xFusion Digital Technologies Co., Ltd. Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: HUAWEI TECHNOLOGIES Co.,Ltd. |