WO2011060570A1

WO2011060570A1 - High-speed counter processing method and counter

Info

Publication number: WO2011060570A1
Application number: PCT/CN2009/074983
Authority: WO
Inventors: 陈略; 王正波; 肖斌
Original assignee: 华为技术有限公司
Priority date: 2009-11-17
Filing date: 2009-11-17
Publication date: 2011-05-26
Also published as: CN102203748A; CN102203748B

Abstract

A counter processing method and counter are provided by the embodiments of the present invention, which relate to the field of computer, can avoid the loss of the memory count and be realized easily, and have low device cost. The method provided by the embodiment of the present invention includes: when the counter value in a first storage or the transform value transformed from the counter value is not less than the depth value of a first in first out data buffer FIFO, the counter value in the first storage is moved into the FIFO, wherein the first storage is a storage with the function of static access.

Description

High-speed counter processing method and counter

The present invention relates to the field of computers, and in particular, to a high-speed counter processing method and a counter. Background technique

In the statistics of 40 Gbps and higher speeds, such as high-speed routers, a large number of high-speed statistical counters are required. In this case, SRAM (Static Random Access Memory) + DRAM (Dynamic Random Access Memory) is basically used. Dynamic random access memory) hybrid scheme to take advantage of the fastness of SRAM and the large capacity of DRAM. Its structure is shown in Figure 1.

Among them, the most important is the Counter Management Algorithm (CMA). At present, many different solutions are proposed in the prior art.

A counter processing method is: When it is judged whether the counter in the SRAM can be moved to the DRAM, the random threshold is used for judging. That is, a threshold value T is randomly set. When a counting event occurs in the SRAM, the counter value is taken out from the SRAM, and it is judged whether the counter value is greater than or equal to the threshold value T. If it is greater than or equal to, the counter value in the SRAM is used. Moved to DRAM. There is a small FIFO (First In First Out) between the SRAM and the DRAM to buffer the counter value that is not immediately moved to the DRAM due to DRAM performance limitations. Through random thresholds, it is attempted to move from SRAM to DRAM at a relatively uniform rate even when the FIFO depth is small, and the probability of shifting from SRAM to DRAM at a rate is unexpected.

However, in the process of implementing this process, the inventor found that: the implementation of random threshold is more cumbersome. In addition, due to the probability and statisticality of random thresholds, it may happen that all SRAM counter values are close to the random threshold in long-term operation; A specific traffic is sent after the random threshold is derived, causing all SRAM counter values to be close to the random threshold, thus causing a FIFO overflow or a large number of SRAM counter values to overflow, eventually resulting in a lost count.

Another counter processing method is: Periodic relocation, that is, according to the update rate ratio of SRAM and DRAM, the size of the shift threshold is determined according to the time required to move all the SRAM counter values to the DRAM. Or, to see how long the SRAM overflows, to ensure that the SRAM counter does not overflow. The counter value is moved from the SRAM to the DRAM during the time period; then it is periodically relocated according to this time period. At the same time, using this method, you also need to maintain a large FIFO for caching.

However, in the process of implementing this process, the inventor found that: most of the counter values during relocation are relatively small, but the relocation of each counter value consumes the bandwidth between SRAM and DRAM, so the bandwidth of SRAM and DRAM is high; The method is strongly related to the number of counters. When the number of counters is relatively large, a large amount of storage resources are required to be used as a FIFO buffer to prevent overflow.

In summary, the high-speed counter processing method and counter in the prior art occupy a large amount of memory, fail to effectively avoid counting loss, and are difficult to implement, and the equipment cost is high.

Summary of the invention

Embodiments of the present invention provide a high-speed counter processing method and a counter, which can avoid loss of memory count, are easy to implement, and have low equipment cost.

In order to achieve the above object, embodiments of the present invention use the following technical solutions:

A high speed counter processing method includes:

And shifting the counter value in the first memory into the FIFO when a counter value in the first memory or a converted value obtained by converting the counter value is not less than a depth value of the FIFO data buffer FIFO The first memory is a memory having a static access function.

A high speed counter comprising:

a first memory, configured to store a counter value, where the first memory is a memory having a static access function;

a processing unit, configured to: when the counter value in the first memory or the converted value obtained by converting the counter value is not less than a depth value of the FIFO data buffer FIFO, the counter value in the first memory Moved into the FIFO;

a FIFO, configured to receive and buffer a counter value in the first memory.

The high-speed counter processing method and the counter provided by the embodiment of the present invention, when the converted value obtained by converting the counter value or the counter value in the first memory is not less than the depth value of the FIFO, the counter value in the first memory is moved into the FIFO. The first memory is a memory having a static access function. In the embodiment of the present invention, the first memory moves data to the FIFO according to the depth of the FIFO. Since the depth of the FI FO changes as it moves the data outward, the threshold for the move is dynamic for the first memory. Therefore, it is impossible to estimate the threshold by statistical calculation, which avoids the possibility that all counter values are close to overflow after the threshold is estimated, and the probability of counting loss is reduced. In addition, the embodiment of the present invention also does not require a larger memory of the first memory and the FIFO, and the device cost is low and easy to implement.

DRAWINGS

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.

Figure 1 is a block diagram of a counter based on a hybrid scheme.

1 is a flow chart of a method for processing a high speed counter according to an embodiment of the present invention;

3 is a block diagram of a high-speed counter processing method according to another embodiment of the present invention; FIG. 4 is a schematic diagram of a SRAM and a FIFO of a high-speed counter processing method according to another embodiment of the present invention;

FIG. 5 is a structural block diagram of a high speed counter according to an embodiment of the present invention.

detailed description

The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. It is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts are within the scope of the present invention.

The high-speed counter processing method provided by the embodiment of the present invention is as shown in FIG. 2, and the method steps include:

S20, when the counter value in the first memory or the converted value obtained by the counter value is not less than the depth value of the FIFO data buffer FIFO, the counter value in the first memory is moved into the FIFO, wherein the A memory is a memory having a static access function.

Specifically, the first memory may be a static memory with higher speed in practical applications, for example: Static random access memory SRAM (Static Random Acces s Memory).

The counter value is: The result obtained by accumulating the counter value in the first memory when a counting event occurs. Assuming that the current counter value in the first memory is C, and a count event occurs, the result obtained after the accumulation is C=C+1.

The converted value obtained after the counter value is converted may be: a value obtained by subtracting the value obtained from the initial threshold value in the first memory, or as follows: after the counter value is subtracted from the initial threshold, according to the maximum FIFO The value obtained after the depth is converted in proportion is specifically described in the following embodiments. In addition, the initial threshold may be a user-defined threshold.

If the converted value obtained by the counter value or the counter value in the first memory is not larger than the depth value of the FIFO, the counter value is not shifted into the FIFO.

Further, the method may further include:

S202, when there is a value in the FIFO, and there is a free bandwidth between the FIFO and the second memory, the value in the FIFO is moved to the second memory, wherein the second memory is a memory with dynamic access function.

The second memory may be a slower memory such as Dynamic Random Accs DRAM (DRAM).

In summary, the first memory and the second memory are memories having different update rates.

The high-speed counter processing method provided by the embodiment of the present invention moves the counter value in the first memory into the FIFO when the converted value obtained by converting the counter value or the counter value in the first memory is not less than the depth value of the FIFO. In the embodiment of the present invention, the first memory moves data to the FIFO according to the depth of the FIFO. Since the depth of the FIFO changes as the data moves outward, the threshold for the first memory is dynamic. of. Therefore, it is impossible to estimate the threshold by statistical calculation, which avoids the possibility that all counter values are close to overflow after the threshold is estimated, and the probability of counting loss is reduced. In addition, the embodiment of the present invention also does not require a larger capacity of the first memory and the FIFO, and the device cost is low and easy to implement.

In the high-speed counter processing method provided by another embodiment of the present invention, as shown in FIG. 3, the method steps include: S 30 When a count event occurs in the first memory, the counter value in the first memory is counted and accumulated, and the counter value after the count is obtained. The first memory is a memory having a static access function.

In this embodiment, optionally, the first memory is a high speed memory SRAM. 4 叚 Set the current counter value in the first memory When the first memory has a counting event, the counter value is counted and accumulated, and the counter value after counting is obtained, which is C=C+1.

5302. When it is determined that the counter value or the converted value obtained by the counter value is not less than the depth value of the FIFO, the counter value is carried into the FIFO, and the counter value is reset to zero.

If the counter value or the converted value is not greater than the depth value of the FIFO, no shift is made to the FIFO, and the counter value C after the count is still written back into the first memory.

Here, the transformed value obtained after the counter value is converted may be: a value obtained by subtracting the value obtained by the initial threshold value from the counter value. Specifically, it is assumed that T is the initial threshold, and the initial threshold is a user-defined threshold. Assume that the current depth of F IFO is D, "determine that the transformed value obtained after the counter value is transformed is not less than the depth value of F IFO" can be determined - "〉 or (^- " A can be seen, at that time, the counter transformation value = Counter value.

5303. When there is a value in the FIFO, and there is an idle bandwidth between the F IFO and the second memory, the value in the FIFO is moved to the second memory. The second memory is a memory with dynamic access function.

In this embodiment, the second memory is a dynamic random access memory DRAM. When the FIFO is not empty and there is free bandwidth between the FIFO and the DRAM, the value in the FIFO is moved to the DRAM.

It should be noted that, in the embodiment of the present invention, the first memory is an SRAM, and the second memory is a DRAM. For example, the embodiment of the present invention is not limited thereto, and any other memory with different update rates may be used. Moreover, the SRAM and the DRAM are not limited to the off-chip memory in the specific implementation, and may be an on-chip memory.

The high-speed counter processing method provided by the embodiment of the present invention, when the first memory has a counting event, the counting is accumulated, and the counter value after the counting is obtained; when the counter value or the counter value is converted, the converted value is not less than the depth of the FIFO. When the value is, the counter value in the first memory is moved in In the FIFO; then, when there is a value in the FIFO and there is free bandwidth between the FIFO and the second memory, the value in the FIFO is moved to the second memory. In the embodiment of the present invention, the first memory moves data to the FIFO according to the depth of the FIFO. Since the depth of the FIFO changes as the data moves outward, the threshold for the movement is dynamic for the first memory. of. Therefore, it is impossible to estimate the threshold by statistical calculation, which avoids the possibility that all counter values are close to overflow after the threshold is estimated, and the probability of counting loss is reduced. In addition, the embodiment of the present invention also does not require a larger memory of the first memory and the FIFO, and the device cost is low and easy to implement.

Further, it is assumed that the total number of counters in the above embodiment is the ratio of the rate at which the counters of the SRAM and the DRAM are updated, and Γ is the initial threshold. Thus, the average bandwidth occupancy of the DRAM is β = τΙ Τ. Using the method provided in the above embodiment, assuming that the depth of the FIFO is n, it can be estimated that when the "≥lg, ^/lg^^" is set, the statistical time required for the SRAM counter value to overflow is the most

Μ ) r )

Big.

In addition, for a specific F IFO depth, a calculated number of statistics that can cause the SRAM counter value to overflow to a minimum is:

OneLowerBound = x (T + r - \) -Mx (T - \) - r In addition, a reasonable FI F0 depth can be obtained according to the statistical time of the actual application, ensuring that the SRAM counter value will never overflow during the application cycle. .

In a high speed counter processing method provided by another embodiment of the present invention, it is assumed that the first memory is an SRAM and the second memory is a DRAM.

In practice, when the SRAM is external, more b i t bit width may be used as the storage counter value, so it is possible to determine whether it can be moved to the FIFO for a set of counter values in the SRAM. That is, it is determined whether the set of counter values obtained by counting the counts in the SRAM is not less than the depth of the current FIFO. If the set of counter values is not less than the depth of the current FIFO, the set of counter values is moved into the FIFO, and the SRAM is The group counter value is zeroed. The subsequent movement between the F IFO and the DRAM is the same as that of the above embodiment, and will not be described herein.

A specific example will be given below to describe the judgment counter value conversion value in the present embodiment. As shown in Figure 4 It is assumed that the SRAM bit width is 10 bi t , the counter value is C, the starting threshold is = 512, and the maximum depth of the FIFO is 128. According to the method provided by the embodiment of the present invention, the count value of the SRAM can be carried into the FIFO at ((C- Γ) » 2 ). Where >> is the right shift operation, and shifting 2 bits to the right is equivalent to dividing by 4.

It can be seen from the above embodiment that when the SRAM has a wide bit width and a small FIFO depth, the SRAM median can be equal to the counter value after the FIFO depth, or the counter value can be subtracted from the initial threshold, according to the FIFO depth. The scale is transformed to obtain a counter value transformed value so that the transformed value can still be used to determine the depth of the FIFO. The conversion method performed by the above embodiment is only an example, and the embodiment of the present invention is not limited thereto, and all methods for making the converted counter conversion value still usable for determining the depth of the FI F0 should be used. Within the scope of protection of the invention.

In the embodiment of the present invention, the first memory moves data to the FIFO according to the depth of the FIFO. Since the depth of the FI F0 changes as the data moves outward, the threshold for the first memory is Dynamic. Therefore, it is impossible to estimate the threshold by statistical calculation, which avoids the possibility that all counter values are close to overflow at the same time after the threshold is estimated, and the probability of counting loss is reduced. In addition, the embodiment of the present invention also does not require a larger memory of the first memory and the FIFO, and the device cost is low and easy to implement.

In addition, this embodiment illustrates that the value section when determining whether the SRAM counter can be moved can be flexibly expanded, but the core using the FIFO depth as the dynamic threshold is unchanged.

Further, based on the above embodiment, it is also possible to make a decision in the following scenario to further ensure that the value in the first memory does not overflow.

One decision scenario is: A decision is made while reading the counter and/or the first memory. That is, when the counter and/or the first memory are read, when the counter value obtained by converting the counter value or the counter value in the first memory is not less than the depth value of the FIFO, the counter value in the first memory is used. Move into the FIFO.

Of course, in addition to the determination and processing of the counter and/or the first memory, it may be subjected to the above calculation when performing any other processing on the first memory. The determination and processing of the digital processing method.

Another decision scenario is: Periodically scan to determine the counter value in the first memory. That is, the periodic scan determines the counter value or the counter conversion value in the first memory, and when the counter value or the counter conversion value in the first memory is not less than the depth value of the FIFO, the counter value in the first memory is moved into the FIFO.

Furthermore, when the FIFO is loaded, it is also possible to suspend the input of the counter value to the first memory if the FIFO is found to be full.

With the above additions, it is possible to further effectively prevent the count loss.

The method provided by the embodiment of the present invention assumes that the first memory is an SRAM and the second memory is a DRAM. For example, the embodiment of the present invention is not limited thereto, and any other memory with different update rates may be used. Also, the first memory and the second memory may be either off-chip memories or on-chip memories.

The high-speed counter provided by the embodiment of the present invention, as shown in FIG. 5, includes:

The first memory 501 is configured to store a counter value, wherein the first memory 501 is a memory having a static access function.

The processing unit 502 is configured to: when the counter value in the first memory 501 or the converted value obtained by the counter value is not less than the depth value of the FIFO 503, move the counter value in the first memory 501 into the FIFO 503;

The FIFO 503 is configured to receive and buffer a counter value in the first memory 501.

Further, the counter further includes: a second memory 504, wherein the second memory 504 is a memory having a dynamic access function.

The processing unit 502 is further configured to move the value in the FIFO 503 to the second memory 504 when there is a value in the FIFO 503 and there is a free bandwidth between the FIFO 503 and the second memory 504.

The second memory 504 is configured to receive and store values in the FIFO 503.

In this way, the bandwidth occupied by the second memory can be reduced.

The high-speed counter provided by the embodiment of the present invention, when the counter value in the first memory or the converted value obtained by the counter value is not less than the depth value of the FIFO, the count in the first memory The value is shifted into the FIFO. Therefore, for the first memory, data is moved to the first memory according to the depth of the FIFO. Since the depth of the FIFO changes as the data moves outward, the threshold for the movement is dynamic for the first memory. Therefore, it is impossible to estimate the threshold by statistical calculation, which avoids the possibility that all counter values are close to overflow after the threshold is estimated, and the probability of counting loss is reduced. In addition, the embodiment of the present invention also does not require a larger memory of the first memory and the FIFO, and the device cost is low and easy to implement.

It should be noted that the first memory and the second memory implemented by the present invention may be any two memories with different update rates. Moreover, in a specific implementation, the first memory and the second memory may be either an off-chip memory or an on-chip memory.

One of ordinary skill in the art will appreciate that implementing all or part of the processes in the above-described embodiments can be accomplished by a computer program that instructs the associated hardware or chip logic. At the same time, this counter is not limited to the count of times, but can also be used for other counts, such as the length of the message.

The above is only the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope of the present invention. It should be covered by the scope of the present invention. Therefore, the scope of the invention should be determined by the scope of the claims.

Claims

Claim

A high-speed counter processing method, comprising:

The high-speed counter processing method according to claim 1, wherein the converted value obtained by converting the counter value is: a value obtained by subtracting the initial threshold value from the counter value, or After the value of the counter is subtracted from the initial threshold, the value obtained by scaling according to the depth value of the FIFO is used; wherein the initial threshold is a user-defined threshold.

The high-speed counter processing method according to claim 1, wherein after the counter value in the first memory is moved into the FIFO, the method further includes:

The counter value in the first memory is zeroed.

The high-speed counter processing method according to any one of claims 1 to 3, wherein the method further comprises:

When there is a value in the FIFO, and there is a free bandwidth between the FIFO and the second memory, the value in the FIFO is moved to the second memory, wherein the second memory has dynamic memory Take the function of the memory.

The method of processing a high-speed counter according to claim 1, wherein the method further comprises:

When the counter and/or the first memory are read, when the counter value in the first memory or the converted value obtained by the counter value is not less than the depth value of the FIFO, the first memory is The counter value in is shifted into the FIFO.

Periodically scanning a counter value in the first memory or a transformed value obtained by converting the counter value, and when the counter value or the converted value is not less than a depth value of the FIFO, the first memory is The counter value is shifted into the FIFO.

When the FIFO is full, the input of the counter value to the first memory is suspended.

The high-speed counter processing method according to claim 5, wherein the update rates of the first memory and the second memory are different.

9. A high speed counter, comprising:

a FIFO for receiving and buffering a counter value in the first memory.

The high-speed counter according to claim 9, wherein the counter further includes a second memory, wherein the second memory is a memory having a dynamic access function;

The processing unit is further configured to: when a value exists in the FIFO, and a free bandwidth exists between the FIFO and the second memory, move a value in the FIFO to the second memory;

The second memory is configured to receive and store a value in the FIFO.

The high speed counter according to claim 10, wherein the update rates of the first memory and the second memory are different.