CN102571477B - Traffic statistic device, chip and equipment - Google Patents
Traffic statistic device, chip and equipment Download PDFInfo
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- CN102571477B CN102571477B CN201010617860.1A CN201010617860A CN102571477B CN 102571477 B CN102571477 B CN 102571477B CN 201010617860 A CN201010617860 A CN 201010617860A CN 102571477 B CN102571477 B CN 102571477B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Abstract
The invention is applied to the field of data communication and provides a traffic statistic device, a chip and equipment. The traffic statistic device comprises a physical interface traffic statistic circuit, a logical channel traffic statistic circuit and a memory module. The logical channel traffic statistic circuit for respectively counting the traffic of each logical channel is additionally arranged in the current traffic statistic device disclosed by the invention without establishing statistic circuits corresponding to different logical channels one by one according to the different logical channels. Compared with the prior art, the traffic statistic device disclosed by the invention has the advantages that the traffic statistic of each logical channel can be realized with lower resource consumption and cost.
Description
Technical field
The invention belongs to data communication field, relate in particular to a kind of flow statistic device, chip and equipment.
Background technology
Flow statistic device is the functional module that is absolutely necessary in the various chips in the communications field, its for statistical unit in the time by the flow of certain interface, for the state of each interface of chip monitoring provides important means.Such as, in digital communication chip, each interface is carried out to the statistics of message flow (PPS) and byte flow (BPS), just need to use flow statistic device.And current a lot of communication protocol and interface are all supported multichannel, as SONET/SDH, SPI4.2 etc., for a this situation that physical interface comprises a plurality of logical channels, need to add up the flow of each logical channel.
In chip design, during use traffic statistic device, for the feature of multi-logical channel, designer always wishes that flow statistic device meets following demand:
The flow statistic device newly-increased flow that must add up fast.Under this single physical interface multi-logical channel applied environment, each clock cycle may have flow to add up, but the same clock cycle only has a logical channel to need flow cumulative.
The logical channel number that flow statistic device is supported is abundant.In order to add up the flow of a total flow in physical interface and each logical channel, flow statistic device must be able to be processed tens even traffic statistics of a hundreds of logical channel, as Interlaken and SPI4.2 at most can support 256 logical channels.
And the defect of current existing flow statistic device is:
Flow statistic device for be incoherent physical interface, i.e. the corresponding flow statistic device of physical interface, and also only support a logical channel in a physical interface.While using such flow statistic device, can not add up the flow of each logical channel simultaneously, thereby have to realize statistical function (a corresponding statistical module of logical channel) with a plurality of statistical modules.When the quantity of logical channel is more, to the consumption of resource, be very surprising.Therefore, existing flow statistic device, in order to meet the demand simultaneously, need to be paid great cost.
Summary of the invention
The object of the embodiment of the present invention is to provide a kind of flow statistic device, and while being intended to solve the flow of current each logical channel of statistics, resource consumption is large, the problem that cost is high.
The embodiment of the present invention is achieved in that a kind of flow statistic device, and described flow statistic device comprises:
Physical interface traffic statistics circuit, logical channel traffic statistics circuit and memory module;
Wherein, described physical interface traffic statistics circuit, for adding up the data on flows of whole physical interface, and exports the data on flows after statistics to described memory module;
Described logical channel traffic statistics circuit, for adding up respectively the data on flows of each logical channel, and exports the data on flows after statistics to described memory module;
Described memory module, for storing the data on flows of whole physical interface and the data on flows of each logical channel, and when CPU needs, exports above-mentioned data on flows to CPU.
Another object of the embodiment of the present invention is to provide a kind of chip that comprises described flow statistic device.
Another object of the embodiment of the present invention is to provide a kind of equipment that comprises described flow statistic device.
The embodiment of the present invention adds for adding up respectively the logical channel traffic statistics circuit of each logical channel flow in current flow statistic device, and without according to different logical channels, set up with it statistical circuit one to one, compared with prior art, the present invention can realize the traffic statistics to each logical channel with lower resource consumption and cost.
Accompanying drawing explanation
Fig. 1 is the fundamental diagram of the flow statistic device that provides of first embodiment of the invention;
Fig. 2 is the circuit structure diagram of the flow statistic device that provides of first embodiment of the invention;
Fig. 3 is the fundamental diagram of the flow statistic device that provides of second embodiment of the invention;
Fig. 4 is the circuit structure diagram of the flow statistic device that provides of second embodiment of the invention.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
The embodiment of the present invention is during for the flow of current each logical channel of statistics, need to set corresponding statistical module and the resource consumption that causes is large in different logical channels, high in cost of production problem, according to the character of the traffic transport of logical channel and increase, in current flow statistic device, add for adding up respectively the logical channel traffic statistics circuit of each logical channel flow, can to each logical channel, carry out traffic statistics respectively with lower resource consumption and cost.
The embodiment of the present invention is achieved in that
A flow statistic device, described flow statistic device comprises:
Physical interface traffic statistics circuit, logical channel traffic statistics circuit and memory module;
Wherein, described physical interface traffic statistics circuit, for adding up the data on flows of whole physical interface, and exports the data on flows after statistics to described memory module;
Described logical channel traffic statistics circuit, for adding up respectively the data on flows of each logical channel, and exports the data on flows after statistics to described memory module;
Described memory module, for storing the data on flows of whole physical interface and the data on flows of each logical channel, and when CPU needs, exports above-mentioned data on flows to CPU.
Another object of the embodiment of the present invention is to provide a kind of chip that comprises described flow statistic device.
Another object of the embodiment of the present invention is to provide a kind of equipment that comprises described flow statistic device.
The embodiment of the present invention adds for adding up respectively the logical channel traffic statistics circuit of each logical channel flow in current flow statistic device, and without according to different logical channels, set up with it statistical circuit one to one, compared with prior art, the present invention can carry out traffic statistics to each logical channel respectively with lower resource consumption and cost.
embodiment mono-:
Fig. 1 shows the fundamental diagram of the flow statistic device that first embodiment of the invention provides, and only shows for convenience of explanation the part relevant to the embodiment of the present invention.
Comprise physical interface traffic statistics circuit 11, logical channel traffic statistics circuit 12 and memory module 13;
Wherein, physical interface traffic statistics circuit 11, for adding up the data on flows of whole physical interface, and exports the data on flows after statistics to memory module 13;
Logical channel traffic statistics circuit 12, for adding up respectively the data on flows of each logical channel, and exports the data on flows after statistics to memory module 13;
Memory module 13, for storing the data on flows of whole physical interface and the data on flows of each logical channel, and when CPU needs, exports above-mentioned data on flows to CPU.
Herein, the definition of physical interface is not limited to chip and outside interface, also comprises the interface between chip internal modules;
The definition of logical channel is not limited to a subchannel in physical interface, is also included in the logical subsets of other type of transmission in physical interface.
In real work, physical interface traffic statistics circuit 11, by after the data on flows statistics of whole physical interface, to memory module 13 outputs.It is a circuit that is independent of channel level traffic statistics.
It is cumulative that logical channel traffic statistics circuit 12 can both be processed a flow within each clock cycle, and in the same clock cycle, only may have a passage to need flow cumulative between a plurality of logical channels, so logical channel traffic statistics circuit 12 can meet a plurality of logical channel stream quantitative statistics needs completely.So, after logical channel traffic statistics circuit 12 is cumulative by the data on flows of each logical channel, be stored in respectively in memory module 13.
Like this, CPU when needed, just can read the data on flows of each logical channel in the data on flows of whole physical interface and physical interface from memory module 13.
The embodiment of the present invention adds for adding up respectively the logical channel traffic statistics circuit of each logical channel flow in current flow statistic device, and without according to different logical channels, set up corresponding statistical circuit, compared with prior art, the present invention can carry out traffic statistics to each logical channel respectively with lower resource consumption and cost.
embodiment bis-:
Fig. 2 shows the circuit structure of the flow statistic device that first embodiment of the invention provides, and only shows for convenience of explanation the part relevant to the embodiment of the present invention.
Physical interface traffic statistics circuit 11 comprises physical interface flow summer 21 and physical interface accumulated value register 22;
Wherein, physical interface flow summer 21, for by the data on flows of physical interface current period and newly-increased data on flows cumulative after, export the data on flows of physical interface to physical interface accumulated value register 22.
Physical interface accumulated value register 22, for storing the data on flows of physical interface, and to the data on flows of described physical interface flow summer 21 output physical interface current periods, and to the data on flows of described memory module output physical interface.
Logical channel traffic statistics circuit 12 comprises channel number/address conversioning unit 23, data delay unit 24, logical channel flow summer 25 and memory RAM 1.
Wherein, channel number/address conversioning unit 23, for logical channel number (LCN) being converted to memory address (address ram), and sends memory address into memory RAM 1.
Data delay unit 24, for postponing the newly-increased data on flows of logical channel after the clock cycle, to export logical channel flow summer 25 to.
Logical channel flow summer 25, after the current data on flows of each logical channel and newly-increased data on flows is cumulative respectively, exports the data on flows of logical channel to memory RAM 1.
Memory RAM 1, for store the data on flows of each logical channel according to the memory address of channel number/address conversioning unit 23 outputs, and to the current data on flows of logical channel flow summer 25 each logical channel of output, and data on flows from each logical channel current periods to memory module 13 that export.Memory RAM 1 can be random access memory or other memories.
Memory module 13 is random access memory, can be also other memories, for the data on flows in each last cycle of logical channel in the last cycle data on flows of whole physical interface and physical interface is provided to CPU.Preferably, memory module 13 adopts random access memory, with saving resource, and obtains storage efficiency better.
In real work, when having data on flows input, for storing the physical interface accumulated value register 22 of physical interface data on flows, to the current data on flows of physical interface flow summer 21 output physical interface.Physical interface flow summer 21 by the current data on flows of physical interface and newly-increased data on flows cumulative after, export the cumulative data on flows of physical interface to physical interface accumulated value register 22.Meanwhile, physical interface accumulated value register 22 to the cumulative data on flows of memory module 13 these physical interfaces of output, flows quantitative statistics to complete physical interface when each measurement period finishes.
Aspect the traffic statistics of logical channel, first, by data delay unit 24 by a clock cycle of data on flows time delay, and send into memory RAM 1 after channel number being converted to memory address by channel number/address conversioning unit 23, after a clock cycle, from memory RAM 1, export the integrated flow data of this passage in current period, the new data on flows obtaining of data delay unit 24 output simultaneously, logical channel flow summer 25 is by these two data accumulations, obtain after a new data on flows accumulated value, this data on flows accumulated value is stored in memory RAM 1.Memory RAM 1 is mainly used in storing according to the address of channel number/address conversioning unit 23 outputs the data on flows of each logical channel, and when current measurement period finishes to total integrated flow data of memory module 13 output logic passage current periods, thereby complete each logical channel stream quantitative statistics.
It is cumulative that above-mentioned 12 each clock cycle of logical channel traffic statistics circuit can be processed 1 flow.And at same period, only may have a passage to need flow cumulative between a plurality of logical channels, so sort circuit can meet the express statistic of a plurality of logical channel flows completely.
With respect to existing flow statistical method, when realizing the passage of equal number, the scheme that this multichannel is shared accumulator and carried out buffer memory accumulated value with random access memory, can save a large amount of accumulators and register resources.For example, when the port number of realizing is 128, can reduce by 127 accumulators, and use the memory buffer accumulated value in chip, than using one by one independently register, the former has the advantage on capacity and cost.
The embodiment of the present invention is according to the character of traffic transport and increase, flow statistic device is distinguished to the traffic statistics circuit for physical interface traffic statistics circuit and each logical channel, in the traffic statistics circuit of logical channel, adopted the method for each channels share accumulator, and use memory buffer accumulated value, can realize the traffic statistics to each logical channel with lower resource consumption and cost.
embodiment tri-:
Fig. 3 shows the operation principle of the flow statistic device that second embodiment of the invention provides, and only shows for convenience of explanation the part relevant to the embodiment of the present invention.
The flow statistic device that second embodiment of the invention provides is on the basis of the flow statistic device that provides in first embodiment of the invention, added periodic refreshing circuit 31, this circuit can be selected measurement period, and when selected measurement period finishes, the data on flows of the data on flows of described physical interface traffic statistics circuit and described logical channel traffic statistics circuit is write to memory module 13, then refresh the data on flows of physical interface traffic statistics circuit and the data on flows of logical channel traffic statistics circuit, with the flow of physical interface in acquisition different cycles and the statistics of the flow of logical channel.The circuit structure of the flow statistic device that second embodiment of the invention provides as shown in Figure 4.
Memory RAM 1 is a dual-ported memory, and wherein, port A is used for reading the current integrated flow of each logical channel, and is sent to the accumulated computing of logical channel flow summer 25.Port B is used for the cumulative result of input logic channel capacity accumulator 25, and when current measurement period finishes, the content of memory RAM 1 is outputed in memory RAM 2.Therefore before the port B of memory RAM 1, have a read-write control circuit, for the access of management port B, this read-write control circuit is a part for memory RAM 1 in logical channel traffic statistics circuit 12.
Read-write control circuit is in measurement period process, the logical access address that is input to port A is preserved and postponed two clock cycle, so just synchronize with the result of logical channel flow summer 25 outputs, then synchronous address is input in memory RAM 1 by port B together with result data.When measurement period finishes, refresh control circuit need to read the total integrated flow of each logical channel in current period by port B, and sends in memory RAM 2.Therefore refresh control circuit can be inputted a plurality of read requests to read-write control circuit, the corresponding logical channel of each read request.Refresh control circuit initiates a read request every several clock cycle (as: 1 or 10 clock cycle).
When read-write control circuit receives a request of reading logical channel statistics, first wait for the gap of logical channel flow summer 25 Output rusults, when not having accumulated value to need write memory RAM1, process a read request: the data on flows of reading counterlogic passage, then toward this address, write 0, complete refreshing of a passage.Logical channel refresh complete after, just again since 0 data on flows of adding up in next cycle.If very close to each other before the 9th clock cycle, can be used for processing read request, the 10th clock cycle, force to refresh this passage.Because request allows read-write control circuit, there are 10 clock cycle to process, can utilize gap to complete to the refreshing of each passage, so whole refresh process is very little on 12 impacts of logical channel traffic statistics circuit.
Wherein, read-write control circuit is a part for memory RAM 1 in logical channel traffic statistics circuit 12.
Refresh control circuit is used for setting measurement period, and when each measurement period finishes, the data on flows of logical channel and physical interface is exported to memory RAM 2.Measurement period is a parameter that CPU is controlled, has very large flexibility.
The embodiment of the present invention by adding periodic refreshing circuit in flow statistic device, it is adjustable that thereby the sampling period that makes flow statistic device becomes, be applicable to more occasion, there is greater flexibility, can obtain the average discharge in the different unit interval according to actual demand.
embodiment tetra-:
The various device of the chip that the flow statistic device that the embodiment of the present invention provides can comprise above-mentioned flow statistic device for various chips and the use in the fields such as communication.
The beneficial effect of the embodiment of the present invention is:
1, in current flow statistic device, add for adding up respectively the logical channel traffic statistics circuit of each logical channel flow, and without according to different logical channels, set up with it statistical circuit one to one, can realize the traffic statistics to each logical channel with lower resource consumption and cost;
2, by each logical channel, share the method for accumulator, only use an accumulator and to complete the flow of all logical channels cumulative, can significantly reduce the cost of statistic logic channel capacity;
3, the carrier of storage data on flows mainly be take random access memory (RAM) as main, rather than take one by one independently register and, as main, compare with register, and random access memory has the advantages that capacity is large, cost is low;
4, by add periodic refreshing circuit in flow statistic device, thereby can be adjusted in the sampling period of flow statistic device, can be applicable to more occasion, there is greater flexibility, can obtain the average discharge in different chronomeres according to actual demand.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any modifications of doing within the spirit and principles in the present invention, be equal to and replace and improvement etc., within all should being included in protection scope of the present invention.
Claims (7)
1. a flow statistic device, is characterized in that, described flow statistic device comprises:
Physical interface traffic statistics circuit, logical channel traffic statistics circuit, periodic refreshing circuit and memory module;
Wherein, described physical interface traffic statistics circuit, for adding up the data on flows of whole physical interface, and exports the data on flows after statistics to described memory module;
Described logical channel traffic statistics circuit, for adding up respectively the data on flows of each logical channel, and exports the data on flows after statistics to described memory module;
Described periodic refreshing circuit, be used for according to selected measurement period, the data on flows of described physical interface traffic statistics circuit and described logical channel traffic statistics circuit is exported to described memory module, and refreshed the data on flows of described physical interface traffic statistics circuit and described logical channel traffic statistics circuit;
Described memory module, for storing the data on flows of whole physical interface and the data on flows of each logical channel, and when CPU needs, exports above-mentioned data on flows to CPU;
Described logical channel traffic statistics circuit comprises channel number/address conversioning unit, data delay unit, logical channel flow summer and memory RAM 1;
Wherein, described channel number/address conversioning unit, for converting each logical channel number (LCN) to memory address, and sends described memory address into described memory RAM 1;
Described data delay unit, for postponing the newly-increased data on flows of logical channel after the clock cycle, to export described logical channel flow summer to;
Described logical channel flow summer, after the current data on flows of each logical channel and newly-increased data on flows is cumulative respectively, exports the data on flows of each logical channel to described memory RAM 1;
Described memory RAM 1, for store the data on flows of each logical channel according to the memory address of described channel number/address conversioning unit output, and export the current data on flows of each logical channel to described logical channel flow summer, and data on flows from each logical channel current period to described memory module that export; Described memory RAM 1 comprises read-write control circuit.
2. flow statistic device as claimed in claim 1, is characterized in that, described physical interface comprises chip and outside interface, and the interface between chip internal modules.
3. flow statistic device as claimed in claim 1, is characterized in that, described logical channel comprises the subchannel in physical interface, and the logical subsets of the other types of transmitting in physical interface.
4. flow statistic device as claimed in claim 1, is characterized in that, described physical interface traffic statistics circuit comprises physical interface flow summer and physical interface accumulated value register;
Wherein, described physical interface flow summer, for by the data on flows of physical interface current period and newly-increased data on flows cumulative after, export the data on flows of physical interface to described physical interface accumulated value register;
Described physical interface accumulated value register, for storing the data on flows of physical interface, and to the data on flows of described physical interface flow summer output physical interface current period, and to the data on flows of described memory module output physical interface.
5. flow statistic device as claimed in claim 1, is characterized in that, described memory module is random access memory.
6. a chip that comprises the flow statistic device as described in claim 1 to 5 any one.
7. an equipment that comprises the flow statistic device as described in claim 1 to 5 any one.
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| CN103365965B (en) * | 2013-06-21 | 2016-12-07 | 大唐移动通信设备有限公司 | A kind of aggregation process method and apparatus of data |
| CN105939218B (en) * | 2016-04-15 | 2019-02-19 | 杭州迪普科技股份有限公司 | The statistical method and device of network flow |
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| CN101079623A (en) * | 2006-05-25 | 2007-11-28 | 李�浩 | A large-capacity and no-refresh high-speed statistical counter |
| CN101141296A (en) * | 2007-08-16 | 2008-03-12 | 华为技术有限公司 | Channelizing logic single channel statistic method and apparatus |
| CN101577681A (en) * | 2009-06-02 | 2009-11-11 | 华为技术有限公司 | Flow control method, device and system |
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| CN101079623A (en) * | 2006-05-25 | 2007-11-28 | 李�浩 | A large-capacity and no-refresh high-speed statistical counter |
| CN101005413A (en) * | 2007-01-30 | 2007-07-25 | 华为技术有限公司 | Method and device for realizing multiple logic path counting |
| CN101141296A (en) * | 2007-08-16 | 2008-03-12 | 华为技术有限公司 | Channelizing logic single channel statistic method and apparatus |
| CN101577681A (en) * | 2009-06-02 | 2009-11-11 | 华为技术有限公司 | Flow control method, device and system |
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Date of cancellation: 20190520 Granted publication date: 20141119 Pledgee: Bank of Beijing Limited by Share Ltd Shenzhen branch Pledgor: Shenzhen Hengxin data Limited by Share Ltd Registration number: 2017990000630 |
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Denomination of invention: The invention relates to a flow statistics device, a chip and a device Effective date of registration: 20200826 Granted publication date: 20141119 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: Y2020980005382 |
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| PC01 | Cancellation of the registration of the contract for pledge of patent right |
Date of cancellation: 20210803 Granted publication date: 20141119 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: Y2020980005382 |
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Denomination of invention: A flow statistics device, chip and equipment Effective date of registration: 20210816 Granted publication date: 20141119 Pledgee: Bank of Beijing Limited by Share Ltd. Shenzhen branch Pledgor: Shenzhen Hengyang Data Co.,Ltd. Registration number: Y2021440020082 |