CN102193344B - Method for removing photoresist in deep N-well process - Google Patents
Method for removing photoresist in deep N-well process Download PDFInfo
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- CN102193344B CN102193344B CN 201010131833 CN201010131833A CN102193344B CN 102193344 B CN102193344 B CN 102193344B CN 201010131833 CN201010131833 CN 201010131833 CN 201010131833 A CN201010131833 A CN 201010131833A CN 102193344 B CN102193344 B CN 102193344B
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Abstract
The invention discloses a method for removing photoresist in a deep n-well process. The method comprises the following steps: ashing the surface of a semi-conductor wafer, wherein the ashing treatment comprises: controlling the ashing temperature at the surface of the wafer, such that the wafer is maintained to be under an ashing temperature of lower than 285 DEG C; cleaning the photoresist; and removing photoresist residues after cleaning. In prior arts of manufacturing wafers by using the deep n-well technology, tiny residues on the surfaces of the wafers can not be completely removed through an existing photoresist-removing process. According to the method provided by the present invention, the problem is solved, the consistency of semi-conductor components manufactured through the deep n-well technology is improved, and the performance of the semi-conductor components manufactured through the deep n-well technology is substantially improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, relate in particular to the method that a kind of dark N-well process is removed photoresist.
Background technology
In the semiconductor fabrication process process, owing to adopt dark N trap (Deep N Well) technique can effectively suppress noise transmission, therefore make the low-noise semiconductor device in the dark N-well process of field of semiconductor manufacture widespread use.
Adopting dark N-well process to carry out in the process of semiconductor devices manufacturing, need to remove the photoresist that the mask link is introduced.Before the photoresist on cleaning wafer surface, need to carry out to the photoresist of crystal column surface ashing and process to make photoresist to be easy to clean.Because ashing temperature directly affects the viscosity of photoresist, when ashing temperature was low, photoresist is thickness very, had so just increased the possibility of polluting manufacturing environment.And when ashing temperature was high, photoresist will strengthen at the adhesive ability of crystal column surface, had so just increased the difficulty of removing the crystal column surface photoresist by cleaning link.
Prior art is polluted manufacturing environment in order to prevent photoresist, often adopts higher ashing temperature, so also with regard to the corresponding difficulty of removing the crystal column surface photoresist by cleaning link that increased.Simultaneously, it is relevant with thickness and the adhesive ability of photoresist that photoresist is removed ability, because dark N-well process has adopted thicker photoresist, and the ashing temperature of prior art is higher, when therefore adopting prior art to remove photoresist, it is residual that crystal column surface has the photoresist residue, and the adhesion of these residual small photoresist residues is also relatively strong.The small photoresist residue of the stubbornness that these are residual can affect other process procedures of dark N-well process, and can affect the consistance of the semiconductor devices of manufacturing, it is more to remove behind the photoresist small photoresist residue residual on the crystal column surface, and the consistance of semiconductor devices is just lower.Simultaneously, remove behind the photoresist that residual small photoresist residue can bring the loose point of a device problem to the semiconductor devices of manufacturing on the crystal column surface.
Figure 1A removes behind the photoresist synoptic diagram of residual small photoresist residue on the crystal column surface in the dark N-well process of 65 nanometers of prior art.Shown in Figure 1A, wherein, adopting prior art to remove on semiconductor devices 101A, 102A after photoresist is processed and the 103A all residually has a small photoresist residue 101.Can be found out by Figure 1A, for the dark N-well process that adopts than thick photoresist, along with the increase of photoresist residue 101 residual on the semiconductor devices, the consistance of semiconductor devices just begins to reduce, and the consistance of the semiconductor devices 101A that residual photoresist residue 101 is maximum is minimum.
Figure 1B is the process flow diagram of the dark N-well process photoetching treatment of prior art.As shown in Figure 1B, dark N-well process photoetching treatment is divided into following steps: step 101B photoetching, step 102B Implantation, the ashing of step 103B crystal column surface, step 104B photoresist clean, the check of step 105B technological effect.Because the photoresist that dark N-well process is selected is thicker, therefore there is certain defective among the step 103B of the photoresist of the dark N-well process of prior art removal and the step 104B, it is not good to cause adopting prior art to remove the photoresist removal effect that photoresist processes, have obstinate small photoresist residue and residual and stay the crystal column surface that dark N-well process is made, and then affect other process procedures of dark N-well process, and can affect the consistance of the semiconductor devices of dark N-well process manufacturing, bring the loose point of a device problem for the semiconductor devices of dark N-well process manufacturing.
Therefore, the photoresist removal ability that improves dark N-well process becomes problem demanding prompt solution.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection domain of attempting to determine technical scheme required for protection.
For the photoresist that solves the dark N-well process of prior art is removed the problem that process procedure can't be removed small photoresist residue residual on the dark N-well process crystal column surface fully, improve the consistance of the semiconductor devices of dark N-well process manufacturing, the invention provides a kind of dark N-well process and remove the method for photoresist, the method that described dark N-well process is removed photoresist may further comprise the steps:
Crystal column surface is carried out ashing processes,
Described ashing is processed and is comprised: control the ashing temperature of described crystal column surface, make described crystal column surface keep below 285 ℃ ashing temperature;
Photoresist is carried out cleaning treatment;
Removing is through described cleaned photoresist residue.
Further, described ashing is processed and is also comprised: be filled with oxygen in the ashing process chamber, or the mixed gas of oxygen and nitrogen produces corresponding plasma.
Further, the ashing temperature of the described crystal column surface of described control comprises:
Keeping the heating-up temperature of heating plate is 285 ℃, the position of control wafer jig and described heating plate, or control the heating-up temperature that described combinations is justified the position of anchor clamps and described heating plate and changed described heating plate.
Further, the position of the described wafer jig of described control and described heating plate comprises: make described wafer jig lifting and described heating plate is descended, described wafer jig lifting comprises:
Described wafer jig is risen to 40% to 50% place of the movable distance of described wafer jig by distance described heating plate nearest position,
Described wafer jig is resetted;
Described heating plate descends and comprises:
Described heating plate is dropped to the maximum position place that board allows, after described heating plate drops to the maximum position place that described board allows, keep fixing;
In the process of the position of the described combinations of described control circle anchor clamps and described heating plate, the ultimate range between described wafer jig and described heating plate is 5 centimetres.
Further, described wafer jig kept 30 to 50 seconds at 40% to 50% place of the movable distance of described wafer jig, and described wafer jig kept 5 to 15 seconds at reset position.
Further, describedly photoresist carried out cleaning treatment comprise:
In the first rinse bath, use H
2SO
4And H
2O
2Mixed solution cleaned 4～6 minutes,
In the second rinse bath, use described H
2SO
4And H
2O
2Mixed solution cleaned 4～6 minutes;
Described H
2SO
4And H
2O
2The volume ratio of mixed solution is:
H
2SO
4(98wt％)∶H
2O
2(30wt％)＝5∶1，
Described H
2SO
4And H
2O
2The temperature of mixed solution is 120 ℃ to 130 ℃.
Further, described removing comprises through described cleaned photoresist residue:
Use NH
4OH and H
2O
2Mixed solution is removed described photoresist residue,
Described NH
4OH and H
2O
2The volume ratio of mixed solution is:
NH
4OH (29wt%): H
2O
2(30wt%): H
2O (distilled water),
Described NH
4OH and H
2O
2The temperature of mixed solution is 20 ℃ to 50 ℃,
Described NH
4OH and H
2O
2The time that mixed solution is removed processing is 5 to 15 minutes.
Further:
Described NH
4OH and H
2O
2The temperature of mixed solution is 35 ℃,
Described NH
4OH and H
2O
2The time that mixed solution is removed processing is 10 minutes.
Further, described removing also comprises through described cleaned photoresist residue:
Use ultrasound wave that wafer is added shake in described reset procedure, described hyperacoustic power is 300W to 800W.
The method that dark N-well process according to the present invention is removed photoresist can effectively solve the photoresist of the dark N-well process of prior art and remove the problem that process procedure can't be removed small photoresist residue residual on the dark N-well process crystal column surface fully, improve the consistance of the semiconductor devices that dark N-well process makes, the performance of the semiconductor devices of can the dark N-well process of Effective Raise making.
Description of drawings
Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A removes behind the photoresist synoptic diagram of residual small photoresist residue on the crystal column surface in the dark N-well process of 65 nanometers of prior art;
Figure 1B is the process flow diagram of the dark N-well process photoetching treatment of prior art;
Fig. 2 A is the process flow diagram that dark N-well process according to an embodiment of the invention is removed photoresist;
Fig. 2 B is the synoptic diagram that the ashing of dark N-well process removal photoresist is according to a preferred embodiment of the present invention processed;
Fig. 3 is the design sketch of the crystal column surface made of the method that adopts the dark N-well process of the preferred embodiments of the present invention to remove photoresist.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, detailed step will be proposed, so that how explanation the present invention solves the photoresist of the dark N-well process of prior art to remove the problem that process procedure can't be removed small photoresist residue residual on the dark N-well process crystal column surface fully in following description.Obviously, execution of the present invention is not limited to the specific details that the technician of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other embodiments.
Remove the problem that process procedure can't be removed small photoresist residue residual on the dark N-well process crystal column surface fully for the photoresist that overcomes the dark N-well process of prior art, the method that the present invention proposes a kind of dark N-well process removal photoresist overcomes this problem.
Fig. 2 A is the process flow diagram that dark N-well process according to an embodiment of the invention is removed the method for photoresist, and Fig. 2 B is the synoptic diagram that the ashing of the method for dark N-well process removal photoresist is according to a preferred embodiment of the present invention processed.Shown in Fig. 2 A and Fig. 2 B, the photoresist removal method of present embodiment comprises:
Particularly, step 201A comprises: the ashing temperature on control wafer 203B surface in the ashing processing procedure makes wafer 203B surface keep below 285 ℃ ashing temperature.By the control ashing temperature, make the photoresist on wafer 203B surface keep suitable ashing temperature, the photoresist on wafer 203B surface is removed in follow-up cleaning and removing treatment step easily.For preventing that the too high photoresist that causes of ashing temperature is attached to wafer 203B surface strongly, therefore the ashing temperature with wafer 203B surface is limited to below 285 ℃.Compared to existing technology, ashing temperature of the present invention is lower.What need to describe is, the present invention does not limit the lower limit of ashing temperature, this is because those skilled in the art when carrying out the ashing processing, pollute manufacturing environment for preventing that photoresist from trickling in manufacturing environment, ashing temperature can not established excessively low.And because the difference of various photoresist compositions, concrete ashing temperature lower limit is also different.
Preferably, the ashing processing procedure can comprise: be filled with oxygen in the ashing process chamber, or the mixed gas of oxygen and nitrogen produces corresponding plasma.In the ashing processing procedure, be filled with above-mentioned gas in the ashing process chamber and produce corresponding plasma, can reduce during the cineration technics damage to the dielectric layer sidewall of patterning.Belong to the prior art category owing to produce the process of plasma, therefore obscure with the present invention's generation for preventing, the production process of corresponding plasma is not elaborated.
Preferably, the ashing temperature on control wafer 203B surface can be realized by the following method: keeping the heating-up temperature of heating plate 202B is 285 ℃, the position of control wafer jig 201B and heating plate 202B, or the position of control wafer jig 201B and heating plate 202B and change the heating-up temperature of heating plate 202B.All can effectively reach the purpose of control wafer 203B surface ashing temperature by said method.
Particularly, the position of control wafer jig 201B and heating plate 202B makes wafer 203B surface keep below 285 ℃ ashing temperature.Position by control wafer jig 201B and heating plate 202B can make wafer 203B be in a suitable heating location, and wafer 203B surface just can obtain suitable low ashing temperature like this.Suitable low ashing temperature need to both guarantee that the photoresist on wafer 203B surface can not trickle in manufacturing environment and pollutes manufacturing environment, the photoresist that guarantees again wafer 203B surface can be not too high and be attached to very doughtily wafer 203B surface owing to ashing temperature, thereby make the photoresist on wafer 203B surface be easy to clean and remove.Compared to existing technologies, the ashing temperature that is lower than 285 ℃ of the present invention will be lower than the ashing temperature of prior art.What need to describe is that owing to the photoresist that each semiconductor manufacturer is selected is different, also there is certain difference in the adhesive ability of various photoresists under a certain ashing temperature.Therefore, the present invention does not strictly limit ashing temperature, those skilled in the art's content disclosed according to the present invention and institute's concrete condition with photoresist obtain is lower than that 285 ℃ the photoresist that both guarantees wafer 203B surface can not trickle in manufacturing environment and the pollution manufacturing environment, and the photoresist that guarantees again wafer 203B surface can be not too high owing to ashing temperature and ashing temperature that be attached to very doughtily wafer 203B surface also should be included scope of the present invention in.
Preferably, the temperature of heating plate 202B can remain 285 ℃.Because heating plate 202B is the thermal source that ashing is processed, make the temperature of heating plate 202B remain 285 ℃ and can guarantee that ashing temperature can not surpass 285 ℃, and then the photoresist that can guarantee wafer 203B surface can be not too high and be attached to very doughtily wafer 203B surface owing to ashing temperature.What need to describe is that although preferred embodiment of the present invention remains 285 ℃ for the temperature with heating plate, the present invention is not limited thereto.Those skilled in the art also can be by remaining other temperature with heating plate 202B, adjust simultaneously the distance of wafer chuck 201B and heating plate or keep heating plate 202B and the invariant position of wafer jig 201B and change the heating-up temperature of heating plate 202B, can reach equally the technique effect that makes wafer 203B surface obtain suitable low ashing temperature.The technique scheme that those skilled in the art's content disclosed according to the present invention draws also should be included scope of the present invention in.
According to one embodiment of present invention, the position of control wafer jig 201B and heating plate 202B can comprise: make the wafer jig lifting and heating plate 202B is descended.Wafer jig 201B lifting can comprise:
Wafer jig 201B is risen to 40% to 50% place of the movable distance of wafer jig 201B by the nearest position of distance heating plate 202B, wafer jig 201B is resetted.Heating plate 202B descends and can comprise: heating plate 202B is dropped to the maximum position place that board allows, keep fixing after heating plate 202B drops to the maximum position place that board allows.In the process of the position of controlling wafer jig 201B and heating plate 202B, the ultimate range between wafer jig 201B and heating plate 202B is 5 centimetres.Distance between wafer jig 201B and heating plate 202B is limited in 5 centimetres, is equivalent to define the ultimate range between wafer jig 201B and heating plate 202B.So just define the scope of activities of wafer jig 201B and heating plate 202B, thereby the photoresist that has guaranteed wafer 203B surface can not be difficult to absorbing heat because distance heating plate 202B cross far away, and then causes the ashing temperature of photoresist to cross low and trickling is polluted manufacturing environment in manufacturing environment.
Preferably, wafer jig 201B kept 30 to 50 seconds at 40% to 50% place of the movable distance of wafer jig 201B, and wafer jig 201B kept 5 to 15 seconds at reset position.The ashing of adopting above-mentioned parameter to carry out wafer 203B surface is processed, can reach at short notice the photoresist that guarantees wafer 203B surface and can not cross low the trickling pollute manufacturing environment in manufacturing environment owing to ashing temperature, the photoresist that can guarantee again wafer 203B surface can be not too high and be attached to very doughtily the technique effect on wafer 203B surface owing to ashing temperature.
By aforesaid operations, can effectively change the distance between wafer 203B and heating plate 202B, thereby can effectively control the heating-up temperature of wafer 203B.And then the photoresist that can guarantee wafer 203B surface can be not too high and be attached to very doughtily wafer 203B surface owing to ashing temperature, makes the photoresist on wafer 203B surface be easy to clean.
Particularly, step 202A comprises: use H
2SO
4And H
2O
2Mixed solution cleans wafer 203B.
Preferably, use H
2SO
4And H
2O
2Mixed solution cleans and can comprise wafer 203B: use H in the first rinse bath
2SO
4And H
2O
2Mixed solution cleaned 4～6 minutes.In the second rinse bath, use H
2SO
4And H
2O
2Mixed solution cleaned 4～6 minutes.Adopt acid H
2SO
4And H
2O
2Mixed solution cleans wafer 203B in two rinse baths respectively, can effectively remove most of photoresist on wafer 203B surface.Simultaneously scavenging period is controlled at the purpose that can substantially reach the photoresist of removing most of wafer 203B surface in 4～6 minutes.
The H that this preferred embodiment adopts
2SO
4And H
2O
2The volume ratio of mixed solution is: H
2SO
4(98wt%): H
2O
2(30wt%)=5: 1.Those skilled in the art need to prove, owing to can select the H of Different Weight ratio
2SO
4And H
2O
2Solution disposes H
2SO
4And H
2O
2Mixed solution, at this moment H
2SO
4And H
2O
2Volume ratio also can be different.Therefore adopt the H of other weight ratio
2SO
4And H
2O
2Solution mixes to obtain the given H of this preferred embodiment
2SO
4And H
2O
2The technical scheme of mixed solution also should be included scope of the present invention in.The H that adopts
2SO
4And H
2O
2The temperature of mixed solution is 120 ℃ to 130 ℃.Adopt the H of above-mentioned parameter
2SO
4And H
2O
2Mixed solution cleans the most of photoresist that can effectively remove wafer 203B surface.
Further, in the first rinse bath, use H
2SO
4And H
2O
2Mixed solution cleaned 5 minutes.In the second rinse bath, use H
2SO
4And H
2O
2Mixed solution cleaned 5 minutes.H
2SO
4And H
2O
2The temperature of mixed solution is 125 ℃.Adopt the H of above-mentioned parameter
2SO
4And H
2O
2The cleaning treatment efficient that mixed solution cleans is higher, compares the H that adopts other parameters
2SO
4And H
2O
2Mixed solution cleans, and the cleaning treatment effect of the photoresist of removal is better, and can save the time of technological process.
In this cleaning process, the photoresist on wafer 203B surface can be removed substantially, but because the characteristic of dark N-well process photoresist, through H
2SO
4And H
2O
2It is residual that the cleaned wafer 203B of mixed solution surface still has small photoresist residue.
For removing through H
2SO
4And H
2O
2The small photoresist residue of the wafer 203B remained on surface after mixed solution cleans need to be to through H
2SO
4And H
2O
2Wafer 203B after mixed solution cleans further removes processing.
Preferably, the present invention adopts NH
4OH and H
2O
2Mixed solution is further removed processing to wafer 203B.
Specifically, adopt NH
4OH and H
2O
2It is in order to remove through H that mixed solution is further removed processing to wafer 203B
2SO
4And H
2O
2The small photoresist residue of the wafer 203B remained on surface after mixed solution cleans utilizes the small photoresist residue of wafer 203B surface and wafer 203B remained on surface at alkaline NH
4OH and H
2O
2All with the characteristic of positive electricity, will mutually repel between the small photoresist residue of wafer 203B surface and wafer 203B remained on surface in the mixed solution.
Preferably, NH
4OH and H
2O
2The volume ratio of mixed solution is: NH
4OH (29wt%): H
2O
2(30wt%): H
2O (distilled water)=1: 2: 50.Compare the NH of other volume ratios
4OH and H
2O
2The removing treatment effect that mixed solution is removed adopts the NH of this volume ratio
4OH and H
2O
2The removing Disposal quality that mixed solution is removed is better, and it is higher to remove treatment effeciency.Those skilled in the art need to prove, owing to can select the NH of Different Weight ratio
4OH and H
2O
2Solution disposes NH
4OH and H
2O
2Mixed solution, at this moment NH
4OH and H
2O
2Volume ratio also can be different.Therefore adopt the NH of other weight ratio
4OH and H
2O
2Solution mixes to obtain the given NH of this preferred embodiment
4OH and H
2O
2The technical scheme of mixed solution also should be included scope of the present invention in.NH
4OH and H
2O
2The temperature of mixed solution is 20 ℃ to 50 ℃.Keep 20 ℃ to 50 ℃ can reach well the requirement of removing processing.Wherein, work as NH
4OH and H
2O
2When mixed solution was 35 ℃, it was optimum to remove the effect of processing.NH
4OH and H
2O
2The time that mixed solution is removed processing is 5 to 15 minutes.The time of remove processing is just to reach well the requirement of removing processing in 5 to 15 minutes, can effectively remove residual small photoresist residue on the semiconductor devices that dark N-well process makes, satisfy the performance requirement of the semiconductor devices that dark N-well process makes.
More thorough for the removing that guarantees the photoresist residue, in removing processing procedure, can use ultrasound wave that wafer 203B is added shake to remove the photoresist residue on wafer 203B surface.In removing processing procedure, use ultrasound wave that wafer 203B is added small photoresist residue that shake can make wafer 203B remained on surface effectively from wafer 203B sur-face peeling, so just can effectively reach the purpose of the small photoresist residue of removing wafer 203B remained on surface.
Hyperacoustic power when preferably, using ultrasound wave that wafer 203B is added shake in removing processing procedure is 300W to 800W.Adopt this power bracket can guarantee that wafer 203B fully shakes, can effectively guarantee to remove the efficient of processing.
When dark N-well process crystal column surface being carried out the photoresist removal, the method that adopts present embodiment to provide can be removed small photoresist residue residual on the dark N-well process crystal column surface fully.Remove the method for photoresist by the dark N-well process of present embodiment, can reach the purpose of removing small photoresist residue residual on the dark N-well process crystal column surface fully, and then also just effectively guarantee to remove the completeness of photoresist.Thereby improve the consistance of the semiconductor devices of dark N-well process manufacturing, can effectively improve the performance of the semiconductor devices of dark N-well process manufacturing.
Fig. 3 is the design sketch of the crystal column surface made of the method that adopts the dark N-well process of the preferred embodiments of the present invention to remove photoresist.As shown in Figure 3, can find out, adopt dark N-well process photoresist removal method of the present invention, small photoresist residue is not adhered on wafer 301 and 302 surfaces of dark N-well process manufacturing.The method that dark N-well process of the present invention is removed photoresist has obtained good technique effect.
Need to prove that this preferred embodiment is to make the given optimal technical scheme of board according to the semiconductor that those skilled in the art commonly use.This is not limitation of the present invention, and the content that those skilled in the art are disclosed according to the present invention is also removed the improvement that link carries out in conjunction with the semiconductor fabrication process board of practical operation to the photoresist of concrete dark N trap semiconductor fabrication process and also should be included scope of the present invention in.
The present invention can remove small photoresist residue residual on the dark N-well process crystal column surface fully when dark N-well process crystal column surface is carried out photoetching treatment.Remove the method for photoresist by dark N-well process of the present invention, can reach the purpose of removing small photoresist residue residual on the dark N-well process crystal column surface fully, improve the consistance of the semiconductor devices that dark N-well process makes, the performance of the semiconductor devices of can the dark N-well process of Effective Raise making.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (7)
1. the method for a dark N-well process removal photoresist is characterized in that, said method comprising the steps of:
Crystal column surface is carried out ashing processes,
Described ashing is processed and is comprised: control the ashing temperature of described crystal column surface, make described crystal column surface keep below 285 ℃ ashing temperature;
Photoresist is carried out cleaning treatment;
Removing is through described cleaned photoresist residue, and the ashing temperature of the described crystal column surface of described control comprises:
Keeping the heating-up temperature of heating plate is 285 ℃, the position of control wafer jig and described heating plate, or control the position of described wafer jig and described heating plate and change the heating-up temperature of described heating plate, the position of the described wafer jig of described control and described heating plate comprises: make described wafer jig lifting and described heating plate is descended, described wafer jig lifting comprises:
Described wafer jig is risen to 40% to 50% place of the movable distance of described wafer jig by distance described heating plate nearest position,
Described wafer jig is resetted;
Described heating plate descends and comprises:
Described heating plate is dropped to the maximum position place that board allows, after described heating plate drops to the maximum position place that described board allows, keep fixing;
In the process of the position of the described wafer jig of described control and described heating plate, the ultimate range between described wafer jig and described heating plate is 5 centimetres.
2. dark N-well process according to claim 1 is removed the method for photoresist, it is characterized in that, described ashing is processed and also comprised: be filled with oxygen in the ashing process chamber, or the mixed gas of oxygen and nitrogen produces corresponding plasma.
3. dark N-well process according to claim 1 is removed the method for photoresist, it is characterized in that, described wafer jig kept 30 to 50 seconds at 40% to 50% place of the movable distance of described wafer jig, and described wafer jig kept 5 to 15 seconds at reset position.
4. dark N-well process according to claim 1 is removed the method for photoresist, it is characterized in that, describedly photoresist is carried out cleaning treatment comprises:
In the first rinse bath, use H
2SO
4And H
2O
2Mixed solution cleaned 4～6 minutes,
In the second rinse bath, use described H
2SO
4And H
2O
2Mixed solution cleaned 4～6 minutes;
Described H
2SO
4And H
2O
2The volume ratio of mixed solution is:
H
2SO
4: H
2O
2=5:1, wherein, described H
2SO
4The massfraction of solution is 98%, H
2O
2The massfraction of solution is 30%;
Described H
2SO
4And H
2O
2The temperature of mixed solution is 120 ℃ to 130 ℃.
5. dark N-well process according to claim 1 is removed the method for photoresist, it is characterized in that described removing comprises through described cleaned photoresist residue:
Use NH
4OH and H
2O
2Mixed solution is removed described photoresist residue,
Described NH
4OH and H
2O
2The volume ratio of mixed solution is:
NH
4OH:H
2O
2: H
2O=1:2:50, wherein, described NH
4The massfraction of OH solution is 29%, H
2O
2The massfraction of solution is 30%, described H
2O is distilled water;
Described NH
4OH and H
2O
2The temperature of mixed solution is 20 ℃ to 50 ℃,
Described NH
4OH and H
2O
2The time that mixed solution is removed processing is 5 to 15 minutes.
6. dark N-well process according to claim 5 is removed the method for photoresist, it is characterized in that:
Described NH
4OH and H
2O
2The temperature of mixed solution is 35 ℃,
Described NH
4OH and H
2O
2The time that mixed solution is removed processing is 10 minutes.
7. dark N-well process according to claim 5 is removed the method for photoresist, it is characterized in that described removing also comprises through described cleaned photoresist residue:
Use ultrasound wave that wafer is added shake in described reset procedure, described hyperacoustic power is 300W to 800W.
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| CN104576343B (en) * | 2013-10-29 | 2018-03-06 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of grid oxic horizon |
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| KR100683416B1 (en) * | 2004-11-25 | 2007-02-20 | 피에스케이 주식회사 | Plasma Chamber System And Method Of Ashing A Photoresist Pattern Formed On The Substrate Having Low-k Dielectric Using The Same |
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| CN101458463A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Ashing method |
| CN101546136A (en) * | 2008-03-25 | 2009-09-30 | 中芯国际集成电路制造(上海)有限公司 | Method for removing optical resist |
| CN101592873A (en) * | 2008-05-29 | 2009-12-02 | 中芯国际集成电路制造(北京)有限公司 | Remove the photoresist layer method |
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