CN102184953B - Stress GeOI structure and forming method thereof - Google Patents
Stress GeOI structure and forming method thereof Download PDFInfo
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- CN102184953B CN102184953B CN 201110058127 CN201110058127A CN102184953B CN 102184953 B CN102184953 B CN 102184953B CN 201110058127 CN201110058127 CN 201110058127 CN 201110058127 A CN201110058127 A CN 201110058127A CN 102184953 B CN102184953 B CN 102184953B
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Abstract
The invention provides a stress GeOI structure comprising a silicon substrate, a Ge layer, a grid stack, a channel region, a drain region, a source region, and a plurality of shallow trench isolation (STI) structures, wherein the surface of the silicon substrate is provided with an oxide insulating layer; the Ge layer is formed on the oxide insulating layer, and a first passivation thin layer is formed between the Ge layer and the oxide insulating layer; the grid stack is formed on the Ge layer, the channel region is formed under the grid stack, and the drain region and the source region are formed on two sides of the channel region; and the plurality of STI structures penetrate through the oxide insulating layer and extend into the silicon substrate, and insulating medium materials introducing strain are filled in the STI structures so as to lead the channel region to generate strain. In the embodiment of the invention, the first passivation layer is used for improving the problem of interfacial state between the Ge material and the insulated oxide, thus reducing the leakage and scattering at the interface.
Description
Technical field
The present invention relates to semiconductor design and manufacturing technology field, particularly a kind of strain GeOI (ge-on-insulator) structure and forming method thereof.
Background technology
For a long time, it is constantly scaled that the characteristic size of metal-oxide semiconductor fieldeffect transistor (MOSFET) is being followed so-called Moore's Law (Moore ' s law) always, its operating rate is more and more faster, but, for for Si material itself, close to the dual limit of physics and technology.Thereby people have proposed various methods in order constantly to promote the MOSFET performance of devices, thereby the development of MOSFET device has entered so-called rear mole (More-Than-Moore) epoch.Wherein a kind of fruitful technology based on the high mobility channel engineering of the high carrier mobility material systems such as dissimilar materials structure especially Si base Ge material.For example, with Ge with have a SiO
2It is exactly a kind of Si base Ge material with high hole mobility that the Si sheet Direct Bonding of insulating barrier forms the GeOI structure, has good application prospect.
Existing GeOI structure is with Ge and SiO
2Deng the insulation oxide Direct Bonding, perhaps be formed with GeO on the Ge
2Again with wafer bonding.The shortcoming that prior art exists is, if in the GeOI technology, directly on the insulation oxide substrate, form the Ge material, because the contact interface between Ge material and the insulation oxide is poor, especially interface state density is very high, thereby cause more serious scattering and electric leakage, finally affected device performance.In addition, because the Ge layer is very thin, so the Ge layer is difficult to form strain, and suitable channel strain can effectively improve device performance.
Summary of the invention
Purpose of the present invention is intended to solve at least one of above-mentioned technological deficiency, particularly solve in the present GeOI structure the very poor defective of interfacial state between the Ge and oxide-insulator, and the Ge layer is difficult to form the defective of strain.
For achieving the above object, one aspect of the present invention proposes a kind of strain GeOI structure, and comprising: the surface has the silicon substrate of oxide insulating layer; Be formed on the Ge layer on the described oxide insulating layer, wherein, be formed with the first passivation thin layer between described Ge layer and the described oxide insulating layer; The grid that are formed on the described Ge layer are stacking, and be formed on described grid under stacking channel region and drain region and the source region of channel region both sides; With a plurality of shallow trench isolations from sti structure, described a plurality of sti structures penetrate described oxide insulating layer and extend in the described silicon substrate, and are filled with the dielectric material of introducing strain in the described sti structure so that described channel region produces strain.
In one embodiment of the invention, described the first passivation thin layer is strontium germanide thin layer, barium germanide thin layer, GeSi passivation thin layer or Si thin layer.
In one embodiment of the invention, also comprise: be formed on the second passivation thin layer on the described Ge layer, described the second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer.
In one embodiment of the invention, link to each other by the bonding mode between described oxide insulating layer and the described Ge layer.
In one embodiment of the invention, described dielectric material is silicon nitride.
The present invention has also proposed a kind of formation method of strain GeOI structure on the other hand, may further comprise the steps: form the Ge layer on the first substrate; The first surface of described Ge layer is processed to form the first passivation thin layer; With described the first substrate, described Ge layer and the upset of described the first passivation thin layer and be transferred to the silicon substrate that the surface has oxide insulating layer; Remove described the first substrate; The grid that formation is positioned on the described Ge layer are stacking, and form and to be positioned at described grid and to form channel region under stacking, and the drain region and the source region that are positioned at described channel region both sides; The described surface of etching has the silicon substrate of oxide insulating layer to form a plurality of sti structures, and described a plurality of sti structures penetrate described oxide insulating layer and extend in the described silicon substrate; Introduce the dielectric material of strain so that described channel region produces strain with filling in described a plurality of sti structures.
In one embodiment of the invention, described the first passivation thin layer is strontium germanide thin layer, barium germanide thin layer, GeSi passivation thin layer or Si thin layer.
In one embodiment of the invention, after described removal the first substrate, also comprise: the second surface of described Ge layer is processed to form the second passivation thin layer, and described the second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer.
In one embodiment of the invention, by the bonding mode described the first passivation thin layer is linked to each other with described oxide insulating layer.
In one embodiment of the invention, described dielectric material is silicon nitride.
Can improve interfacial state problem between Ge material and the insulation oxide by the first passivation layer in embodiments of the present invention, thereby reduce this electric leakage and scattering at the interface.In the preferred embodiment of the present invention, can improve interfacial state problem between Ge material and the insulation oxide by the first passivation layer, thereby reduce this electric leakage and scattering at the interface.In the preferred embodiment of the present invention, the passivation thin layer that strontium germanide or barium germanide form belongs to semiconductor, therefore not only can improve the interfacial state problem between Ge material and the insulation oxide, reduce this electric leakage and scattering at the interface, also can excessively not reduce in addition the mobility performance of Ge material.In addition, a plurality of sti structures of being filled by the dielectrics with strain by the embodiment of the invention make the Ge channel region of grid under stacking produce required strain, thereby improve device performance.
The aspect that the present invention adds and advantage in the following description part provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or the additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the schematic diagram of the strain GeOI structure of the embodiment of the invention;
Fig. 2-7 is the intermediate steps schematic diagram of formation method of the strain GeOI structure of the embodiment of the invention.
Embodiment
The below describes embodiments of the invention in detail, and the example of described embodiment is shown in the drawings, and wherein identical or similar label represents identical or similar element or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the present invention, and can not be interpreted as limitation of the present invention.
Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter parts and the setting of specific examples are described.Certainly, they only are example, and purpose does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between the various embodiment that discuss of institute and/or the setting.In addition, the various specific technique that the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
As shown in Figure 1, be the schematic diagram of the strain GeOI structure of the embodiment of the invention.This GeOI structure comprises that there is the silicon substrate 1100 and the Ge layer 1300 that is formed on the oxide insulating layer 1200 of oxide insulating layer 1200 on the surface, wherein, is formed with the first passivation thin layer 1400 between Ge layer 1300 and the oxide insulating layer 1200.In embodiments of the present invention, the first passivation thin layer 1300 is for adopting strontium Sr or barium Ba to be strontium germanide GeSr to what the first surface of Ge layer 1200 was processed formation
xOr barium germanide GeBa
xCertainly in other embodiments of the invention, the first passivation thin layer 1400 also can be GeSi passivation thin layer or Si thin layer.In one embodiment of the invention, the surface has the silicon substrate 1100 of oxide insulating layer to comprise the Si substrate, and is formed on the SiO on the Si substrate
2Insulating barrier.Because the passivation thin layer that strontium germanide or barium germanide form belongs to semiconductor, therefore not only can improve the interfacial state problem between Ge material and the insulation oxide, reduce this electric leakage and scattering at the interface, also can excessively not reduce in addition the mobility performance of Ge material.In embodiments of the present invention, in order to generate the Ge channel device with strain, this strain GeOI structure comprises that also a plurality of shallow trench isolations are from sti structure 1900, a plurality of sti structures 1900 penetrate oxide insulating layer 1200 and extend in the silicon substrate 1100, and are filled with the dielectric material of introducing strain in the sti structure 1900 so that channel region produces strain.In one embodiment of the invention, the dielectric that has a strain can be silicon nitride.But need to prove that silicon nitride described herein does not refer in particular to the SiN of 1: 1 ratio, particularly, can adjust the strain of its generation by the relative scale of adjusting each component in the silicon nitride, for example can produce compressive strain or tensile strain.
Therefore, sti structure 1900 not only can provide the buffer action between the device in embodiments of the present invention, can also make it produce strain to the channel region stress application, thereby improve device performance.
In one embodiment of the invention, this strain GeOI structure also comprises the second passivation thin layer 1500 that is formed on the described Ge layer.Wherein, similarly, the second passivation thin layer 1500 adopts strontium Sr or barium Ba to be strontium germanide or barium germanide to what the second surface of Ge layer 1400 was processed formation.Certainly in other embodiments of the invention, also can form by other means the second passivation thin layer 1500, namely this second passivation thin layer 1500 is GeSi.
In one embodiment of the invention, this GeOI structure also comprises the gate dielectric layer 1600 that is formed on the second passivation thin layer 1500 and the gate electrode 1700 that is formed on the gate dielectric layer 1600, and is formed on source electrode and drain electrode 1800 among the Ge layer 1400.
Shown in Fig. 2-7, be the intermediate steps schematic diagram of the formation method of the strain GeOI structure of the embodiment of the invention.The method may further comprise the steps:
Step S101 provides the first substrate 2000, and wherein, the first substrate 2000 is Si substrate or Ge substrate.Certainly in other embodiments of the invention, also can adopt other substrates.The first substrate 2000 is reusable in embodiments of the present invention, thereby reduces manufacturing cost.
Step S102 forms Ge layer 1300, as shown in Figure 2 on the first substrate 2000.
Step S103 adopts strontium Sr or barium Ba that the first surface of Ge layer 1300 is processed to form the first passivation thin layer 1400, and this first passivation thin layer 1400 is strontium germanide or barium germanide, as shown in Figure 3.Certainly in other embodiments of the invention, the first passivation thin layer 1400 also can be GeSi passivation thin layer or Si thin layer, for example Ge layer 1300 is carried out the Siization processing, perhaps deposit Si thin layer on Ge layer 1300.
Step S104 is with the first substrate 2000, Ge layer 1300 and 1400 upsets of the first passivation thin layer and be transferred to the silicon substrate 1100 that there is oxide insulating layer 1200 on the surface, as shown in Figure 4.In one embodiment of the invention, by the bonding mode the first passivation thin layer 1300 is linked to each other with oxide insulating layer 1200.
Step S105 removes the first substrate 2000, as shown in Figure 5.
Step S106 selectively, adopts strontium or barium that the second surface of Ge layer 1400 is processed to form the second passivation thin layer 1500, and this second passivation thin layer 1500 is strontium germanide or barium germanide, as shown in Figure 6.Similarly, in other embodiments of the invention, also can form by other means the second passivation thin layer 1500, namely this second passivation thin layer 1500 is GeSi.
Step S107, formation is positioned at grid stacking (being gate dielectric layer 1600 and gate electrode 1700) on the second passivation thin layer 1500 and the side wall of the stacking both sides of grid, and form and to be positioned at grid and to form channel region under stacking, and the drain region and the source region 1800 that are positioned at the channel region both sides.In an embodiment of the present invention, grid formation stacking and source region and drain region both can have been adopted front grid (gate-first) technique, also can adopt rear grid (gate-last) technique.
Step S108, etching the second passivation thin layer 1500, Ge layer 1300, the first passivation thin layer 1400 and oxide insulating layer 1200 are to form a plurality of sti structures 1900, a plurality of sti structures 1900 penetrate oxide insulating layer 1200 and extend in the silicon substrate 1100, as shown in Figure 7.
Step S109 fills silicon nitride material so that channel region produces strain, as shown in Figure 1 in a plurality of sti structures 1900.
Can improve interfacial state problem between Ge material and the insulation oxide by the first passivation layer in embodiments of the present invention, thereby reduce this electric leakage and scattering at the interface.In the preferred embodiment of the present invention, the passivation thin layer that strontium germanide or barium germanide form belongs to semiconductor, therefore not only can improve the interfacial state problem between Ge material and the insulation oxide, reduce this electric leakage and scattering at the interface, also can excessively not reduce in addition the mobility performance of Ge material.In addition, a plurality of sti structures by the embodiment of the invention make the Ge channel region of grid under stacking produce required strain, thereby improve device performance.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification to these embodiment that scope of the present invention is by claims and be equal to and limit.
Claims (8)
1. a strain GeOI structure is characterized in that, comprising:
The surface has the silicon substrate of oxide insulating layer;
Be formed on the Ge layer on the described oxide insulating layer, wherein, be formed with the first passivation thin layer between described Ge layer and the described oxide insulating layer;
The grid that are formed on the described Ge layer are stacking, and be formed on described grid under stacking channel region and drain region and the source region of channel region both sides; With
A plurality of shallow trench isolations are from sti structure, and described a plurality of sti structures penetrate described oxide insulating layer and extend in the described silicon substrate, and are filled with the dielectric material of introducing strain in the described sti structure so that described channel region produces strain,
Wherein, described the first passivation thin layer is strontium germanide thin layer or barium germanide thin layer.
2. strain GeOI structure as claimed in claim 1 is characterized in that, also comprises:
Be formed on the second passivation thin layer on the described Ge layer, described the second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer, and wherein, described grid are stacking to be formed on described the second passivation thin layer.
3. strain GeOI structure as claimed in claim 1 is characterized in that, links to each other by the bonding mode between described oxide insulating layer and described the first passivation thin layer.
4. strain GeOI structure as claimed in claim 1 is characterized in that, described dielectric material is silicon nitride.
5. the formation method of a strain GeOI structure is characterized in that, may further comprise the steps:
On the first substrate, form the Ge layer;
The first surface of described Ge layer is processed to form the first passivation thin layer;
With described the first substrate, described Ge layer and the upset of described the first passivation thin layer and be transferred to the silicon substrate that the surface has oxide insulating layer;
Remove described the first substrate;
The grid that formation is positioned on the described Ge layer are stacking, and form be positioned at described grid under stacking channel region and drain region and the source region that is positioned at described channel region both sides;
The described Ge layer of etching, described the first passivation thin layer and described surface have the silicon substrate of oxide insulating layer to form a plurality of sti structures, and described a plurality of sti structures penetrate described oxide insulating layer and extend in the described silicon substrate; With
In described a plurality of sti structures, fill the dielectric material of introducing strain so that described channel region produces strain,
Wherein, described the first passivation thin layer is strontium germanide thin layer or barium germanide thin layer.
6. the formation method of strain GeOI structure as claimed in claim 5 is characterized in that, after described removal the first substrate and before the described grid of formation are stacking, also comprises:
The second surface of described Ge layer is processed to form the second passivation thin layer, and described the second passivation thin layer is strontium germanide thin layer, barium germanide thin layer or GeSi passivation thin layer.
7. the formation method of strain GeOI structure as claimed in claim 5 is characterized in that, by the bonding mode described the first passivation thin layer is linked to each other with described oxide insulating layer.
8. the formation method of strain GeOI structure as claimed in claim 5 is characterized in that, described dielectric material is silicon nitride.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110058127 CN102184953B (en) | 2011-03-10 | 2011-03-10 | Stress GeOI structure and forming method thereof |
| PCT/CN2011/078946 WO2012119418A1 (en) | 2011-03-10 | 2011-08-25 | Strained ge-on-insulator structure and method for forming the same |
| US13/263,227 US8890209B2 (en) | 2011-03-10 | 2011-08-25 | Strained GE-ON-insulator structure and method for forming the same |
| US13/263,222 US8786017B2 (en) | 2011-03-10 | 2011-08-25 | Strained Ge-on-insulator structure and method for forming the same |
| PCT/CN2011/078944 WO2012119417A1 (en) | 2011-03-10 | 2011-08-25 | Strained ge-on-insulator structure and method for forming the same |
| PCT/CN2011/078948 WO2012119419A1 (en) | 2011-03-10 | 2011-08-25 | Strained ge-on-insulator structure and method for forming the same |
| US13/263,236 US8704306B2 (en) | 2011-03-10 | 2011-08-25 | Strained Ge-on-insulator structure and method for forming the same |
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| CN 201110058127 CN102184953B (en) | 2011-03-10 | 2011-03-10 | Stress GeOI structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101292342A (en) * | 2005-10-19 | 2008-10-22 | Soi科技公司 | Treating a germanium layer bonded to a substrate |
| CN101882624A (en) * | 2010-06-29 | 2010-11-10 | 清华大学 | Structure with high-Ge strained layer formed on insulating substrate and forming method |
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| US20070057320A1 (en) * | 2005-09-12 | 2007-03-15 | Tetsuji Ueno | Semiconductor Devices with Stressed Channel Regions and methods Forming the Same |
| FR2933534B1 (en) * | 2008-07-03 | 2011-04-01 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101292342A (en) * | 2005-10-19 | 2008-10-22 | Soi科技公司 | Treating a germanium layer bonded to a substrate |
| CN101882624A (en) * | 2010-06-29 | 2010-11-10 | 清华大学 | Structure with high-Ge strained layer formed on insulating substrate and forming method |
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