FR2933534B1 - METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE - Google Patents

METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE

Info

Publication number
FR2933534B1
FR2933534B1 FR0854510A FR0854510A FR2933534B1 FR 2933534 B1 FR2933534 B1 FR 2933534B1 FR 0854510 A FR0854510 A FR 0854510A FR 0854510 A FR0854510 A FR 0854510A FR 2933534 B1 FR2933534 B1 FR 2933534B1
Authority
FR
France
Prior art keywords
substrate
manufacturing
germanium layer
germanium
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0854510A
Other languages
French (fr)
Other versions
FR2933534A1 (en
Inventor
Nicolas Daval
Oleg Kononchuk
Eric Guiot
Cecile Aulnette
Fabrice Lallement
Christophe Figuet
Didier Landru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0854510A priority Critical patent/FR2933534B1/en
Application filed by Soitec SA filed Critical Soitec SA
Priority to PCT/EP2009/057293 priority patent/WO2010000596A1/en
Priority to EP09772296A priority patent/EP2294611A1/en
Priority to KR1020107024928A priority patent/KR20110003522A/en
Priority to CN2009801145931A priority patent/CN102017124A/en
Priority to JP2011512155A priority patent/JP2011522432A/en
Priority to US12/937,920 priority patent/US20110183493A1/en
Publication of FR2933534A1 publication Critical patent/FR2933534A1/en
Application granted granted Critical
Publication of FR2933534B1 publication Critical patent/FR2933534B1/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
FR0854510A 2008-07-03 2008-07-03 METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE Expired - Fee Related FR2933534B1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
FR0854510A FR2933534B1 (en) 2008-07-03 2008-07-03 METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE
EP09772296A EP2294611A1 (en) 2008-07-03 2009-06-12 Process for manufacturing a structure comprising a germanium layer on a substrate
KR1020107024928A KR20110003522A (en) 2008-07-03 2009-06-12 Process for manufacturing a structure comprising a germanium layer on a substrate
CN2009801145931A CN102017124A (en) 2008-07-03 2009-06-12 Process for manufacturing a structure comprising a germanium layer on a substrate
PCT/EP2009/057293 WO2010000596A1 (en) 2008-07-03 2009-06-12 Process for manufacturing a structure comprising a germanium layer on a substrate
JP2011512155A JP2011522432A (en) 2008-07-03 2009-06-12 Manufacturing process for a structure containing a germanium layer on a substrate
US12/937,920 US20110183493A1 (en) 2008-07-03 2009-06-12 Process for manufacturing a structure comprising a germanium layer on a substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0854510A FR2933534B1 (en) 2008-07-03 2008-07-03 METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE

Publications (2)

Publication Number Publication Date
FR2933534A1 FR2933534A1 (en) 2010-01-08
FR2933534B1 true FR2933534B1 (en) 2011-04-01

Family

ID=40032913

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0854510A Expired - Fee Related FR2933534B1 (en) 2008-07-03 2008-07-03 METHOD FOR MANUFACTURING A STRUCTURE COMPRISING A GERMANIUM LAYER ON A SUBSTRATE

Country Status (7)

Country Link
US (1) US20110183493A1 (en)
EP (1) EP2294611A1 (en)
JP (1) JP2011522432A (en)
KR (1) KR20110003522A (en)
CN (1) CN102017124A (en)
FR (1) FR2933534B1 (en)
WO (1) WO2010000596A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102184954B (en) * 2011-03-10 2013-03-27 清华大学 Ge channel device and forming method thereof
CN102184953B (en) * 2011-03-10 2013-03-27 清华大学 Stress GeOI structure and forming method thereof
FR2977069B1 (en) 2011-06-23 2014-02-07 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE USING TEMPORARY COLLAGE
CN102420167A (en) * 2011-12-05 2012-04-18 中国科学院微电子研究所 Reduction method for germanium substrate on insulator
FR2995447B1 (en) 2012-09-07 2014-09-05 Soitec Silicon On Insulator METHOD FOR SEPARATING AT LEAST TWO SUBSTRATES ACCORDING TO A CHOSEN INTERFACE
KR102150252B1 (en) 2013-11-12 2020-09-02 삼성전자주식회사 Method of manufacturing semiconductor device
US9384964B1 (en) 2014-08-01 2016-07-05 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
CN104701425A (en) * 2015-04-08 2015-06-10 常州时创能源科技有限公司 Diffusion post treatment technique of crystalline silicon solar cell
KR102342850B1 (en) * 2015-04-17 2021-12-23 삼성전자주식회사 Curing method of dielectric layer for manufacturing semiconductor device
KR101889352B1 (en) 2016-09-13 2018-08-20 한국과학기술연구원 Semicondutor device including strained germanium and method for manufacturing the same

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7084460B2 (en) * 2003-11-03 2006-08-01 International Business Machines Corporation Method for fabricating SiGe-on-insulator (SGOI) and Ge-on-insulator (GOI) substrates
US6958286B2 (en) * 2004-01-02 2005-10-25 International Business Machines Corporation Method of preventing surface roughening during hydrogen prebake of SiGe substrates
US7495313B2 (en) * 2004-07-22 2009-02-24 Board Of Trustees Of The Leland Stanford Junior University Germanium substrate-type materials and approach therefor
EP1659623B1 (en) * 2004-11-19 2008-04-16 S.O.I. Tec Silicon on Insulator Technologies S.A. Method for fabricating a germanium on insulator (GeOI) type wafer
JP2006270000A (en) * 2005-03-25 2006-10-05 Sumco Corp PROCESS FOR PRODUCING STRAINED Si-SOI SUBSTRATE AND STRAINED Si-SOI SUBSTRATE PRODUCED BY THAT METHOD
FR2892230B1 (en) * 2005-10-19 2008-07-04 Soitec Silicon On Insulator TREATMENT OF A GERMAMIUM LAYER
US7767541B2 (en) * 2005-10-26 2010-08-03 International Business Machines Corporation Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
EP2095415B1 (en) * 2006-12-26 2010-10-27 S.O.I.Tec Silicon on Insulator Technologies Method for producing a semiconductor-on-insulator structure
FR2911430B1 (en) * 2007-01-15 2009-04-17 Soitec Silicon On Insulator "METHOD OF MANUFACTURING A HYBRID SUBSTRATE"

Also Published As

Publication number Publication date
WO2010000596A1 (en) 2010-01-07
CN102017124A (en) 2011-04-13
JP2011522432A (en) 2011-07-28
KR20110003522A (en) 2011-01-12
EP2294611A1 (en) 2011-03-16
US20110183493A1 (en) 2011-07-28
FR2933534A1 (en) 2010-01-08

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Legal Events

Date Code Title Description
CD Change of name or company name

Owner name: SOITEC, FR

Effective date: 20120423

ST Notification of lapse

Effective date: 20140331