CN102184887B - For the formation method of flash memory fleet plough groove isolation structure - Google Patents
For the formation method of flash memory fleet plough groove isolation structure Download PDFInfo
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- CN102184887B CN102184887B CN201110117352.1A CN201110117352A CN102184887B CN 102184887 B CN102184887 B CN 102184887B CN 201110117352 A CN201110117352 A CN 201110117352A CN 102184887 B CN102184887 B CN 102184887B
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Abstract
A kind of for improving the formation method of the fleet plough groove isolation structure of flash memory " smiling face " effect, comprising: provide Semiconductor substrate, described semiconductor substrate surface is formed with tunnel oxide and floating gate polysilicon layer successively; Form hard mask layer on described floating gate polysilicon layer surface, and etch described hard mask layer, floating gate polysilicon layer, tunnel oxide, Semiconductor substrate successively, in described Semiconductor substrate, form shallow trench; Situ steam generating process is adopted to form the cushion oxide layer covering described shallow trench surface; Chemical vapor deposition is adopted to form the spacer medium layer of filling full described shallow trench." smiling face " problem of the floating gate tunneling oxide that traditional handicraft is brought effectively can be improved by the formation method of the fleet plough groove isolation structure for flash memory provided by the present invention, improve programming and the efficiency of erasing of flash memory, increase the read current under flash memory erases state, thus reach the object increasing window memory.
Description
Technical field
The present invention relates to the formation method of fleet plough groove isolation structure, particularly for the formation method of the fleet plough groove isolation structure of flash memory.
Background technology
In current semiconductor industry, integrated circuit (IC) products mainly can be divided into three major types type: logic, memory and analog circuit, and wherein memory device account for sizable ratio in integrated circuit (IC) products.And in memory device, the development of flash memory (flashmemory) is particularly rapid in recent years.Its main feature is the information that can keep for a long time when not powering up storing, have integrated level high, faster access speed, be easy to erasing and the multiple advantages such as rewriting, be thus widely used in the multinomial field such as microcomputer, Automated condtrol.
The standard physical structure of flash memory is called flash cell (bit).The structure of flash cell is different from conventional MOS transistor.Separated by gate insulator between the grid (gate) of conventional MOS transistor and conducting channel, be generally oxide layer (oxide); And flash cell layer of substance more than between control gate (CG:controlgate is equivalent to the grid of conventional MOS transistor) and conducting channel, be referred to as floating boom (FG:floatinggate).Due to the existence of floating boom, make flash memory can complete three kinds of basic manipulation modes: i.e. reading and writing, erasing.Even if when not having power supply to supply, the existence of floating boom can keep the integrality storing data.Isolate with fleet plough groove isolation structure (STI) between adjacent flash cell.
Fig. 1 to Fig. 3 is the generalized section of the formation method of shallow trench isolation structure between the flash cell of existing flash memory.
Please refer to Fig. 1, provide substrate 200, described substrate 200 surface is formed with tunnel oxide 210, polysilicon layer 220, silicon nitride layer 240 successively, successively etch nitride silicon layer 240, polysilicon layer 220, tunnel oxide 210, forms shallow trench 230.
With reference to figure 2, adopt thermal oxidation technology, form the cushion oxide layer 250 covering described shallow trench 230.
With reference to figure 3, form the spacer medium layer 260 of filling full described shallow trench 230.
But find in practice, said method is adopted to form the flash memory of fleet plough groove isolation structure, due to tunnel oxide " smiling face " problem that thermal oxidation process causes, namely the tunnel oxide of shallow trench both sides is thickening, reduce control gate and source, leakage to the coupling coefficient of floating boom, the programming of device and efficiency of erasing are reduced, and the read current after causing device to be wiped reduce, and reduces the operation window of memory device.
The method of existing solution smiling face problem is: first form fleet plough groove isolation structure, the filled media floor height of described fleet plough groove isolation structure is in Semiconductor substrate; Form the polysilicon layer covering Semiconductor substrate again, then milled processed is carried out to formed polysilicon layer, and with described filled media layer for polish stop layer.But the polysilicon layer formed by said method is in uneven thickness.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of the fleet plough groove isolation structure for flash memory, adopt described method effectively can improve " smiling face " problem of the floating gate tunneling oxide layer that traditional handicraft is brought, improve programming and the efficiency of erasing of flash memory, increase the read current under flash memory erases state, thus reach the object increasing window memory.
For solving the problem, the invention provides a kind of formation method of the fleet plough groove isolation structure for flash memory, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with tunnel oxide and floating gate polysilicon layer successively;
Form hard mask layer on described floating gate polysilicon layer surface, and etch described floating gate polysilicon layer, tunnel oxide, Semiconductor substrate successively, in described Semiconductor substrate, form shallow trench;
Situ steam generating process is adopted to form the cushion oxide layer covering described shallow trench surface;
Form the spacer medium layer of filling full described shallow trench.
Preferably, the thickness of described tunnel oxide is 70-120 dust.
Preferably, the formation process of described tunnel oxide is dry method thermal oxide growth technique.
Preferably, the temperature forming described cushion oxide layer is 900 degree to 1200 degree.
Preferably, the process pressure of described situ steam generating process is 0.1Torr to 100Torr, and reacting gas is H
2, O
2with N
2mist, mixed gas flow is 0.1SLM to 10SLM.
Preferably, the process pressure of described chemical vapor deposition generating process is 0.1Torr to 100Torr, and reacting gas is SiH
4with O
2mist, SiH
4with O
2mist gas flow be 0.1SLM to 50SLM.
Preferably, the reaction time of described situ steam generating process is 1-10s.
Preferably, the thickness of described cushion oxide layer is 50-200 dust.
Preferably, chemical vapor deposition is adopted to form the spacer medium layer of filling full described shallow trench.
Preferably, the depositing operation of described floating gate polysilicon layer is chemical vapour deposition technique.
Preferably, the thickness of described floating gate polysilicon layer is 100-1000 dust.
Compared with prior art, the present invention has the following advantages:
The present invention adopt situ steam generating process be formed at the shallow trench in Semiconductor substrate surface formed cushion oxide layer.Because the deposition velocity that employing situ steam generating process forms described cushion oxide layer is fast, required sedimentation time is short, so the diffusion relative to the Semiconductor substrate of described floating gate polysilicon layer and shallow trench both sides of oxygen in reacting gas can be reduced, and the oxidation reaction between the oxygen therefore reduced in reacting gas and the Semiconductor substrate of described floating gate polysilicon layer and shallow trench both sides, thus improve the homogeneity of the thickness of tunnel oxide.And therefore effectively improve " smiling face " problem of the tunnel oxide of the floating boom that traditional handicraft is brought, improve programming and the efficiency of erasing of flash memory, increase the read current under flash memory erases state, thus reach the object increasing window memory.
Accompanying drawing explanation
Fig. 1 to Fig. 3 is the generalized section of the existing formation method of shallow trench isolation structure for flash memory;
Fig. 4 is the schematic flow sheet of the formation method of shallow trench isolation structure for flash memory that one embodiment of the invention provides;
Fig. 5 to Fig. 8 is the generalized section of the formation method of the fleet plough groove isolation structure for flash memory that one embodiment of the invention provides.
Embodiment
From background technology, floating gate tunneling oxide " smiling face " problem that existing flash memory causes in shallow isolating trough oxygen pad layer forming process, reduce control gate and source and drain to the coupling coefficient of floating boom, the programming of device and efficiency of erasing are reduced, and the read current after causing device to be wiped reduces, and reduces the operation window of memory device.The present inventor studies for the problems referred to above, finds that the formation method by changing the isolation structure in flash memory between adjacent flash cell can reduce the read current of flash memory, and improves the efficiency of write and erasing.
Inventor studies for the problems referred to above, think in the formation method of the isolation structure in existing flash memory between adjacent flash cell, formed in the step of cushion oxide layer adopting thermal oxidation technology, floating gate polysilicon layer and semiconductor substrate section material participate in oxidation reaction, cause the thickness of tunnel oxide to increase.Specifically please refer to Fig. 1 to Fig. 3.
As depicted in figs. 1 and 2, formed in the step of cushion oxide layer 250 adopting thermal oxidation technology, there is oxidation reaction and generate oxide in the substrate 200 that oxygen and shallow trench 230 expose and floating gate polysilicon layer 220, formed cushion oxide layer 250 is had between floating gate polysilicon layer 220 and tunnel oxide 210, and the projection 280 between tunnel oxide and substrate 200.
As described in Figure 3, described protruding 280 cause described tunnel oxide 210 thickening near the part of spacer medium layer 260.Tunnel oxide 210 is thickening, causes the control gate of flash memory and source and drain to reduce the coupling coefficient of floating boom, thus the programming of device and efficiency of erasing are reduced.Inventor after further research, provides a kind of formation method of the fleet plough groove isolation structure for flash memory in the present invention.The formation method of the fleet plough groove isolation structure for flash memory provided by the present invention is for improving " smiling face " effect of flash memory.
Adopt the formation method of the fleet plough groove isolation structure in flash memory provided by the present invention can improve " smiling face " effect of existing flash memory, improve the performance of flash memory with this.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when describing the embodiment of the present invention in detail; for ease of explanation; represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of protection of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Fig. 4 is the schematic flow sheet of the formation method of the fleet plough groove isolation structure for flash memory that one embodiment of the present of invention provide, and comprising:
Step S101, provides Semiconductor substrate, and described semiconductor substrate surface is formed with tunnel oxide and floating gate polysilicon layer successively;
Step S102, forms hard mask layer on described floating gate polysilicon layer surface, and etches described hard mask layer, floating gate polysilicon layer, tunnel oxide, Semiconductor substrate successively, in described Semiconductor substrate, form shallow trench;
Step S103, adopts situ steam generating process to form the cushion oxide layer covering described shallow trench surface;
Step S104, forms the spacer medium layer of filling full described shallow trench.
First, with reference to figure 5, perform step S101, provide Semiconductor substrate 100, described Semiconductor substrate 100 surface is formed with tunnel oxide 110 and floating gate polysilicon layer 120 successively.
Concrete, semiconductor base 100 can be silicon or the SiGe (SiGe) of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI), or other material can also be comprised, such as indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide.Although there is described herein several examples of the material that can form semiconductor base 100, all the spirit and scope of the present invention can be fallen into as any material of semiconductor base.
In the present embodiment, adopt thermal oxidation to form described tunnel oxide 110, the process gas forming described tunnel oxide 110 comprises silicon-containing gas and oxygen, and described silicon-containing gas is SiH
2cl
2or SiH
2.By the restriction of vacuum condition, in process gas, also comprise N
2.The thickness of the tunnel oxide 110 formed is 70-120 dust.The thickness of described tunnel oxide 110 is too large, the distance between floating gate polysilicon layer 120 (follow-up through over etching formation floating boom) and Semiconductor substrate 100 can be increased, thus the electric capacity reduced between floating gate polysilicon layer 120 and Semiconductor substrate 100, the efficiency that the reading and writing reducing flash memory enter and wipe.
In a preferred embodiment of the invention, annealing in process can also be carried out to formed tunnel oxide 250.
In the present embodiment, the formation process of described floating gate polysilicon layer 120 is chemical vapor deposition method, and the thickness of described floating gate polysilicon layer 120 is 100-1000 dust.The effect of described floating gate polysilicon layer 120 forms floating boom in subsequent process.
With reference to figure 6, perform step S102, form hard mask layer 130 on described floating gate polysilicon layer 120 surface, and etch described hard mask layer 130, floating gate polysilicon layer 120, tunnel oxide 110, Semiconductor substrate 100 successively, in described Semiconductor substrate 100, form shallow trench 140.
In the present embodiment, the material of described hard mask layer 130 is silicon nitrides.Described hard mask layer 130 is used as polish stop layer in the process of grinding at subsequent chemical mechanical.
In the present embodiment, form the photoresist layer containing opening on described hard mask layer 130 surface, position and the width of the shallow trench of the position of described opening and width and follow-up formation are corresponding.Then hard mask layer 130, floating gate polysilicon layer 120, tunnel oxide 110, Semiconductor substrate 100 is etched successively along described opening, until form the shallow trench 140 of desired depth in described Semiconductor substrate 100.
Described etching can utilize method well known to those skilled in the art to etch, such as, utilize dry plasma etch.Specifically comprise: select inductively coupled plasma type etching apparatus, in etching process, such as etching gas comprises argon Ar and tetrafluoromethane CF
4, perfluoroethane C
2f
6with fluoroform CHF
3deng fluoro-gas.In reative cell, pass into above-mentioned gas, wherein argon Ar plays the effect of dilution etching gas, and its flow is 100sccm ~ 300sccm simultaneously.Rise in the gas of corrasion, tetrafluoromethane CF
4flow be 50sccm ~ 100sccm; Perfluoroethane C
2f
6flow be 100sccm ~ 400sccm; Fluoroform CHF
3flow be 10sccm ~ 100sccm.Be the power output of the radio frequency power source of plasma by described gas ionization in reative cell be 50W ~ 1000W; The power output in RF bias power source is 50W ~ 250W.Pressure in reative cell is set to 50mTorr ~ 200mTorr, and semiconductor base temperature controls between 20 DEG C and 90 DEG C.The process of above-mentioned plasma etching is a kind of anisotropic etching, and the groove after the acting in conjunction of etching gas and diluent gas makes etching is inclined-plane.Described etching technics can also carry out in other etching apparatus, as capacitance coupling plasma type etching apparatus, inductively coupled plasma etching equipment.
With reference to figure 7, perform step S103, adopt situ steam generating process (ISSG) to form the cushion oxide layer 150 covering described shallow trench 140 surface.
Described situ steam generating process is wet-oxygen oxidation technique, and oxidation rate is fast.In an embodiment of the present invention, the thickness of the cushion oxide layer 150 formed is 50-200 dust, and the time that the cushion oxide layer 150 adopting situ steam generating process to form described thickness uses is 1-10s.Because the reaction time is very short, only have 1-10s, so the oxygen in reacting gas is between described floating gate polysilicon layer 120 and tunnel oxide 110, and the amount spread between described tunnel oxide 110 and Semiconductor substrate 100 is little.And the oxygen therefore in reacting gas can not react with the Semiconductor substrate of described floating gate polysilicon layer and shallow trench both sides, thus avoid because the Semiconductor substrate 100 of the oxygen in reacting gas and shallow trench 140 both sides, and floating gate polysilicon layer 120 reacts generation oxide, and therefore improve the homogeneity of the thickness of tunnel oxide 110.
In the prior art, adopt the technique of thermal oxidation to form cushion oxide layer 150, cushion oxide layer 150 thickness formed is 50-200 dust.The time used adopting the technique of thermal oxidation to form the cushion oxide layer 150 of described thickness is 5-6 hour.Because the formation speed of oxide layer is very slow, the oxygen in reacting gas is diffused between described floating gate polysilicon layer 120 and tunnel oxide 110 so can substantially pass the very little oxide layer of formed thickness, and between described tunnel oxide 110 and Semiconductor substrate 100, and with the Semiconductor substrate 100 of shallow trench 140 both sides, and floating gate polysilicon layer 120 reacts generation oxide, thus tunnel oxide 110 is caused to increase near shallow trench 140 segment thickness.The increase of tunnel oxide 110 thickness can cause the electric capacity between floating gate polysilicon layer 120 and Semiconductor substrate 100 to reduce, thus reduce control gate and source, leakage to the coupling coefficient of floating boom, the programming of device and efficiency of erasing are reduced, and the read current after causing device to be wiped reduces, and reduces the operation window of memory device.
In one embodiment of the invention, the concrete technological parameter of situ steam generating process is: temperature is 900 degree to 1200 degree, and reacting gas is H
2, 0
2with N
2mist, mixed gas flow is 0.1SLM to 10SLM, and original position distillation reaction pressure is 0.1Torr to 50Torr.
In a preferred embodiment of the invention, the concrete technological parameter of situ steam generating process is: temperature 1000 degree, and mixed gas flow is 0.1SLM to 10SLM, and reaction pressure is 0.1Torr to 50Torr, the cushion oxide layer 150 formed under these conditions is finer and close, and isolation effect is better.
With reference to figure 8, perform step S104, form the spacer medium layer 160 of filling full described shallow trench 140.
Described spacer medium layer 160 forms fleet plough groove isolation structure 160 for filling described shallow trench 140, and the material of described spacer medium layer 160 is silica, and the formation process of described spacer medium layer 160 is chemical vapor deposition method.Because the technique forming described spacer medium layer 160 is well known to those skilled in the art, do not repeat them here.
The step forming spacer medium layer 160 also comprises, and adopt and carry out smoothly managing to spacer medium layer 160 everywhere, until expose described hard mask layer 130, described planarization can adopt chemical mechanical milling tech.
To sum up, the present invention adopt situ steam generating process be formed at the shallow trench in Semiconductor substrate surface formed cushion oxide layer.Because the deposition velocity that employing situ steam generating process forms described cushion oxide layer is fast, required sedimentation time is short, so the diffusion relative to the Semiconductor substrate of described floating gate polysilicon layer and shallow trench both sides of oxygen in reacting gas can be reduced, and the oxidation reaction between the oxygen therefore reduced in reacting gas and the Semiconductor substrate of described floating gate polysilicon layer and shallow trench both sides, thus improve the homogeneity of the thickness of tunnel oxide.Effective " smiling face " problem improving the floating gate tunneling oxide layer that traditional handicraft is brought, improves the efficiency of write and erasing.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (9)
1., for a formation method for the fleet plough groove isolation structure of flash memory, it is characterized in that, comprising:
There is provided Semiconductor substrate, described semiconductor substrate surface is formed with tunnel oxide and floating gate polysilicon layer successively;
Form hard mask layer on described floating gate polysilicon layer surface, and etch described floating gate polysilicon layer, tunnel oxide, Semiconductor substrate successively, in described Semiconductor substrate, form shallow trench;
Adopt situ steam generating process to form the cushion oxide layer covering described shallow trench surface, the reaction time of described situ steam generating process is 1-10s, and the temperature forming described cushion oxide layer is 900 degree to 1200 degree;
Form the spacer medium layer of filling full described shallow trench.
2., according to the formation method of the fleet plough groove isolation structure for flash memory of claim 1, it is characterized in that, the process pressure of described situ steam generating process is 0.1Torr to 100Torr, and reacting gas is H
2, O
2with N
2mist, mixed gas flow is 0.1SLM to 10SLM.
3., according to the formation method of the fleet plough groove isolation structure for flash memory of claim 1, it is characterized in that, the thickness of described tunnel oxide is 70-120 dust.
4., according to the formation method of the fleet plough groove isolation structure for flash memory of claim 1, it is characterized in that, the formation process of described tunnel oxide is dry method thermal oxide growth.
5. according to the formation method of the fleet plough groove isolation structure for flash memory of claim 1, it is characterized in that, the technique forming the spacer medium layer of filling full described shallow trench is chemical vapor deposition method.
6., according to the formation method of the fleet plough groove isolation structure for flash memory of claim 5, it is characterized in that, the process pressure of described chemical vapor deposition generating process is 0.1Torr to 100Torr, and reacting gas is SiH
4with O
2mist, SiH
4with O
2mist gas flow be 0.1SLM to 50SLM.
7., according to the formation method of the fleet plough groove isolation structure for flash memory of claim 1, it is characterized in that, the thickness of described cushion oxide layer is 50-200 dust.
8., according to the formation method of the fleet plough groove isolation structure for flash memory of claim 1, it is characterized in that, the depositing operation of described floating gate polysilicon layer is chemical vapour deposition technique.
9., according to the formation method of the fleet plough groove isolation structure for flash memory of claim 1, it is characterized in that, the thickness of described floating gate polysilicon layer is 100-1000 dust.
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| CN103441075A (en) * | 2013-08-02 | 2013-12-11 | 上海华力微电子有限公司 | Method for manufacturing floating gate MOS transistor |
| CN105990249A (en) * | 2015-02-27 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure formation method |
| CN109309123B (en) * | 2017-07-28 | 2020-11-10 | 联华电子股份有限公司 | Semiconductor element and manufacturing method thereof |
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| CN101515570A (en) * | 2008-02-22 | 2009-08-26 | 旺宏电子股份有限公司 | Inverted t-shaped floating gate memory and method for fabricating the same |
| CN101572230A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for improving thickness consistency of oxide layer on side wall of grid electrode and method for manufacturing grid electrode |
| CN102044498A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Formation method for split gate storage device |
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| KR100645196B1 (en) * | 2005-03-10 | 2006-11-10 | 주식회사 하이닉스반도체 | Method of forming gate of a flash memory device |
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| CN101515570A (en) * | 2008-02-22 | 2009-08-26 | 旺宏电子股份有限公司 | Inverted t-shaped floating gate memory and method for fabricating the same |
| CN101572230A (en) * | 2008-04-30 | 2009-11-04 | 中芯国际集成电路制造(北京)有限公司 | Method for improving thickness consistency of oxide layer on side wall of grid electrode and method for manufacturing grid electrode |
| CN102044498A (en) * | 2009-10-20 | 2011-05-04 | 中芯国际集成电路制造(上海)有限公司 | Formation method for split gate storage device |
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